tjh.dev
Linux kernel mirror (for testing)
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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * max22007.c - MAX22007 DAC driver
4 *
5 * Driver for Analog Devices MAX22007 Digital to Analog Converter.
6 *
7 * Copyright (c) 2026 Analog Devices Inc.
8 */
9
10#include <linux/bitfield.h>
11#include <linux/bits.h>
12#include <linux/crc8.h>
13#include <linux/delay.h>
14#include <linux/dev_printk.h>
15#include <linux/device/devres.h>
16#include <linux/err.h>
17#include <linux/errno.h>
18#include <linux/gpio/consumer.h>
19#include <linux/iio/iio.h>
20#include <linux/kstrtox.h>
21#include <linux/minmax.h>
22#include <linux/mod_devicetable.h>
23#include <linux/module.h>
24#include <linux/property.h>
25#include <linux/regmap.h>
26#include <linux/regulator/consumer.h>
27#include <linux/slab.h>
28#include <linux/spi/spi.h>
29#include <linux/string.h>
30#include <linux/sysfs.h>
31#include <linux/types.h>
32
33#include <dt-bindings/iio/addac/adi,ad74413r.h>
34struct device;
35
36#define MAX22007_NUM_CHANNELS 4
37#define MAX22007_REV_ID_REG 0x00
38#define MAX22007_STAT_INTR_REG 0x01
39#define MAX22007_INTERRUPT_EN_REG 0x02
40#define MAX22007_CONFIG_REG 0x03
41#define MAX22007_CONTROL_REG 0x04
42#define MAX22007_CHANNEL_MODE_REG 0x05
43#define MAX22007_SOFT_RESET_REG 0x06
44#define MAX22007_DAC_CHANNEL_REG(ch) (0x07 + (ch))
45#define MAX22007_GPIO_CTRL_REG 0x0B
46#define MAX22007_GPIO_DATA_REG 0x0C
47#define MAX22007_GPI_EDGE_INT_CTRL_REG 0x0D
48#define MAX22007_GPI_INT_STATUS_REG 0x0E
49
50/* Channel mask definitions */
51#define MAX22007_CH_MODE_CH_MASK(ch) BIT(12 + (ch))
52#define MAX22007_CH_PWRON_CH_MASK(ch) BIT(8 + (ch))
53#define MAX22007_DAC_LATCH_MODE_MASK(ch) BIT(12 + (ch))
54#define MAX22007_LDAC_UPDATE_MASK(ch) BIT(12 + (ch))
55#define MAX22007_SW_RST_MASK BIT(8)
56#define MAX22007_SW_CLR_MASK BIT(12)
57#define MAX22007_SOFT_RESET_BITS_MASK (MAX22007_SW_RST_MASK | \
58 MAX22007_SW_CLR_MASK)
59#define MAX22007_DAC_DATA_MASK GENMASK(15, 4)
60#define MAX22007_DAC_MAX_RAW GENMASK(11, 0)
61#define MAX22007_CRC8_POLYNOMIAL 0x8C
62#define MAX22007_CRC_EN_MASK BIT(0)
63#define MAX22007_RW_MASK BIT(0)
64#define MAX22007_CRC_OVERHEAD 1
65#define MAX22007_NUM_SUPPLIES 3
66#define MAX22007_REF_MV 2500
67
68/* Field value preparation macros with masking */
69#define MAX22007_CH_PWR_VAL(ch, val) (((val) & 0x1) << (8 + (ch)))
70#define MAX22007_CH_MODE_VAL(ch, val) (((val) & 0x1) << (12 + (ch)))
71#define MAX22007_DAC_LATCH_MODE_VAL(ch, val) (((val) & 0x1) << (12 + (ch)))
72
73static u8 max22007_crc8_table[CRC8_TABLE_SIZE];
74
75static const char * const max22007_supply_names[MAX22007_NUM_SUPPLIES] = {
76 "vdd",
77 "hvdd",
78 "hvss",
79};
80
81struct max22007_state {
82 struct spi_device *spi;
83 struct regmap *regmap;
84 struct iio_chan_spec *iio_chans;
85 u8 tx_buf[4] __aligned(IIO_DMA_MINALIGN);
86 u8 rx_buf[4];
87};
88
89static int max22007_spi_read(void *context, const void *reg, size_t reg_size,
90 void *val, size_t val_size)
91{
92 struct max22007_state *st = context;
93 u8 calculated_crc, received_crc;
94 u8 rx_buf[4];
95 u8 reg_byte;
96 int ret;
97
98 if (reg_size != 1)
99 return -EINVAL;
100
101 if (val_size == 0 || val_size > 3)
102 return -EINVAL;
103
104 memcpy(®_byte, reg, 1);
105
106 ret = spi_write_then_read(st->spi, ®_byte, 1, rx_buf,
107 val_size + MAX22007_CRC_OVERHEAD);
108 if (ret) {
109 dev_err(&st->spi->dev, "SPI transfer failed: %d\n", ret);
110 return ret;
111 }
112
113 calculated_crc = crc8(max22007_crc8_table, ®_byte, 1, 0x00);
114 calculated_crc = crc8(max22007_crc8_table, rx_buf, 2, calculated_crc);
115 received_crc = rx_buf[val_size];
116
117 if (calculated_crc != received_crc) {
118 dev_err(&st->spi->dev, "CRC mismatch on read register %02x\n", reg_byte);
119 return -EIO;
120 }
121
122 memcpy(val, rx_buf, val_size);
123
124 return 0;
125}
126
127static int max22007_spi_write(void *context, const void *data, size_t count)
128{
129 struct max22007_state *st = context;
130 struct spi_transfer xfer = {
131 .tx_buf = st->tx_buf,
132 .rx_buf = st->rx_buf,
133 };
134
135 if (count + MAX22007_CRC_OVERHEAD > sizeof(st->tx_buf))
136 return -EINVAL;
137
138 memset(st->tx_buf, 0, sizeof(st->tx_buf));
139
140 xfer.len = count + MAX22007_CRC_OVERHEAD;
141
142 memcpy(st->tx_buf, data, count);
143 st->tx_buf[count] = crc8(max22007_crc8_table, st->tx_buf,
144 sizeof(st->tx_buf) - 1, 0x00);
145
146 return spi_sync_transfer(st->spi, &xfer, 1);
147}
148
149static bool max22007_reg_readable(struct device *dev, unsigned int reg)
150{
151 switch (reg) {
152 case MAX22007_REV_ID_REG:
153 case MAX22007_STAT_INTR_REG:
154 case MAX22007_CONFIG_REG:
155 case MAX22007_CONTROL_REG:
156 case MAX22007_CHANNEL_MODE_REG:
157 case MAX22007_SOFT_RESET_REG:
158 case MAX22007_GPIO_CTRL_REG:
159 case MAX22007_GPIO_DATA_REG:
160 case MAX22007_GPI_EDGE_INT_CTRL_REG:
161 case MAX22007_GPI_INT_STATUS_REG:
162 return true;
163 case MAX22007_DAC_CHANNEL_REG(0) ... MAX22007_DAC_CHANNEL_REG(MAX22007_NUM_CHANNELS - 1):
164 return true;
165 default:
166 return false;
167 }
168}
169
170static bool max22007_reg_writable(struct device *dev, unsigned int reg)
171{
172 switch (reg) {
173 case MAX22007_CONFIG_REG:
174 case MAX22007_CONTROL_REG:
175 case MAX22007_CHANNEL_MODE_REG:
176 case MAX22007_SOFT_RESET_REG:
177 case MAX22007_GPIO_CTRL_REG:
178 case MAX22007_GPIO_DATA_REG:
179 case MAX22007_GPI_EDGE_INT_CTRL_REG:
180 return true;
181 case MAX22007_DAC_CHANNEL_REG(0) ... MAX22007_DAC_CHANNEL_REG(MAX22007_NUM_CHANNELS - 1):
182 return true;
183 default:
184 return false;
185 }
186}
187
188static const struct regmap_bus max22007_regmap_bus = {
189 .read = max22007_spi_read,
190 .write = max22007_spi_write,
191 .read_flag_mask = MAX22007_RW_MASK,
192 .reg_format_endian_default = REGMAP_ENDIAN_BIG,
193 .val_format_endian_default = REGMAP_ENDIAN_BIG,
194};
195
196static const struct regmap_config max22007_regmap_config = {
197 .reg_bits = 8,
198 .val_bits = 16,
199 .reg_shift = -1,
200 .readable_reg = max22007_reg_readable,
201 .writeable_reg = max22007_reg_writable,
202 .max_register = 0x0E,
203};
204
205static int max22007_write_channel_data(struct max22007_state *st,
206 unsigned int channel, int data)
207{
208 unsigned int reg_val;
209
210 if (data < 0 || data > MAX22007_DAC_MAX_RAW)
211 return -EINVAL;
212
213 reg_val = FIELD_PREP(MAX22007_DAC_DATA_MASK, data);
214
215 return regmap_write(st->regmap, MAX22007_DAC_CHANNEL_REG(channel), reg_val);
216}
217
218static int max22007_read_channel_data(struct max22007_state *st,
219 unsigned int channel, int *data)
220{
221 unsigned int reg_val;
222 int ret;
223
224 ret = regmap_read(st->regmap, MAX22007_DAC_CHANNEL_REG(channel), ®_val);
225 if (ret)
226 return ret;
227
228 *data = FIELD_GET(MAX22007_DAC_DATA_MASK, reg_val);
229
230 return 0;
231}
232
233static int max22007_read_raw(struct iio_dev *indio_dev,
234 struct iio_chan_spec const *chan,
235 int *val, int *val2, long mask)
236{
237 struct max22007_state *st = iio_priv(indio_dev);
238 int ret;
239
240 switch (mask) {
241 case IIO_CHAN_INFO_RAW:
242 ret = max22007_read_channel_data(st, chan->channel, val);
243 if (ret)
244 return ret;
245 return IIO_VAL_INT;
246 case IIO_CHAN_INFO_SCALE:
247 if (chan->type == IIO_VOLTAGE)
248 *val = 5 * MAX22007_REF_MV; /* 5 * Vref in mV */
249 else
250 *val = 25; /* Vref / (2 * Rsense) = MAX22007_REF_MV / 100 */
251 *val2 = 12; /* 12-bit DAC resolution */
252 return IIO_VAL_FRACTIONAL_LOG2;
253 default:
254 return -EINVAL;
255 }
256}
257
258static int max22007_write_raw(struct iio_dev *indio_dev,
259 struct iio_chan_spec const *chan,
260 int val, int val2, long mask)
261{
262 struct max22007_state *st = iio_priv(indio_dev);
263
264 switch (mask) {
265 case IIO_CHAN_INFO_RAW:
266 return max22007_write_channel_data(st, chan->channel, val);
267 default:
268 return -EINVAL;
269 }
270}
271
272static const struct iio_info max22007_info = {
273 .read_raw = max22007_read_raw,
274 .write_raw = max22007_write_raw,
275};
276
277static ssize_t max22007_read_dac_powerdown(struct iio_dev *indio_dev,
278 uintptr_t private,
279 const struct iio_chan_spec *chan,
280 char *buf)
281{
282 struct max22007_state *st = iio_priv(indio_dev);
283 unsigned int reg_val;
284 bool powerdown;
285 int ret;
286
287 ret = regmap_read(st->regmap, MAX22007_CHANNEL_MODE_REG, ®_val);
288 if (ret)
289 return ret;
290
291 powerdown = !(reg_val & MAX22007_CH_PWRON_CH_MASK(chan->channel));
292
293 return sysfs_emit(buf, "%d\n", powerdown);
294}
295
296static ssize_t max22007_write_dac_powerdown(struct iio_dev *indio_dev,
297 uintptr_t private,
298 const struct iio_chan_spec *chan,
299 const char *buf, size_t len)
300{
301 struct max22007_state *st = iio_priv(indio_dev);
302 bool powerdown;
303 int ret;
304
305 ret = kstrtobool(buf, &powerdown);
306 if (ret)
307 return ret;
308
309 ret = regmap_update_bits(st->regmap, MAX22007_CHANNEL_MODE_REG,
310 MAX22007_CH_PWRON_CH_MASK(chan->channel),
311 MAX22007_CH_PWR_VAL(chan->channel, powerdown ? 0 : 1));
312 if (ret)
313 return ret;
314
315 return len;
316}
317
318static const struct iio_chan_spec_ext_info max22007_ext_info[] = {
319 {
320 .name = "powerdown",
321 .read = max22007_read_dac_powerdown,
322 .write = max22007_write_dac_powerdown,
323 .shared = IIO_SEPARATE,
324 },
325 { }
326};
327
328static int max22007_parse_channel_cfg(struct max22007_state *st, u8 *num_channels)
329{
330 struct device *dev = &st->spi->dev;
331 int ret, num_chan;
332 int i = 0;
333 u32 reg;
334
335 num_chan = device_get_child_node_count(dev);
336 if (!num_chan)
337 return dev_err_probe(dev, -ENODEV, "no channels configured\n");
338
339 st->iio_chans = devm_kcalloc(dev, num_chan, sizeof(*st->iio_chans), GFP_KERNEL);
340 if (!st->iio_chans)
341 return -ENOMEM;
342
343 device_for_each_child_node_scoped(dev, child) {
344 u32 ch_func;
345 enum iio_chan_type chan_type;
346
347 ret = fwnode_property_read_u32(child, "reg", ®);
348 if (ret)
349 return dev_err_probe(dev, ret,
350 "failed to read reg property of %pfwP\n", child);
351
352 if (reg >= MAX22007_NUM_CHANNELS)
353 return dev_err_probe(dev, -EINVAL,
354 "reg out of range in %pfwP\n", child);
355
356 ret = fwnode_property_read_u32(child, "adi,ch-func", &ch_func);
357 if (ret)
358 return dev_err_probe(dev, ret,
359 "missing adi,ch-func property for %pfwP\n", child);
360
361 switch (ch_func) {
362 case CH_FUNC_VOLTAGE_OUTPUT:
363 chan_type = IIO_VOLTAGE;
364 break;
365 case CH_FUNC_CURRENT_OUTPUT:
366 chan_type = IIO_CURRENT;
367 break;
368 default:
369 return dev_err_probe(dev, -EINVAL,
370 "invalid adi,ch-func %u for %pfwP\n",
371 ch_func, child);
372 }
373
374 st->iio_chans[i++] = (struct iio_chan_spec) {
375 .output = 1,
376 .indexed = 1,
377 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
378 BIT(IIO_CHAN_INFO_SCALE),
379 .ext_info = max22007_ext_info,
380 .channel = reg,
381 .type = chan_type,
382 };
383
384 ret = regmap_update_bits(st->regmap, MAX22007_CHANNEL_MODE_REG,
385 MAX22007_CH_MODE_CH_MASK(reg),
386 MAX22007_CH_MODE_VAL(reg, ch_func - 1));
387 if (ret)
388 return ret;
389
390 /* Set DAC to transparent mode (immediate update) */
391 ret = regmap_update_bits(st->regmap, MAX22007_CONFIG_REG,
392 MAX22007_DAC_LATCH_MODE_MASK(reg),
393 MAX22007_DAC_LATCH_MODE_VAL(reg, 1));
394 if (ret)
395 return ret;
396 }
397
398 *num_channels = num_chan;
399
400 return 0;
401}
402
403static int max22007_probe(struct spi_device *spi)
404{
405 struct device *dev = &spi->dev;
406 struct gpio_desc *reset_gpio;
407 struct max22007_state *st;
408 struct iio_dev *indio_dev;
409 u8 num_channels;
410 int ret;
411
412 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
413 if (!indio_dev)
414 return -ENOMEM;
415
416 st = iio_priv(indio_dev);
417 st->spi = spi;
418
419 crc8_populate_lsb(max22007_crc8_table, MAX22007_CRC8_POLYNOMIAL);
420
421 st->regmap = devm_regmap_init(dev, &max22007_regmap_bus, st,
422 &max22007_regmap_config);
423 if (IS_ERR(st->regmap))
424 return dev_err_probe(dev, PTR_ERR(st->regmap),
425 "Failed to initialize regmap\n");
426
427 ret = devm_regulator_bulk_get_enable(dev, MAX22007_NUM_SUPPLIES,
428 max22007_supply_names);
429 if (ret)
430 return dev_err_probe(dev, ret, "Failed to get and enable regulators\n");
431
432 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
433 if (IS_ERR(reset_gpio))
434 return dev_err_probe(dev, PTR_ERR(reset_gpio),
435 "Failed to get reset GPIO\n");
436
437 if (reset_gpio) {
438 gpiod_set_value_cansleep(reset_gpio, 1);
439 usleep_range(1000, 5000);
440 gpiod_set_value_cansleep(reset_gpio, 0);
441 usleep_range(1000, 5000);
442 } else {
443 ret = regmap_write(st->regmap, MAX22007_SOFT_RESET_REG,
444 MAX22007_SOFT_RESET_BITS_MASK);
445 if (ret)
446 return ret;
447 }
448
449 ret = regmap_set_bits(st->regmap, MAX22007_CONFIG_REG,
450 MAX22007_CRC_EN_MASK);
451 if (ret)
452 return ret;
453
454 ret = max22007_parse_channel_cfg(st, &num_channels);
455 if (ret)
456 return ret;
457
458 indio_dev->info = &max22007_info;
459 indio_dev->modes = INDIO_DIRECT_MODE;
460 indio_dev->channels = st->iio_chans;
461 indio_dev->num_channels = num_channels;
462 indio_dev->name = "max22007";
463
464 return devm_iio_device_register(dev, indio_dev);
465}
466
467static const struct spi_device_id max22007_id[] = {
468 { "max22007" },
469 { }
470};
471MODULE_DEVICE_TABLE(spi, max22007_id);
472
473static const struct of_device_id max22007_of_match[] = {
474 { .compatible = "adi,max22007" },
475 { }
476};
477MODULE_DEVICE_TABLE(of, max22007_of_match);
478
479static struct spi_driver max22007_driver = {
480 .driver = {
481 .name = "max22007",
482 .of_match_table = max22007_of_match,
483 },
484 .probe = max22007_probe,
485 .id_table = max22007_id,
486};
487module_spi_driver(max22007_driver);
488
489MODULE_AUTHOR("Janani Sunil <janani.sunil@analog.com>");
490MODULE_DESCRIPTION("Analog Devices MAX22007 DAC");
491MODULE_LICENSE("GPL");