tjh.dev
Linux kernel mirror (for testing)
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linux
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Synopsys DesignWare I2C adapter driver.
4 *
5 * Based on the TI DAVINCI I2C adapter driver.
6 *
7 * Copyright (C) 2006 Texas Instruments.
8 * Copyright (C) 2007 MontaVista Software Inc.
9 * Copyright (C) 2009 Provigent Ltd.
10 */
11
12#include <linux/bits.h>
13#include <linux/completion.h>
14#include <linux/errno.h>
15#include <linux/i2c.h>
16#include <linux/irqreturn.h>
17#include <linux/pm.h>
18#include <linux/regmap.h>
19#include <linux/types.h>
20
21#define DW_IC_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | \
22 I2C_FUNC_SMBUS_BYTE | \
23 I2C_FUNC_SMBUS_BYTE_DATA | \
24 I2C_FUNC_SMBUS_WORD_DATA | \
25 I2C_FUNC_SMBUS_BLOCK_DATA | \
26 I2C_FUNC_SMBUS_I2C_BLOCK)
27
28#define DW_IC_CON_MASTER BIT(0)
29#define DW_IC_CON_SPEED_STD (1 << 1)
30#define DW_IC_CON_SPEED_FAST (2 << 1)
31#define DW_IC_CON_SPEED_HIGH (3 << 1)
32#define DW_IC_CON_SPEED_MASK GENMASK(2, 1)
33#define DW_IC_CON_10BITADDR_SLAVE BIT(3)
34#define DW_IC_CON_10BITADDR_MASTER BIT(4)
35#define DW_IC_CON_RESTART_EN BIT(5)
36#define DW_IC_CON_SLAVE_DISABLE BIT(6)
37#define DW_IC_CON_STOP_DET_IFADDRESSED BIT(7)
38#define DW_IC_CON_TX_EMPTY_CTRL BIT(8)
39#define DW_IC_CON_RX_FIFO_FULL_HLD_CTRL BIT(9)
40#define DW_IC_CON_BUS_CLEAR_CTRL BIT(11)
41
42#define DW_IC_DATA_CMD_DAT GENMASK(7, 0)
43#define DW_IC_DATA_CMD_FIRST_DATA_BYTE BIT(11)
44
45/*
46 * Register access parameters
47 */
48#define DW_IC_REG_STEP_BYTES 2
49#define DW_IC_REG_WORD_SHIFT 16
50
51/*
52 * FIFO depth configuration
53 */
54#define DW_IC_FIFO_TX_FIELD GENMASK(23, 16)
55#define DW_IC_FIFO_RX_FIELD GENMASK(15, 8)
56#define DW_IC_FIFO_MIN_DEPTH 2
57
58/*
59 * Registers offset
60 */
61#define DW_IC_CON 0x00
62#define DW_IC_TAR 0x04
63#define DW_IC_SAR 0x08
64#define DW_IC_DATA_CMD 0x10
65#define DW_IC_SS_SCL_HCNT 0x14
66#define DW_IC_SS_SCL_LCNT 0x18
67#define DW_IC_FS_SCL_HCNT 0x1c
68#define DW_IC_FS_SCL_LCNT 0x20
69#define DW_IC_HS_SCL_HCNT 0x24
70#define DW_IC_HS_SCL_LCNT 0x28
71#define DW_IC_INTR_STAT 0x2c
72#define DW_IC_INTR_MASK 0x30
73#define DW_IC_RAW_INTR_STAT 0x34
74#define DW_IC_RX_TL 0x38
75#define DW_IC_TX_TL 0x3c
76#define DW_IC_CLR_INTR 0x40
77#define DW_IC_CLR_RX_UNDER 0x44
78#define DW_IC_CLR_RX_OVER 0x48
79#define DW_IC_CLR_TX_OVER 0x4c
80#define DW_IC_CLR_RD_REQ 0x50
81#define DW_IC_CLR_TX_ABRT 0x54
82#define DW_IC_CLR_RX_DONE 0x58
83#define DW_IC_CLR_ACTIVITY 0x5c
84#define DW_IC_CLR_STOP_DET 0x60
85#define DW_IC_CLR_START_DET 0x64
86#define DW_IC_CLR_GEN_CALL 0x68
87#define DW_IC_ENABLE 0x6c
88#define DW_IC_STATUS 0x70
89#define DW_IC_TXFLR 0x74
90#define DW_IC_RXFLR 0x78
91#define DW_IC_SDA_HOLD 0x7c
92#define DW_IC_TX_ABRT_SOURCE 0x80
93#define DW_IC_ENABLE_STATUS 0x9c
94#define DW_IC_CLR_RESTART_DET 0xa8
95#define DW_IC_SMBUS_INTR_MASK 0xcc
96#define DW_IC_COMP_PARAM_1 0xf4
97#define DW_IC_COMP_VERSION 0xf8
98#define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A /* "111*" == v1.11* */
99#define DW_IC_COMP_TYPE 0xfc
100#define DW_IC_COMP_TYPE_VALUE 0x44570140 /* "DW" + 0x0140 */
101
102#define DW_IC_INTR_RX_UNDER BIT(0)
103#define DW_IC_INTR_RX_OVER BIT(1)
104#define DW_IC_INTR_RX_FULL BIT(2)
105#define DW_IC_INTR_TX_OVER BIT(3)
106#define DW_IC_INTR_TX_EMPTY BIT(4)
107#define DW_IC_INTR_RD_REQ BIT(5)
108#define DW_IC_INTR_TX_ABRT BIT(6)
109#define DW_IC_INTR_RX_DONE BIT(7)
110#define DW_IC_INTR_ACTIVITY BIT(8)
111#define DW_IC_INTR_STOP_DET BIT(9)
112#define DW_IC_INTR_START_DET BIT(10)
113#define DW_IC_INTR_GEN_CALL BIT(11)
114#define DW_IC_INTR_RESTART_DET BIT(12)
115#define DW_IC_INTR_MST_ON_HOLD BIT(13)
116
117#define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
118 DW_IC_INTR_TX_ABRT | \
119 DW_IC_INTR_STOP_DET)
120#define DW_IC_INTR_MASTER_MASK (DW_IC_INTR_DEFAULT_MASK | \
121 DW_IC_INTR_TX_EMPTY)
122#define DW_IC_INTR_SLAVE_MASK (DW_IC_INTR_DEFAULT_MASK | \
123 DW_IC_INTR_RX_UNDER | \
124 DW_IC_INTR_RD_REQ)
125
126#define DW_IC_ENABLE_ENABLE BIT(0)
127#define DW_IC_ENABLE_ABORT BIT(1)
128
129#define DW_IC_STATUS_ACTIVITY BIT(0)
130#define DW_IC_STATUS_TFE BIT(2)
131#define DW_IC_STATUS_RFNE BIT(3)
132#define DW_IC_STATUS_MASTER_ACTIVITY BIT(5)
133#define DW_IC_STATUS_SLAVE_ACTIVITY BIT(6)
134#define DW_IC_STATUS_MASTER_HOLD_TX_FIFO_EMPTY BIT(7)
135
136#define DW_IC_SDA_HOLD_RX_SHIFT 16
137#define DW_IC_SDA_HOLD_RX_MASK GENMASK(23, 16)
138
139#define DW_IC_ERR_TX_ABRT 0x1
140
141#define DW_IC_TAR_10BITADDR_MASTER BIT(12)
142
143#define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH (BIT(2) | BIT(3))
144#define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK GENMASK(3, 2)
145
146/*
147 * Sofware status flags
148 */
149#define STATUS_ACTIVE BIT(0)
150#define STATUS_WRITE_IN_PROGRESS BIT(1)
151#define STATUS_READ_IN_PROGRESS BIT(2)
152#define STATUS_MASK GENMASK(2, 0)
153
154/*
155 * operation modes
156 */
157#define DW_IC_MASTER 0
158#define DW_IC_SLAVE 1
159
160/*
161 * Hardware abort codes from the DW_IC_TX_ABRT_SOURCE register.
162 *
163 * Only expected abort codes are listed here,
164 * refer to the datasheet for the full list.
165 */
166#define ABRT_7B_ADDR_NOACK 0
167#define ABRT_10ADDR1_NOACK 1
168#define ABRT_10ADDR2_NOACK 2
169#define ABRT_TXDATA_NOACK 3
170#define ABRT_GCALL_NOACK 4
171#define ABRT_GCALL_READ 5
172#define ABRT_SBYTE_ACKDET 7
173#define ABRT_SBYTE_NORSTRT 9
174#define ABRT_10B_RD_NORSTRT 10
175#define ABRT_MASTER_DIS 11
176#define ARB_LOST 12
177#define ABRT_SLAVE_FLUSH_TXFIFO 13
178#define ABRT_SLAVE_ARBLOST 14
179#define ABRT_SLAVE_RD_INTX 15
180
181#define DW_IC_TX_ABRT_7B_ADDR_NOACK BIT(ABRT_7B_ADDR_NOACK)
182#define DW_IC_TX_ABRT_10ADDR1_NOACK BIT(ABRT_10ADDR1_NOACK)
183#define DW_IC_TX_ABRT_10ADDR2_NOACK BIT(ABRT_10ADDR2_NOACK)
184#define DW_IC_TX_ABRT_TXDATA_NOACK BIT(ABRT_TXDATA_NOACK)
185#define DW_IC_TX_ABRT_GCALL_NOACK BIT(ABRT_GCALL_NOACK)
186#define DW_IC_TX_ABRT_GCALL_READ BIT(ABRT_GCALL_READ)
187#define DW_IC_TX_ABRT_SBYTE_ACKDET BIT(ABRT_SBYTE_ACKDET)
188#define DW_IC_TX_ABRT_SBYTE_NORSTRT BIT(ABRT_SBYTE_NORSTRT)
189#define DW_IC_TX_ABRT_10B_RD_NORSTRT BIT(ABRT_10B_RD_NORSTRT)
190#define DW_IC_TX_ABRT_MASTER_DIS BIT(ABRT_MASTER_DIS)
191#define DW_IC_TX_ARB_LOST BIT(ARB_LOST)
192#define DW_IC_RX_ABRT_SLAVE_RD_INTX BIT(ABRT_SLAVE_RD_INTX)
193#define DW_IC_RX_ABRT_SLAVE_ARBLOST BIT(ABRT_SLAVE_ARBLOST)
194#define DW_IC_RX_ABRT_SLAVE_FLUSH_TXFIFO BIT(ABRT_SLAVE_FLUSH_TXFIFO)
195
196#define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
197 DW_IC_TX_ABRT_10ADDR1_NOACK | \
198 DW_IC_TX_ABRT_10ADDR2_NOACK | \
199 DW_IC_TX_ABRT_TXDATA_NOACK | \
200 DW_IC_TX_ABRT_GCALL_NOACK)
201
202struct clk;
203struct device;
204struct reset_control;
205
206/**
207 * struct dw_i2c_dev - private i2c-designware data
208 * @dev: driver model device node
209 * @map: IO registers map
210 * @sysmap: System controller registers map
211 * @base: IO registers pointer
212 * @ext: Extended IO registers pointer
213 * @cmd_complete: tx completion indicator
214 * @clk: input reference clock
215 * @pclk: clock required to access the registers
216 * @rst: optional reset for the controller
217 * @slave: represent an I2C slave device
218 * @get_clk_rate_khz: callback to retrieve IP specific bus speed
219 * @cmd_err: run time hardware error code
220 * @msgs: points to an array of messages currently being transferred
221 * @msgs_num: the number of elements in msgs
222 * @msg_write_idx: the element index of the current tx message in the msgs array
223 * @tx_buf_len: the length of the current tx buffer
224 * @tx_buf: the current tx buffer
225 * @msg_read_idx: the element index of the current rx message in the msgs array
226 * @rx_buf_len: the length of the current rx buffer
227 * @rx_buf: the current rx buffer
228 * @msg_err: error status of the current transfer
229 * @status: i2c master status, one of STATUS_*
230 * @abort_source: copy of the TX_ABRT_SOURCE register
231 * @sw_mask: SW mask of DW_IC_INTR_MASK used in polling mode
232 * @irq: interrupt number for the i2c master
233 * @flags: platform specific flags like type of IO accessors or model
234 * @adapter: i2c subsystem adapter node
235 * @functionality: I2C_FUNC_* ORed bits to reflect what controller does support
236 * @master_cfg: configuration for the master device
237 * @slave_cfg: configuration for the slave device
238 * @tx_fifo_depth: depth of the hardware tx fifo
239 * @rx_fifo_depth: depth of the hardware rx fifo
240 * @rx_outstanding: current master-rx elements in tx fifo
241 * @timings: bus clock frequency, SDA hold and other timings
242 * @sda_hold_time: SDA hold value
243 * @ss_hcnt: standard speed HCNT value
244 * @ss_lcnt: standard speed LCNT value
245 * @fs_hcnt: fast speed HCNT value
246 * @fs_lcnt: fast speed LCNT value
247 * @fp_hcnt: fast plus HCNT value
248 * @fp_lcnt: fast plus LCNT value
249 * @hs_hcnt: high speed HCNT value
250 * @hs_lcnt: high speed LCNT value
251 * @acquire_lock: function to acquire a hardware lock on the bus
252 * @release_lock: function to release a hardware lock on the bus
253 * @semaphore_idx: Index of table with semaphore type attached to the bus. It's
254 * -1 if there is no semaphore.
255 * @shared_with_punit: true if this bus is shared with the SoC's PUNIT
256 * @set_sda_hold_time: callback to retrieve IP specific SDA hold timing
257 * @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE
258 * @rinfo: I²C GPIO recovery information
259 * @bus_capacitance_pF: bus capacitance in picofarads
260 * @clk_freq_optimized: if this value is true, it means the hardware reduces
261 * its internal clock frequency by reducing the internal latency required
262 * to generate the high period and low period of SCL line.
263 * @emptyfifo_hold_master: true if the controller acting as master holds
264 * the clock when the Tx FIFO is empty instead of emitting a stop.
265 *
266 * HCNT and LCNT parameters can be used if the platform knows more accurate
267 * values than the one computed based only on the input clock frequency.
268 * Leave them to be %0 if not used.
269 */
270struct dw_i2c_dev {
271 struct device *dev;
272 struct regmap *map;
273 struct regmap *sysmap;
274 void __iomem *base;
275 void __iomem *ext;
276 struct completion cmd_complete;
277 struct clk *clk;
278 struct clk *pclk;
279 struct reset_control *rst;
280 struct i2c_client *slave;
281 u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev);
282 int cmd_err;
283 struct i2c_msg *msgs;
284 int msgs_num;
285 int msg_write_idx;
286 u32 tx_buf_len;
287 u8 *tx_buf;
288 int msg_read_idx;
289 u32 rx_buf_len;
290 u8 *rx_buf;
291 int msg_err;
292 unsigned int status;
293 unsigned int abort_source;
294 unsigned int sw_mask;
295 int irq;
296 u32 flags;
297 struct i2c_adapter adapter;
298 u32 functionality;
299 u32 master_cfg;
300 u32 slave_cfg;
301 unsigned int tx_fifo_depth;
302 unsigned int rx_fifo_depth;
303 int rx_outstanding;
304 struct i2c_timings timings;
305 u32 sda_hold_time;
306 u16 ss_hcnt;
307 u16 ss_lcnt;
308 u16 fs_hcnt;
309 u16 fs_lcnt;
310 u16 fp_hcnt;
311 u16 fp_lcnt;
312 u16 hs_hcnt;
313 u16 hs_lcnt;
314 int (*acquire_lock)(void);
315 void (*release_lock)(void);
316 int semaphore_idx;
317 bool shared_with_punit;
318 int (*set_sda_hold_time)(struct dw_i2c_dev *dev);
319 int mode;
320 struct i2c_bus_recovery_info rinfo;
321 u32 bus_capacitance_pF;
322 bool clk_freq_optimized;
323 bool emptyfifo_hold_master;
324};
325
326#define ACCESS_INTR_MASK BIT(0)
327#define ACCESS_NO_IRQ_SUSPEND BIT(1)
328#define ARBITRATION_SEMAPHORE BIT(2)
329#define ACCESS_POLLING BIT(3)
330
331#define MODEL_AMD_NAVI_GPU BIT(10)
332#define MODEL_WANGXUN_SP BIT(11)
333#define MODEL_MASK GENMASK(11, 8)
334
335/*
336 * Enable UCSI interrupt by writing 0xd at register
337 * offset 0x474 specified in hardware specification.
338 */
339#define AMD_UCSI_INTR_REG 0x474
340#define AMD_UCSI_INTR_EN 0xd
341
342#define TXGBE_TX_FIFO_DEPTH 4
343#define TXGBE_RX_FIFO_DEPTH 1
344
345struct i2c_dw_semaphore_callbacks {
346 int (*probe)(struct dw_i2c_dev *dev);
347};
348
349u32 i2c_dw_scl_hcnt(struct dw_i2c_dev *dev, unsigned int reg, u32 ic_clk,
350 u32 tSYMBOL, u32 tf, int offset);
351u32 i2c_dw_scl_lcnt(struct dw_i2c_dev *dev, unsigned int reg, u32 ic_clk,
352 u32 tLOW, u32 tf, int offset);
353u32 i2c_dw_clk_rate(struct dw_i2c_dev *dev);
354int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare);
355int i2c_dw_acquire_lock(struct dw_i2c_dev *dev);
356void i2c_dw_release_lock(struct dw_i2c_dev *dev);
357int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev);
358int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev);
359u32 i2c_dw_func(struct i2c_adapter *adap);
360irqreturn_t i2c_dw_isr_master(struct dw_i2c_dev *dev);
361
362extern const struct dev_pm_ops i2c_dw_dev_pm_ops;
363
364static inline void __i2c_dw_enable(struct dw_i2c_dev *dev)
365{
366 dev->status |= STATUS_ACTIVE;
367 regmap_write(dev->map, DW_IC_ENABLE, 1);
368}
369
370static inline void __i2c_dw_disable_nowait(struct dw_i2c_dev *dev)
371{
372 regmap_write(dev->map, DW_IC_ENABLE, 0);
373 dev->status &= ~STATUS_ACTIVE;
374}
375
376static inline void __i2c_dw_write_intr_mask(struct dw_i2c_dev *dev,
377 unsigned int intr_mask)
378{
379 unsigned int val = dev->flags & ACCESS_POLLING ? 0 : intr_mask;
380
381 regmap_write(dev->map, DW_IC_INTR_MASK, val);
382 dev->sw_mask = intr_mask;
383}
384
385static inline void __i2c_dw_read_intr_mask(struct dw_i2c_dev *dev,
386 unsigned int *intr_mask)
387{
388 if (!(dev->flags & ACCESS_POLLING))
389 regmap_read(dev->map, DW_IC_INTR_MASK, intr_mask);
390 else
391 *intr_mask = dev->sw_mask;
392}
393
394void __i2c_dw_disable(struct dw_i2c_dev *dev);
395void i2c_dw_disable(struct dw_i2c_dev *dev);
396
397extern void i2c_dw_configure_master(struct dw_i2c_dev *dev);
398extern int i2c_dw_probe_master(struct dw_i2c_dev *dev);
399
400int i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num);
401
402#if IS_ENABLED(CONFIG_I2C_SLAVE)
403extern void i2c_dw_configure_slave(struct dw_i2c_dev *dev);
404irqreturn_t i2c_dw_isr_slave(struct dw_i2c_dev *dev);
405int i2c_dw_reg_slave(struct i2c_client *client);
406int i2c_dw_unreg_slave(struct i2c_client *client);
407#else
408static inline void i2c_dw_configure_slave(struct dw_i2c_dev *dev) { }
409static inline irqreturn_t i2c_dw_isr_slave(struct dw_i2c_dev *dev) { return IRQ_NONE; }
410#endif
411
412static inline void i2c_dw_configure(struct dw_i2c_dev *dev)
413{
414 i2c_dw_configure_slave(dev);
415 i2c_dw_configure_master(dev);
416}
417
418int i2c_dw_probe(struct dw_i2c_dev *dev);
419int i2c_dw_init(struct dw_i2c_dev *dev);
420void i2c_dw_set_mode(struct dw_i2c_dev *dev, int mode);
421
422#if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL)
423int i2c_dw_baytrail_probe_lock_support(struct dw_i2c_dev *dev);
424#endif
425
426#if IS_ENABLED(CONFIG_I2C_DESIGNWARE_AMDPSP)
427int i2c_dw_amdpsp_probe_lock_support(struct dw_i2c_dev *dev);
428#endif
429
430int i2c_dw_fw_parse_and_configure(struct dw_i2c_dev *dev);