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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h/17h
4 * processor hardware monitoring
5 *
6 * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
7 * Copyright (c) 2020 Guenter Roeck <linux@roeck-us.net>
8 *
9 * Implementation notes:
10 * - CCD register address information as well as the calculation to
11 * convert raw register values is from https://github.com/ocerman/zenpower.
12 * The information is not confirmed from chip datasheets, but experiments
13 * suggest that it provides reasonable temperature values.
14 */
15
16#include <linux/bitops.h>
17#include <linux/err.h>
18#include <linux/hwmon.h>
19#include <linux/init.h>
20#include <linux/module.h>
21#include <linux/pci.h>
22#include <linux/pci_ids.h>
23#include <asm/amd/node.h>
24#include <asm/processor.h>
25
26MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
27MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
28MODULE_LICENSE("GPL");
29
30static bool force;
31module_param(force, bool, 0444);
32MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
33
34#ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
35#define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3
36#endif
37
38/* CPUID function 0x80000001, ebx */
39#define CPUID_PKGTYPE_MASK GENMASK(31, 28)
40#define CPUID_PKGTYPE_F 0x00000000
41#define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
42
43/* DRAM controller (PCI function 2) */
44#define REG_DCT0_CONFIG_HIGH 0x094
45#define DDR3_MODE BIT(8)
46
47/* miscellaneous (PCI function 3) */
48#define REG_HARDWARE_THERMAL_CONTROL 0x64
49#define HTC_ENABLE BIT(0)
50
51#define REG_REPORTED_TEMPERATURE 0xa4
52
53#define REG_NORTHBRIDGE_CAPABILITIES 0xe8
54#define NB_CAP_HTC BIT(10)
55
56/*
57 * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
58 * and REG_REPORTED_TEMPERATURE have been moved to
59 * D0F0xBC_xD820_0C64 [Hardware Temperature Control]
60 * D0F0xBC_xD820_0CA4 [Reported Temperature Control]
61 */
62#define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64
63#define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
64
65/* Common for Zen CPU families (Family 17h and 18h and 19h and 1Ah) */
66#define ZEN_REPORTED_TEMP_CTRL_BASE 0x00059800
67
68#define ZEN_CCD_TEMP(offset, x) (ZEN_REPORTED_TEMP_CTRL_BASE + \
69 (offset) + ((x) * 4))
70#define ZEN_CCD_TEMP_VALID BIT(11)
71#define ZEN_CCD_TEMP_MASK GENMASK(10, 0)
72
73#define ZEN_CUR_TEMP_SHIFT 21
74#define ZEN_CUR_TEMP_RANGE_SEL_MASK BIT(19)
75#define ZEN_CUR_TEMP_TJ_SEL_MASK GENMASK(17, 16)
76
77/*
78 * AMD's Industrial processor 3255 supports temperature from -40 deg to 105 deg Celsius.
79 * Use the model name to identify 3255 CPUs and set a flag to display negative temperature.
80 * Do not round off to zero for negative Tctl or Tdie values if the flag is set
81 */
82#define AMD_I3255_STR "3255"
83
84/*
85 * PCI Device IDs for AMD's Family 17h-based SOCs.
86 * Defining locally as IDs are not shared.
87 */
88#define PCI_DEVICE_ID_AMD_17H_M90H_DF_F3 0x1663
89
90/*
91 * PCI Device IDs for AMD's Family 1Ah-based SOCs.
92 * Defining locally as IDs are not shared.
93 */
94#define PCI_DEVICE_ID_AMD_1AH_M50H_DF_F3 0x12cb
95#define PCI_DEVICE_ID_AMD_1AH_M90H_DF_F3 0x127b
96
97struct k10temp_data {
98 struct pci_dev *pdev;
99 void (*read_htcreg)(struct pci_dev *pdev, u32 *regval);
100 void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
101 int temp_offset;
102 u32 temp_adjust_mask;
103 u32 show_temp;
104 bool is_zen;
105 u32 ccd_offset;
106 bool disp_negative;
107};
108
109#define TCTL_BIT 0
110#define TDIE_BIT 1
111#define TCCD_BIT(x) ((x) + 2)
112
113#define HAVE_TEMP(d, channel) ((d)->show_temp & BIT(channel))
114
115struct tctl_offset {
116 u8 model;
117 char const *id;
118 int offset;
119};
120
121static const struct tctl_offset tctl_offset_table[] = {
122 { 0x17, "AMD Ryzen 5 1600X", 20000 },
123 { 0x17, "AMD Ryzen 7 1700X", 20000 },
124 { 0x17, "AMD Ryzen 7 1800X", 20000 },
125 { 0x17, "AMD Ryzen 7 2700X", 10000 },
126 { 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */
127 { 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */
128};
129
130static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)
131{
132 pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
133}
134
135static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
136{
137 pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
138}
139
140static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
141 unsigned int base, int offset, u32 *val)
142{
143 pci_bus_write_config_dword(pdev->bus, devfn,
144 base, offset);
145 pci_bus_read_config_dword(pdev->bus, devfn,
146 base + 4, val);
147}
148
149static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval)
150{
151 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
152 F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
153}
154
155static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
156{
157 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
158 F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
159}
160
161static u16 amd_pci_dev_to_node_id(struct pci_dev *pdev)
162{
163 return PCI_SLOT(pdev->devfn) - AMD_NODE0_PCI_SLOT;
164}
165
166static void read_tempreg_nb_zen(struct pci_dev *pdev, u32 *regval)
167{
168 if (amd_smn_read(amd_pci_dev_to_node_id(pdev),
169 ZEN_REPORTED_TEMP_CTRL_BASE, regval))
170 *regval = 0;
171}
172
173static int read_ccd_temp_reg(struct k10temp_data *data, int ccd, u32 *regval)
174{
175 u16 node_id = amd_pci_dev_to_node_id(data->pdev);
176
177 return amd_smn_read(node_id, ZEN_CCD_TEMP(data->ccd_offset, ccd), regval);
178}
179
180static long get_raw_temp(struct k10temp_data *data)
181{
182 u32 regval;
183 long temp;
184
185 data->read_tempreg(data->pdev, ®val);
186 temp = (regval >> ZEN_CUR_TEMP_SHIFT) * 125;
187 if ((regval & data->temp_adjust_mask) ||
188 (regval & ZEN_CUR_TEMP_TJ_SEL_MASK) == ZEN_CUR_TEMP_TJ_SEL_MASK)
189 temp -= 49000;
190 return temp;
191}
192
193static const char *k10temp_temp_label[] = {
194 "Tctl",
195 "Tdie",
196 "Tccd1",
197 "Tccd2",
198 "Tccd3",
199 "Tccd4",
200 "Tccd5",
201 "Tccd6",
202 "Tccd7",
203 "Tccd8",
204 "Tccd9",
205 "Tccd10",
206 "Tccd11",
207 "Tccd12",
208};
209
210static int k10temp_read_labels(struct device *dev,
211 enum hwmon_sensor_types type,
212 u32 attr, int channel, const char **str)
213{
214 switch (type) {
215 case hwmon_temp:
216 *str = k10temp_temp_label[channel];
217 break;
218 default:
219 return -EOPNOTSUPP;
220 }
221 return 0;
222}
223
224static int k10temp_read_temp(struct device *dev, u32 attr, int channel,
225 long *val)
226{
227 struct k10temp_data *data = dev_get_drvdata(dev);
228 int ret = -EOPNOTSUPP;
229 u32 regval;
230
231 switch (attr) {
232 case hwmon_temp_input:
233 switch (channel) {
234 case 0: /* Tctl */
235 *val = get_raw_temp(data);
236 if (*val < 0 && !data->disp_negative)
237 *val = 0;
238 break;
239 case 1: /* Tdie */
240 *val = get_raw_temp(data) - data->temp_offset;
241 if (*val < 0 && !data->disp_negative)
242 *val = 0;
243 break;
244 case 2 ... 13: /* Tccd{1-12} */
245 ret = read_ccd_temp_reg(data, channel - 2, ®val);
246
247 if (ret)
248 return ret;
249
250 *val = (regval & ZEN_CCD_TEMP_MASK) * 125 - 49000;
251 break;
252 default:
253 return ret;
254 }
255 break;
256 case hwmon_temp_max:
257 *val = 70 * 1000;
258 break;
259 case hwmon_temp_crit:
260 data->read_htcreg(data->pdev, ®val);
261 *val = ((regval >> 16) & 0x7f) * 500 + 52000;
262 break;
263 case hwmon_temp_crit_hyst:
264 data->read_htcreg(data->pdev, ®val);
265 *val = (((regval >> 16) & 0x7f)
266 - ((regval >> 24) & 0xf)) * 500 + 52000;
267 break;
268 default:
269 return ret;
270 }
271 return 0;
272}
273
274static int k10temp_read(struct device *dev, enum hwmon_sensor_types type,
275 u32 attr, int channel, long *val)
276{
277 switch (type) {
278 case hwmon_temp:
279 return k10temp_read_temp(dev, attr, channel, val);
280 default:
281 return -EOPNOTSUPP;
282 }
283}
284
285static umode_t k10temp_is_visible(const void *drvdata,
286 enum hwmon_sensor_types type,
287 u32 attr, int channel)
288{
289 const struct k10temp_data *data = drvdata;
290 struct pci_dev *pdev = data->pdev;
291 u32 reg;
292
293 switch (type) {
294 case hwmon_temp:
295 switch (attr) {
296 case hwmon_temp_input:
297 if (!HAVE_TEMP(data, channel))
298 return 0;
299 break;
300 case hwmon_temp_max:
301 if (channel || data->is_zen)
302 return 0;
303 break;
304 case hwmon_temp_crit:
305 case hwmon_temp_crit_hyst:
306 if (channel || !data->read_htcreg)
307 return 0;
308
309 pci_read_config_dword(pdev,
310 REG_NORTHBRIDGE_CAPABILITIES,
311 ®);
312 if (!(reg & NB_CAP_HTC))
313 return 0;
314
315 data->read_htcreg(data->pdev, ®);
316 if (!(reg & HTC_ENABLE))
317 return 0;
318 break;
319 case hwmon_temp_label:
320 /* Show temperature labels only on Zen CPUs */
321 if (!data->is_zen || !HAVE_TEMP(data, channel))
322 return 0;
323 break;
324 default:
325 return 0;
326 }
327 break;
328 default:
329 return 0;
330 }
331 return 0444;
332}
333
334static bool has_erratum_319(struct pci_dev *pdev)
335{
336 u32 pkg_type, reg_dram_cfg;
337
338 if (boot_cpu_data.x86 != 0x10)
339 return false;
340
341 /*
342 * Erratum 319: The thermal sensor of Socket F/AM2+ processors
343 * may be unreliable.
344 */
345 pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
346 if (pkg_type == CPUID_PKGTYPE_F)
347 return true;
348 if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
349 return false;
350
351 /* DDR3 memory implies socket AM3, which is good */
352 pci_bus_read_config_dword(pdev->bus,
353 PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
354 REG_DCT0_CONFIG_HIGH, ®_dram_cfg);
355 if (reg_dram_cfg & DDR3_MODE)
356 return false;
357
358 /*
359 * Unfortunately it is possible to run a socket AM3 CPU with DDR2
360 * memory. We blacklist all the cores which do exist in socket AM2+
361 * format. It still isn't perfect, as RB-C2 cores exist in both AM2+
362 * and AM3 formats, but that's the best we can do.
363 */
364 return boot_cpu_data.x86_model < 4 ||
365 (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
366}
367
368static const struct hwmon_channel_info * const k10temp_info[] = {
369 HWMON_CHANNEL_INFO(temp,
370 HWMON_T_INPUT | HWMON_T_MAX |
371 HWMON_T_CRIT | HWMON_T_CRIT_HYST |
372 HWMON_T_LABEL,
373 HWMON_T_INPUT | HWMON_T_LABEL,
374 HWMON_T_INPUT | HWMON_T_LABEL,
375 HWMON_T_INPUT | HWMON_T_LABEL,
376 HWMON_T_INPUT | HWMON_T_LABEL,
377 HWMON_T_INPUT | HWMON_T_LABEL,
378 HWMON_T_INPUT | HWMON_T_LABEL,
379 HWMON_T_INPUT | HWMON_T_LABEL,
380 HWMON_T_INPUT | HWMON_T_LABEL,
381 HWMON_T_INPUT | HWMON_T_LABEL,
382 HWMON_T_INPUT | HWMON_T_LABEL,
383 HWMON_T_INPUT | HWMON_T_LABEL,
384 HWMON_T_INPUT | HWMON_T_LABEL,
385 HWMON_T_INPUT | HWMON_T_LABEL),
386 NULL
387};
388
389static const struct hwmon_ops k10temp_hwmon_ops = {
390 .is_visible = k10temp_is_visible,
391 .read = k10temp_read,
392 .read_string = k10temp_read_labels,
393};
394
395static const struct hwmon_chip_info k10temp_chip_info = {
396 .ops = &k10temp_hwmon_ops,
397 .info = k10temp_info,
398};
399
400static void k10temp_get_ccd_support(struct k10temp_data *data, int limit)
401{
402 u32 regval;
403 int i;
404
405 for (i = 0; i < limit; i++) {
406 /*
407 * Ignore inaccessible CCDs.
408 *
409 * Some systems will return a register value of 0, and the TEMP_VALID
410 * bit check below will naturally fail.
411 *
412 * Other systems will return a PCI_ERROR_RESPONSE (0xFFFFFFFF) for
413 * the register value. And this will incorrectly pass the TEMP_VALID
414 * bit check.
415 */
416 if (read_ccd_temp_reg(data, i, ®val))
417 continue;
418
419 if (regval & ZEN_CCD_TEMP_VALID)
420 data->show_temp |= BIT(TCCD_BIT(i));
421 }
422}
423
424static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
425{
426 int unreliable = has_erratum_319(pdev);
427 struct device *dev = &pdev->dev;
428 struct k10temp_data *data;
429 struct device *hwmon_dev;
430 int i;
431
432 if (unreliable) {
433 if (!force) {
434 dev_err(dev,
435 "unreliable CPU thermal sensor; monitoring disabled\n");
436 return -ENODEV;
437 }
438 dev_warn(dev,
439 "unreliable CPU thermal sensor; check erratum 319\n");
440 }
441
442 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
443 if (!data)
444 return -ENOMEM;
445
446 data->pdev = pdev;
447 data->show_temp |= BIT(TCTL_BIT); /* Always show Tctl */
448
449 if (boot_cpu_data.x86 == 0x17 &&
450 strstr(boot_cpu_data.x86_model_id, AMD_I3255_STR)) {
451 data->disp_negative = true;
452 }
453
454 data->is_zen = cpu_feature_enabled(X86_FEATURE_ZEN);
455 if (data->is_zen) {
456 data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
457 data->read_tempreg = read_tempreg_nb_zen;
458 } else if (boot_cpu_data.x86 == 0x15 &&
459 ((boot_cpu_data.x86_model & 0xf0) == 0x60 ||
460 (boot_cpu_data.x86_model & 0xf0) == 0x70)) {
461 data->read_htcreg = read_htcreg_nb_f15;
462 data->read_tempreg = read_tempreg_nb_f15;
463 } else {
464 data->read_htcreg = read_htcreg_pci;
465 data->read_tempreg = read_tempreg_pci;
466 }
467
468 if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
469 switch (boot_cpu_data.x86_model) {
470 case 0x1: /* Zen */
471 case 0x8: /* Zen+ */
472 case 0x11: /* Zen APU */
473 case 0x18: /* Zen+ APU */
474 data->ccd_offset = 0x154;
475 k10temp_get_ccd_support(data, 4);
476 break;
477 case 0x31: /* Zen2 Threadripper */
478 case 0x47: /* Cyan Skillfish */
479 case 0x60: /* Renoir */
480 case 0x68: /* Lucienne */
481 case 0x71: /* Zen2 */
482 data->ccd_offset = 0x154;
483 k10temp_get_ccd_support(data, 8);
484 break;
485 case 0xa0 ... 0xaf:
486 data->ccd_offset = 0x300;
487 k10temp_get_ccd_support(data, 8);
488 break;
489 }
490 } else if (boot_cpu_data.x86 == 0x19) {
491 switch (boot_cpu_data.x86_model) {
492 case 0x0 ... 0x1: /* Zen3 SP3/TR */
493 case 0x8: /* Zen3 TR Chagall */
494 case 0x21: /* Zen3 Ryzen Desktop */
495 case 0x50 ... 0x5f: /* Green Sardine */
496 data->ccd_offset = 0x154;
497 k10temp_get_ccd_support(data, 8);
498 break;
499 case 0x40 ... 0x4f: /* Yellow Carp */
500 data->ccd_offset = 0x300;
501 k10temp_get_ccd_support(data, 8);
502 break;
503 case 0x60 ... 0x6f:
504 case 0x70 ... 0x7f:
505 data->ccd_offset = 0x308;
506 k10temp_get_ccd_support(data, 8);
507 break;
508 case 0x10 ... 0x1f:
509 case 0xa0 ... 0xaf:
510 data->ccd_offset = 0x300;
511 k10temp_get_ccd_support(data, 12);
512 break;
513 }
514 } else if (boot_cpu_data.x86 == 0x1a) {
515 switch (boot_cpu_data.x86_model) {
516 case 0x40 ... 0x4f: /* Zen5 Ryzen Desktop */
517 data->ccd_offset = 0x308;
518 k10temp_get_ccd_support(data, 8);
519 break;
520 }
521 }
522
523 for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
524 const struct tctl_offset *entry = &tctl_offset_table[i];
525
526 if (boot_cpu_data.x86 == entry->model &&
527 strstr(boot_cpu_data.x86_model_id, entry->id)) {
528 data->show_temp |= BIT(TDIE_BIT); /* show Tdie */
529 data->temp_offset = entry->offset;
530 break;
531 }
532 }
533
534 hwmon_dev = devm_hwmon_device_register_with_info(dev, "k10temp", data,
535 &k10temp_chip_info,
536 NULL);
537 return PTR_ERR_OR_ZERO(hwmon_dev);
538}
539
540static const struct pci_device_id k10temp_id_table[] = {
541 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
542 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
543 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
544 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
545 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
546 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
547 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
548 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
549 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
550 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
551 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
552 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
553 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
554 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M40H_DF_F3) },
555 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
556 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
557 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M90H_DF_F3) },
558 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_MA0H_DF_F3) },
559 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
560 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) },
561 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
562 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
563 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M60H_DF_F3) },
564 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F3) },
565 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M78H_DF_F3) },
566 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M00H_DF_F3) },
567 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M20H_DF_F3) },
568 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M50H_DF_F3) },
569 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M60H_DF_F3) },
570 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M70H_DF_F3) },
571 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M90H_DF_F3) },
572 { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
573 {}
574};
575MODULE_DEVICE_TABLE(pci, k10temp_id_table);
576
577static struct pci_driver k10temp_driver = {
578 .name = "k10temp",
579 .id_table = k10temp_id_table,
580 .probe = k10temp_probe,
581};
582
583module_pci_driver(k10temp_driver);