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1/* SPDX-License-Identifier: MIT */ 2/* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6#ifndef _XE_PCODE_H_ 7#define _XE_PCODE_H_ 8 9#include <linux/types.h> 10 11struct drm_device; 12struct xe_device; 13struct xe_tile; 14 15void xe_pcode_init(struct xe_tile *tile); 16int xe_pcode_probe_early(struct xe_device *xe); 17int xe_pcode_ready(struct xe_device *xe, bool locked); 18int xe_pcode_init_min_freq_table(struct xe_tile *tile, u32 min_gt_freq, 19 u32 max_gt_freq); 20int xe_pcode_read(struct xe_tile *tile, u32 mbox, u32 *val, u32 *val1); 21int xe_pcode_write_timeout(struct xe_tile *tile, u32 mbox, u32 val, 22 int timeout_ms); 23int xe_pcode_write64_timeout(struct xe_tile *tile, u32 mbox, u32 data0, 24 u32 data1, int timeout); 25 26#define xe_pcode_write(tile, mbox, val) \ 27 xe_pcode_write_timeout(tile, mbox, val, 1) 28 29int xe_pcode_request(struct xe_tile *tile, u32 mbox, u32 request, 30 u32 reply_mask, u32 reply, int timeout_ms); 31 32#define PCODE_MBOX(mbcmd, param1, param2)\ 33 (FIELD_PREP(PCODE_MB_COMMAND, mbcmd)\ 34 | FIELD_PREP(PCODE_MB_PARAM1, param1)\ 35 | FIELD_PREP(PCODE_MB_PARAM2, param2)) 36 37/* Helpers with drm device */ 38int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1); 39int intel_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms); 40#define intel_pcode_write(drm, mbox, val) \ 41 intel_pcode_write_timeout((drm), (mbox), (val), 1) 42int intel_pcode_request(struct drm_device *drm, u32 mbox, u32 request, 43 u32 reply_mask, u32 reply, int timeout_base_ms); 44 45#endif