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1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright 2019 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27#ifndef AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
28#define AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
29
30struct drm_crtc;
31struct dm_crtc_state;
32
33enum amdgpu_dm_pipe_crc_source {
34 AMDGPU_DM_PIPE_CRC_SOURCE_NONE = 0,
35 AMDGPU_DM_PIPE_CRC_SOURCE_CRTC,
36 AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER,
37 AMDGPU_DM_PIPE_CRC_SOURCE_DPRX,
38 AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER,
39 AMDGPU_DM_PIPE_CRC_SOURCE_MAX,
40 AMDGPU_DM_PIPE_CRC_SOURCE_INVALID = -1,
41};
42
43#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
44#define MAX_CRTC 6
45
46enum secure_display_mode {
47 /* via dmub + psp */
48 LEGACY_MODE = 0,
49 /* driver directly */
50 DISPLAY_CRC_MODE,
51 SECURE_DISPLAY_MODE_MAX,
52};
53
54struct phy_id_mapping {
55 bool assigned;
56 bool is_mst;
57 uint8_t enc_hw_inst;
58 u8 lct;
59 u8 port_num;
60 u8 rad[8];
61};
62
63struct crc_data {
64 uint32_t crc_R;
65 uint32_t crc_G;
66 uint32_t crc_B;
67 uint32_t frame_count;
68 bool crc_ready;
69};
70
71struct crc_info {
72 struct crc_data crc[MAX_CRC_WINDOW_NUM];
73 struct completion completion;
74 spinlock_t lock;
75};
76
77struct crc_window_param {
78 uint16_t x_start;
79 uint16_t y_start;
80 uint16_t x_end;
81 uint16_t y_end;
82 /* CRC window is activated or not*/
83 bool enable;
84 /* Update crc window during vertical blank or not */
85 bool update_win;
86 /* skip reading/writing for few frames */
87 int skip_frame_cnt;
88};
89
90struct secure_display_crtc_context {
91 /* work to notify PSP TA*/
92 struct work_struct notify_ta_work;
93
94 /* work to forward ROI to dmcu/dmub */
95 struct work_struct forward_roi_work;
96
97 struct drm_crtc *crtc;
98
99 /* Region of Interest (ROI) */
100 struct crc_window roi[MAX_CRC_WINDOW_NUM];
101
102 struct crc_info crc_info;
103};
104
105struct secure_display_context {
106
107 struct secure_display_crtc_context *crtc_ctx;
108 /* Whether dmub support multiple ROI setting */
109 bool support_mul_roi;
110 enum secure_display_mode op_mode;
111 bool phy_mapping_updated;
112 int phy_id_mapping_cnt;
113 struct phy_id_mapping phy_id_mapping[MAX_CRTC];
114};
115#endif
116
117static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source source)
118{
119 return (source > AMDGPU_DM_PIPE_CRC_SOURCE_NONE) &&
120 (source < AMDGPU_DM_PIPE_CRC_SOURCE_MAX);
121}
122
123/* amdgpu_dm_crc.c */
124#ifdef CONFIG_DEBUG_FS
125int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
126 struct dm_crtc_state *dm_crtc_state,
127 enum amdgpu_dm_pipe_crc_source source);
128int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);
129int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
130 const char *src_name,
131 size_t *values_cnt);
132const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
133 size_t *count);
134void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
135#else
136#define amdgpu_dm_crtc_set_crc_source NULL
137#define amdgpu_dm_crtc_verify_crc_source NULL
138#define amdgpu_dm_crtc_get_crc_sources NULL
139#define amdgpu_dm_crtc_handle_crc_irq(x)
140#endif
141
142#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
143bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc);
144void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc);
145void amdgpu_dm_crtc_secure_display_create_contexts(struct amdgpu_device *adev);
146#else
147#define amdgpu_dm_crc_window_is_activated(x)
148#define amdgpu_dm_crtc_handle_crc_window_irq(x)
149#define amdgpu_dm_crtc_secure_display_create_contexts(x)
150#endif
151
152#endif /* AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ */