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1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright 2023 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25#ifndef AMDGPU_USERQ_H_
26#define AMDGPU_USERQ_H_
27#include "amdgpu_eviction_fence.h"
28
29#define AMDGPU_MAX_USERQ_COUNT 512
30
31#define to_ev_fence(f) container_of(f, struct amdgpu_eviction_fence, base)
32#define uq_mgr_to_fpriv(u) container_of(u, struct amdgpu_fpriv, userq_mgr)
33#define work_to_uq_mgr(w, name) container_of(w, struct amdgpu_userq_mgr, name)
34
35enum amdgpu_userq_state {
36 AMDGPU_USERQ_STATE_UNMAPPED = 0,
37 AMDGPU_USERQ_STATE_MAPPED,
38 AMDGPU_USERQ_STATE_PREEMPTED,
39 AMDGPU_USERQ_STATE_HUNG,
40 AMDGPU_USERQ_STATE_INVALID_VA,
41};
42
43struct amdgpu_mqd_prop;
44
45struct amdgpu_userq_obj {
46 void *cpu_ptr;
47 uint64_t gpu_addr;
48 struct amdgpu_bo *obj;
49};
50
51struct amdgpu_userq_va_cursor {
52 u64 gpu_addr;
53 struct list_head list;
54};
55
56struct amdgpu_usermode_queue {
57 int queue_type;
58 enum amdgpu_userq_state state;
59 uint64_t doorbell_handle;
60 uint64_t doorbell_index;
61 uint64_t flags;
62 struct amdgpu_mqd_prop *userq_prop;
63 struct amdgpu_userq_mgr *userq_mgr;
64 struct amdgpu_vm *vm;
65 struct amdgpu_userq_obj mqd;
66 struct amdgpu_userq_obj db_obj;
67 struct amdgpu_userq_obj fw_obj;
68 struct amdgpu_userq_obj wptr_obj;
69 struct xarray fence_drv_xa;
70 struct amdgpu_userq_fence_driver *fence_drv;
71 struct dma_fence *last_fence;
72 u32 xcp_id;
73 int priority;
74 struct dentry *debugfs_queue;
75
76 struct list_head userq_va_list;
77};
78
79struct amdgpu_userq_funcs {
80 int (*mqd_create)(struct amdgpu_userq_mgr *uq_mgr,
81 struct drm_amdgpu_userq_in *args,
82 struct amdgpu_usermode_queue *queue);
83 void (*mqd_destroy)(struct amdgpu_userq_mgr *uq_mgr,
84 struct amdgpu_usermode_queue *uq);
85 int (*unmap)(struct amdgpu_userq_mgr *uq_mgr,
86 struct amdgpu_usermode_queue *queue);
87 int (*map)(struct amdgpu_userq_mgr *uq_mgr,
88 struct amdgpu_usermode_queue *queue);
89 int (*preempt)(struct amdgpu_userq_mgr *uq_mgr,
90 struct amdgpu_usermode_queue *queue);
91 int (*restore)(struct amdgpu_userq_mgr *uq_mgr,
92 struct amdgpu_usermode_queue *queue);
93 int (*detect_and_reset)(struct amdgpu_device *adev,
94 int queue_type);
95};
96
97/* Usermode queues for gfx */
98struct amdgpu_userq_mgr {
99 /**
100 * @userq_mgr_xa: Per-process user queue map (queue ID → queue)
101 * Key: queue_id (unique ID within the process's userq manager)
102 * Value: struct amdgpu_usermode_queue
103 */
104 struct xarray userq_mgr_xa;
105 struct mutex userq_mutex;
106 struct amdgpu_device *adev;
107 struct delayed_work resume_work;
108 struct drm_file *file;
109 atomic_t userq_count[AMDGPU_RING_TYPE_MAX];
110};
111
112struct amdgpu_db_info {
113 uint64_t doorbell_handle;
114 uint32_t queue_type;
115 uint32_t doorbell_offset;
116 struct amdgpu_userq_obj *db_obj;
117};
118
119int amdgpu_userq_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
120
121int amdgpu_userq_mgr_init(struct amdgpu_userq_mgr *userq_mgr, struct drm_file *file_priv,
122 struct amdgpu_device *adev);
123
124void amdgpu_userq_mgr_fini(struct amdgpu_userq_mgr *userq_mgr);
125
126int amdgpu_userq_create_object(struct amdgpu_userq_mgr *uq_mgr,
127 struct amdgpu_userq_obj *userq_obj,
128 int size);
129
130void amdgpu_userq_destroy_object(struct amdgpu_userq_mgr *uq_mgr,
131 struct amdgpu_userq_obj *userq_obj);
132
133void amdgpu_userq_evict(struct amdgpu_userq_mgr *uq_mgr,
134 struct amdgpu_eviction_fence *ev_fence);
135
136void amdgpu_userq_ensure_ev_fence(struct amdgpu_userq_mgr *userq_mgr,
137 struct amdgpu_eviction_fence_mgr *evf_mgr);
138
139uint64_t amdgpu_userq_get_doorbell_index(struct amdgpu_userq_mgr *uq_mgr,
140 struct amdgpu_db_info *db_info,
141 struct drm_file *filp);
142
143u32 amdgpu_userq_get_supported_ip_mask(struct amdgpu_device *adev);
144bool amdgpu_userq_enabled(struct drm_device *dev);
145
146int amdgpu_userq_suspend(struct amdgpu_device *adev);
147int amdgpu_userq_resume(struct amdgpu_device *adev);
148
149int amdgpu_userq_stop_sched_for_enforce_isolation(struct amdgpu_device *adev,
150 u32 idx);
151int amdgpu_userq_start_sched_for_enforce_isolation(struct amdgpu_device *adev,
152 u32 idx);
153void amdgpu_userq_reset_work(struct work_struct *work);
154void amdgpu_userq_pre_reset(struct amdgpu_device *adev);
155int amdgpu_userq_post_reset(struct amdgpu_device *adev, bool vram_lost);
156
157int amdgpu_userq_input_va_validate(struct amdgpu_usermode_queue *queue,
158 u64 addr, u64 expected_size);
159int amdgpu_userq_gem_va_unmap_validate(struct amdgpu_device *adev,
160 struct amdgpu_bo_va_mapping *mapping,
161 uint64_t saddr);
162#endif