Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __AMDGPU_JPEG_H__
25#define __AMDGPU_JPEG_H__
26
27#include "amdgpu_ras.h"
28#include "amdgpu_cs.h"
29
30#define AMDGPU_MAX_JPEG_INSTANCES 4
31#define AMDGPU_MAX_JPEG_RINGS 10
32#define AMDGPU_MAX_JPEG_RINGS_4_0_3 8
33
34#define JPEG_REG_RANGE_START 0x4000
35#define JPEG_REG_RANGE_END 0x41c2
36#define JPEG_ATOMIC_RANGE_START 0x4120
37#define JPEG_ATOMIC_RANGE_END 0x412A
38
39
40#define AMDGPU_JPEG_HARVEST_JPEG0 (1 << 0)
41#define AMDGPU_JPEG_HARVEST_JPEG1 (1 << 1)
42
43#define WREG32_SOC15_JPEG_DPG_MODE(inst_idx, offset, value, indirect) \
44 do { \
45 if (!indirect) { \
46 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
47 mmUVD_DPG_LMA_DATA, value); \
48 WREG32_SOC15( \
49 JPEG, GET_INST(JPEG, inst_idx), \
50 mmUVD_DPG_LMA_CTL, \
51 (UVD_DPG_LMA_CTL__READ_WRITE_MASK | \
52 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT | \
53 indirect << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
54 } else { \
55 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = \
56 offset; \
57 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = \
58 value; \
59 } \
60 } while (0)
61
62#define RREG32_SOC15_JPEG_DPG_MODE(inst_idx, offset, mask_en) \
63 ({ \
64 WREG32_SOC15(JPEG, inst_idx, mmUVD_DPG_LMA_CTL, \
65 (0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \
66 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \
67 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
68 RREG32_SOC15(JPEG, inst_idx, mmUVD_DPG_LMA_DATA); \
69 })
70
71#define WREG32_SOC24_JPEG_DPG_MODE(inst_idx, offset, value, indirect) \
72 do { \
73 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
74 regUVD_DPG_LMA_DATA, value); \
75 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
76 regUVD_DPG_LMA_MASK, 0xFFFFFFFF); \
77 WREG32_SOC15( \
78 JPEG, GET_INST(JPEG, inst_idx), \
79 regUVD_DPG_LMA_CTL, \
80 (UVD_DPG_LMA_CTL__READ_WRITE_MASK | \
81 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT | \
82 indirect << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
83 } while (0)
84
85#define RREG32_SOC24_JPEG_DPG_MODE(inst_idx, offset, mask_en) \
86 do { \
87 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
88 regUVD_DPG_LMA_MASK, 0xFFFFFFFF); \
89 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
90 regUVD_DPG_LMA_CTL, \
91 (UVD_DPG_LMA_CTL__MASK_EN_MASK | \
92 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
93 RREG32_SOC15(JPEG, inst_idx, regUVD_DPG_LMA_DATA); \
94 } while (0)
95
96#define ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, offset, value, indirect) \
97 do { \
98 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = offset; \
99 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = value; \
100 } while (0)
101
102struct amdgpu_hwip_reg_entry;
103
104enum amdgpu_jpeg_caps {
105 AMDGPU_JPEG_RRMT_ENABLED,
106};
107
108#define AMDGPU_JPEG_CAPS(caps) BIT(AMDGPU_JPEG_##caps)
109
110struct amdgpu_jpeg_reg{
111 unsigned jpeg_pitch[AMDGPU_MAX_JPEG_RINGS];
112};
113
114struct amdgpu_jpeg_inst {
115 struct amdgpu_ring ring_dec[AMDGPU_MAX_JPEG_RINGS];
116 struct amdgpu_irq_src irq;
117 struct amdgpu_irq_src ras_poison_irq;
118 struct amdgpu_jpeg_reg external;
119 struct amdgpu_bo *dpg_sram_bo;
120 struct dpg_pause_state pause_state;
121 void *dpg_sram_cpu_addr;
122 uint64_t dpg_sram_gpu_addr;
123 uint32_t *dpg_sram_curr_addr;
124 uint8_t aid_id;
125};
126
127struct amdgpu_jpeg_ras {
128 struct amdgpu_ras_block_object ras_block;
129};
130
131struct amdgpu_jpeg {
132 uint8_t num_jpeg_inst;
133 struct amdgpu_jpeg_inst inst[AMDGPU_MAX_JPEG_INSTANCES];
134 unsigned num_jpeg_rings;
135 struct amdgpu_jpeg_reg internal;
136 unsigned harvest_config;
137 struct delayed_work idle_work;
138 enum amd_powergating_state cur_state;
139 struct mutex jpeg_pg_lock;
140 atomic_t total_submission_cnt;
141 struct ras_common_if *ras_if;
142 struct amdgpu_jpeg_ras *ras;
143
144 uint16_t inst_mask;
145 uint8_t num_inst_per_aid;
146 bool indirect_sram;
147 uint32_t supported_reset;
148 uint32_t caps;
149 u32 *ip_dump;
150 u32 reg_count;
151 const struct amdgpu_hwip_reg_entry *reg_list;
152};
153
154int amdgpu_jpeg_sw_init(struct amdgpu_device *adev);
155int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev);
156int amdgpu_jpeg_suspend(struct amdgpu_device *adev);
157int amdgpu_jpeg_resume(struct amdgpu_device *adev);
158
159void amdgpu_jpeg_ring_begin_use(struct amdgpu_ring *ring);
160void amdgpu_jpeg_ring_end_use(struct amdgpu_ring *ring);
161
162int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring);
163int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
164
165int amdgpu_jpeg_process_poison_irq(struct amdgpu_device *adev,
166 struct amdgpu_irq_src *source,
167 struct amdgpu_iv_entry *entry);
168int amdgpu_jpeg_ras_late_init(struct amdgpu_device *adev,
169 struct ras_common_if *ras_block);
170int amdgpu_jpeg_ras_sw_init(struct amdgpu_device *adev);
171int amdgpu_jpeg_psp_update_sram(struct amdgpu_device *adev, int inst_idx,
172 enum AMDGPU_UCODE_ID ucode_id);
173void amdgpu_debugfs_jpeg_sched_mask_init(struct amdgpu_device *adev);
174int amdgpu_jpeg_sysfs_reset_mask_init(struct amdgpu_device *adev);
175void amdgpu_jpeg_sysfs_reset_mask_fini(struct amdgpu_device *adev);
176int amdgpu_jpeg_reg_dump_init(struct amdgpu_device *adev,
177 const struct amdgpu_hwip_reg_entry *reg, u32 count);
178void amdgpu_jpeg_dump_ip_state(struct amdgpu_ip_block *ip_block);
179void amdgpu_jpeg_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p);
180int amdgpu_jpeg_dec_parse_cs(struct amdgpu_cs_parser *parser,
181 struct amdgpu_job *job,
182 struct amdgpu_ib *ib);
183
184#endif /*__AMDGPU_JPEG_H__*/