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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * GPIO interface for IT87xx Super I/O chips
4 *
5 * Author: Diego Elio Pettenò <flameeyes@flameeyes.eu>
6 * Copyright (c) 2017 Google, Inc.
7 *
8 * Based on it87_wdt.c by Oliver Schuster
9 * gpio-it8761e.c by Denis Turischev
10 * gpio-stmpe.c by Rabin Vincent
11 */
12
13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15#include <linux/cleanup.h>
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/io.h>
20#include <linux/errno.h>
21#include <linux/ioport.h>
22#include <linux/slab.h>
23#include <linux/gpio/driver.h>
24
25/* Chip Id numbers */
26#define NO_DEV_ID 0xffff
27#define IT8613_ID 0x8613
28#define IT8620_ID 0x8620
29#define IT8628_ID 0x8628
30#define IT8718_ID 0x8718
31#define IT8728_ID 0x8728
32#define IT8732_ID 0x8732
33#define IT8761_ID 0x8761
34#define IT8772_ID 0x8772
35#define IT8786_ID 0x8786
36
37/* IO Ports */
38#define REG 0x2e
39#define VAL 0x2f
40
41/* Logical device Numbers LDN */
42#define GPIO 0x07
43
44/* Configuration Registers and Functions */
45#define LDNREG 0x07
46#define CHIPID 0x20
47#define CHIPREV 0x22
48
49/**
50 * struct it87_gpio - it87-specific GPIO chip
51 * @chip: the underlying gpio_chip structure
52 * @lock: a lock to avoid races between operations
53 * @io_base: base address for gpio ports
54 * @io_size: size of the port rage starting from io_base.
55 * @output_base: Super I/O register address for Output Enable register
56 * @simple_base: Super I/O 'Simple I/O' Enable register
57 * @simple_size: Super IO 'Simple I/O' Enable register size; this is
58 * required because IT87xx chips might only provide Simple I/O
59 * switches on a subset of lines, whereas the others keep the
60 * same status all time.
61 */
62struct it87_gpio {
63 struct gpio_chip chip;
64 spinlock_t lock;
65 u16 io_base;
66 u16 io_size;
67 u8 output_base;
68 u8 simple_base;
69 u8 simple_size;
70};
71
72static struct it87_gpio it87_gpio_chip = {
73 .lock = __SPIN_LOCK_UNLOCKED(it87_gpio_chip.lock),
74};
75
76/* Superio chip access functions; copied from wdt_it87 */
77
78static inline int superio_enter(void)
79{
80 /*
81 * Try to reserve REG and REG + 1 for exclusive access.
82 */
83 if (!request_muxed_region(REG, 2, KBUILD_MODNAME))
84 return -EBUSY;
85
86 outb(0x87, REG);
87 outb(0x01, REG);
88 outb(0x55, REG);
89 outb(0x55, REG);
90 return 0;
91}
92
93static inline void superio_exit(void)
94{
95 outb(0x02, REG);
96 outb(0x02, VAL);
97 release_region(REG, 2);
98}
99
100static inline void superio_select(int ldn)
101{
102 outb(LDNREG, REG);
103 outb(ldn, VAL);
104}
105
106static inline int superio_inb(int reg)
107{
108 outb(reg, REG);
109 return inb(VAL);
110}
111
112static inline void superio_outb(int val, int reg)
113{
114 outb(reg, REG);
115 outb(val, VAL);
116}
117
118static inline int superio_inw(int reg)
119{
120 int val;
121
122 outb(reg++, REG);
123 val = inb(VAL) << 8;
124 outb(reg, REG);
125 val |= inb(VAL);
126 return val;
127}
128
129static inline void superio_set_mask(int mask, int reg)
130{
131 u8 curr_val = superio_inb(reg);
132 u8 new_val = curr_val | mask;
133
134 if (curr_val != new_val)
135 superio_outb(new_val, reg);
136}
137
138static inline void superio_clear_mask(int mask, int reg)
139{
140 u8 curr_val = superio_inb(reg);
141 u8 new_val = curr_val & ~mask;
142
143 if (curr_val != new_val)
144 superio_outb(new_val, reg);
145}
146
147static int it87_gpio_request(struct gpio_chip *chip, unsigned gpio_num)
148{
149 u8 mask, group;
150 int rc = 0;
151 struct it87_gpio *it87_gpio = gpiochip_get_data(chip);
152
153 mask = 1 << (gpio_num % 8);
154 group = (gpio_num / 8);
155
156 spin_lock(&it87_gpio->lock);
157
158 rc = superio_enter();
159 if (rc)
160 goto exit;
161
162 /* not all the IT87xx chips support Simple I/O and not all of
163 * them allow all the lines to be set/unset to Simple I/O.
164 */
165 if (group < it87_gpio->simple_size)
166 superio_set_mask(mask, group + it87_gpio->simple_base);
167
168 /* clear output enable, setting the pin to input, as all the
169 * newly-exported GPIO interfaces are set to input.
170 */
171 superio_clear_mask(mask, group + it87_gpio->output_base);
172
173 superio_exit();
174
175exit:
176 spin_unlock(&it87_gpio->lock);
177 return rc;
178}
179
180static int it87_gpio_get(struct gpio_chip *chip, unsigned gpio_num)
181{
182 u16 reg;
183 u8 mask;
184 struct it87_gpio *it87_gpio = gpiochip_get_data(chip);
185
186 mask = 1 << (gpio_num % 8);
187 reg = (gpio_num / 8) + it87_gpio->io_base;
188
189 return !!(inb(reg) & mask);
190}
191
192static int it87_gpio_direction_in(struct gpio_chip *chip, unsigned gpio_num)
193{
194 u8 mask, group;
195 int rc = 0;
196 struct it87_gpio *it87_gpio = gpiochip_get_data(chip);
197
198 mask = 1 << (gpio_num % 8);
199 group = (gpio_num / 8);
200
201 spin_lock(&it87_gpio->lock);
202
203 rc = superio_enter();
204 if (rc)
205 goto exit;
206
207 /* clear the output enable bit */
208 superio_clear_mask(mask, group + it87_gpio->output_base);
209
210 superio_exit();
211
212exit:
213 spin_unlock(&it87_gpio->lock);
214 return rc;
215}
216
217static int it87_gpio_set(struct gpio_chip *chip, unsigned int gpio_num, int val)
218{
219 u8 mask, curr_vals;
220 u16 reg;
221 struct it87_gpio *it87_gpio = gpiochip_get_data(chip);
222
223 mask = 1 << (gpio_num % 8);
224 reg = (gpio_num / 8) + it87_gpio->io_base;
225
226 curr_vals = inb(reg);
227 if (val)
228 outb(curr_vals | mask, reg);
229 else
230 outb(curr_vals & ~mask, reg);
231
232 return 0;
233}
234
235static int it87_gpio_direction_out(struct gpio_chip *chip,
236 unsigned gpio_num, int val)
237{
238 u8 mask, group;
239 int rc = 0;
240 struct it87_gpio *it87_gpio = gpiochip_get_data(chip);
241
242 mask = 1 << (gpio_num % 8);
243 group = (gpio_num / 8);
244
245 guard(spinlock)(&it87_gpio->lock);
246
247 rc = superio_enter();
248 if (rc)
249 return rc;
250
251 /* set the output enable bit */
252 superio_set_mask(mask, group + it87_gpio->output_base);
253
254 rc = it87_gpio_set(chip, gpio_num, val);
255 superio_exit();
256 return rc;
257}
258
259static const struct gpio_chip it87_template_chip = {
260 .label = KBUILD_MODNAME,
261 .owner = THIS_MODULE,
262 .request = it87_gpio_request,
263 .get = it87_gpio_get,
264 .direction_input = it87_gpio_direction_in,
265 .set = it87_gpio_set,
266 .direction_output = it87_gpio_direction_out,
267 .base = -1
268};
269
270static int __init it87_gpio_init(void)
271{
272 int rc = 0, i;
273 u16 chip_type;
274 u8 chip_rev, gpio_ba_reg;
275 char *labels, **labels_table;
276
277 struct it87_gpio *it87_gpio = &it87_gpio_chip;
278
279 rc = superio_enter();
280 if (rc)
281 return rc;
282
283 chip_type = superio_inw(CHIPID);
284 chip_rev = superio_inb(CHIPREV) & 0x0f;
285 superio_exit();
286
287 it87_gpio->chip = it87_template_chip;
288
289 switch (chip_type) {
290 case IT8613_ID:
291 gpio_ba_reg = 0x62;
292 it87_gpio->io_size = 8; /* it8613 only needs 6, use 8 for alignment */
293 it87_gpio->output_base = 0xc8;
294 it87_gpio->simple_base = 0xc0;
295 it87_gpio->simple_size = 6;
296 it87_gpio->chip.ngpio = 64; /* has 48, use 64 for convenient calc */
297 break;
298 case IT8620_ID:
299 case IT8628_ID:
300 gpio_ba_reg = 0x62;
301 it87_gpio->io_size = 11;
302 it87_gpio->output_base = 0xc8;
303 it87_gpio->simple_size = 0;
304 it87_gpio->chip.ngpio = 64;
305 break;
306 case IT8718_ID:
307 case IT8728_ID:
308 case IT8732_ID:
309 case IT8772_ID:
310 case IT8786_ID:
311 gpio_ba_reg = 0x62;
312 it87_gpio->io_size = 8;
313 it87_gpio->output_base = 0xc8;
314 it87_gpio->simple_base = 0xc0;
315 it87_gpio->simple_size = 5;
316 it87_gpio->chip.ngpio = 64;
317 break;
318 case IT8761_ID:
319 gpio_ba_reg = 0x60;
320 it87_gpio->io_size = 4;
321 it87_gpio->output_base = 0xf0;
322 it87_gpio->simple_size = 0;
323 it87_gpio->chip.ngpio = 16;
324 break;
325 case NO_DEV_ID:
326 pr_err("no device\n");
327 return -ENODEV;
328 default:
329 pr_err("Unknown Chip found, Chip %04x Revision %x\n",
330 chip_type, chip_rev);
331 return -ENODEV;
332 }
333
334 rc = superio_enter();
335 if (rc)
336 return rc;
337
338 superio_select(GPIO);
339
340 /* fetch GPIO base address */
341 it87_gpio->io_base = superio_inw(gpio_ba_reg);
342
343 superio_exit();
344
345 pr_info("Found Chip IT%04x rev %x. %u GPIO lines starting at %04xh\n",
346 chip_type, chip_rev, it87_gpio->chip.ngpio,
347 it87_gpio->io_base);
348
349 if (!request_region(it87_gpio->io_base, it87_gpio->io_size,
350 KBUILD_MODNAME))
351 return -EBUSY;
352
353 /* Set up aliases for the GPIO connection.
354 *
355 * ITE documentation for recent chips such as the IT8728F
356 * refers to the GPIO lines as GPxy, with a coordinates system
357 * where x is the GPIO group (starting from 1) and y is the
358 * bit within the group.
359 *
360 * By creating these aliases, we make it easier to understand
361 * to which GPIO pin we're referring to.
362 */
363 labels = kcalloc(it87_gpio->chip.ngpio, sizeof("it87_gpXY"),
364 GFP_KERNEL);
365 labels_table = kcalloc(it87_gpio->chip.ngpio, sizeof(const char *),
366 GFP_KERNEL);
367
368 if (!labels || !labels_table) {
369 rc = -ENOMEM;
370 goto labels_free;
371 }
372
373 for (i = 0; i < it87_gpio->chip.ngpio; i++) {
374 char *label = &labels[i * sizeof("it87_gpXY")];
375
376 sprintf(label, "it87_gp%u%u", 1+(i/8), i%8);
377 labels_table[i] = label;
378 }
379
380 it87_gpio->chip.names = (const char *const*)labels_table;
381
382 rc = gpiochip_add_data(&it87_gpio->chip, it87_gpio);
383 if (rc)
384 goto labels_free;
385
386 return 0;
387
388labels_free:
389 kfree(labels_table);
390 kfree(labels);
391 release_region(it87_gpio->io_base, it87_gpio->io_size);
392 return rc;
393}
394
395static void __exit it87_gpio_exit(void)
396{
397 struct it87_gpio *it87_gpio = &it87_gpio_chip;
398
399 gpiochip_remove(&it87_gpio->chip);
400 release_region(it87_gpio->io_base, it87_gpio->io_size);
401 kfree(it87_gpio->chip.names[0]);
402 kfree(it87_gpio->chip.names);
403}
404
405module_init(it87_gpio_init);
406module_exit(it87_gpio_exit);
407
408MODULE_AUTHOR("Diego Elio Pettenò <flameeyes@flameeyes.eu>");
409MODULE_DESCRIPTION("GPIO interface for IT87xx Super I/O chips");
410MODULE_LICENSE("GPL");