Linux kernel mirror (for testing)
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tjh.dev
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linux
1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (C) 2008-2009 The GameCube Linux Team
3// Copyright (C) 2008,2009 Albert Herranz
4// Copyright (C) 2017-2018 Jonathan Neuschäfer
5//
6// Nintendo Wii (Hollywood) GPIO driver
7
8#include <linux/gpio/driver.h>
9#include <linux/gpio/generic.h>
10#include <linux/io.h>
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15#include <linux/seq_file.h>
16#include <linux/slab.h>
17
18/*
19 * Register names and offsets courtesy of WiiBrew:
20 * https://wiibrew.org/wiki/Hardware/Hollywood_GPIOs
21 *
22 * Note that for most registers, there are two versions:
23 * - HW_GPIOB_* Is always accessible by the Broadway PowerPC core, but does
24 * always give access to all GPIO lines
25 * - HW_GPIO_* Is only accessible by the Broadway PowerPC code if the memory
26 * firewall (AHBPROT) in the Hollywood chipset has been configured to allow
27 * such access.
28 *
29 * The ownership of each GPIO line can be configured in the HW_GPIO_OWNER
30 * register: A one bit configures the line for access via the HW_GPIOB_*
31 * registers, a zero bit indicates access via HW_GPIO_*. This driver uses
32 * HW_GPIOB_*.
33 */
34#define HW_GPIOB_OUT 0x00
35#define HW_GPIOB_DIR 0x04
36#define HW_GPIOB_IN 0x08
37#define HW_GPIOB_INTLVL 0x0c
38#define HW_GPIOB_INTFLAG 0x10
39#define HW_GPIOB_INTMASK 0x14
40#define HW_GPIOB_INMIR 0x18
41#define HW_GPIO_ENABLE 0x1c
42#define HW_GPIO_OUT 0x20
43#define HW_GPIO_DIR 0x24
44#define HW_GPIO_IN 0x28
45#define HW_GPIO_INTLVL 0x2c
46#define HW_GPIO_INTFLAG 0x30
47#define HW_GPIO_INTMASK 0x34
48#define HW_GPIO_INMIR 0x38
49#define HW_GPIO_OWNER 0x3c
50
51struct hlwd_gpio {
52 struct gpio_generic_chip gpioc;
53 struct device *dev;
54 void __iomem *regs;
55 int irq;
56 u32 edge_emulation;
57 u32 rising_edge, falling_edge;
58};
59
60static void hlwd_gpio_irqhandler(struct irq_desc *desc)
61{
62 struct hlwd_gpio *hlwd =
63 gpiochip_get_data(irq_desc_get_handler_data(desc));
64 struct irq_chip *chip = irq_desc_get_chip(desc);
65 unsigned long pending;
66 int hwirq;
67 u32 emulated_pending;
68
69 scoped_guard(gpio_generic_lock_irqsave, &hlwd->gpioc) {
70 pending = ioread32be(hlwd->regs + HW_GPIOB_INTFLAG);
71 pending &= ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
72
73 /* Treat interrupts due to edge trigger emulation separately */
74 emulated_pending = hlwd->edge_emulation & pending;
75 pending &= ~emulated_pending;
76 if (emulated_pending) {
77 u32 level, rising, falling;
78
79 level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
80 rising = level & emulated_pending;
81 falling = ~level & emulated_pending;
82
83 /* Invert the levels */
84 iowrite32be(level ^ emulated_pending,
85 hlwd->regs + HW_GPIOB_INTLVL);
86
87 /* Ack all emulated-edge interrupts */
88 iowrite32be(emulated_pending, hlwd->regs + HW_GPIOB_INTFLAG);
89
90 /* Signal interrupts only on the correct edge */
91 rising &= hlwd->rising_edge;
92 falling &= hlwd->falling_edge;
93
94 /* Mark emulated interrupts as pending */
95 pending |= rising | falling;
96 }
97 }
98
99 chained_irq_enter(chip, desc);
100
101 for_each_set_bit(hwirq, &pending, 32)
102 generic_handle_domain_irq(hlwd->gpioc.gc.irq.domain, hwirq);
103
104 chained_irq_exit(chip, desc);
105}
106
107static void hlwd_gpio_irq_ack(struct irq_data *data)
108{
109 struct hlwd_gpio *hlwd =
110 gpiochip_get_data(irq_data_get_irq_chip_data(data));
111
112 iowrite32be(BIT(data->hwirq), hlwd->regs + HW_GPIOB_INTFLAG);
113}
114
115static void hlwd_gpio_irq_mask(struct irq_data *data)
116{
117 struct hlwd_gpio *hlwd =
118 gpiochip_get_data(irq_data_get_irq_chip_data(data));
119 u32 mask;
120
121 scoped_guard(gpio_generic_lock_irqsave, &hlwd->gpioc) {
122 mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
123 mask &= ~BIT(data->hwirq);
124 iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
125 }
126 gpiochip_disable_irq(&hlwd->gpioc.gc, irqd_to_hwirq(data));
127}
128
129static void hlwd_gpio_irq_unmask(struct irq_data *data)
130{
131 struct hlwd_gpio *hlwd =
132 gpiochip_get_data(irq_data_get_irq_chip_data(data));
133 u32 mask;
134
135 gpiochip_enable_irq(&hlwd->gpioc.gc, irqd_to_hwirq(data));
136
137 guard(gpio_generic_lock_irqsave)(&hlwd->gpioc);
138
139 mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
140 mask |= BIT(data->hwirq);
141 iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
142}
143
144static void hlwd_gpio_irq_enable(struct irq_data *data)
145{
146 hlwd_gpio_irq_ack(data);
147 hlwd_gpio_irq_unmask(data);
148}
149
150static void hlwd_gpio_irq_setup_emulation(struct hlwd_gpio *hlwd, int hwirq,
151 unsigned int flow_type)
152{
153 u32 level, state;
154
155 /* Set the trigger level to the inactive level */
156 level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
157 state = ioread32be(hlwd->regs + HW_GPIOB_IN) & BIT(hwirq);
158 level &= ~BIT(hwirq);
159 level |= state ^ BIT(hwirq);
160 iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
161
162 hlwd->edge_emulation |= BIT(hwirq);
163 hlwd->rising_edge &= ~BIT(hwirq);
164 hlwd->falling_edge &= ~BIT(hwirq);
165 if (flow_type & IRQ_TYPE_EDGE_RISING)
166 hlwd->rising_edge |= BIT(hwirq);
167 if (flow_type & IRQ_TYPE_EDGE_FALLING)
168 hlwd->falling_edge |= BIT(hwirq);
169}
170
171static int hlwd_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
172{
173 struct hlwd_gpio *hlwd =
174 gpiochip_get_data(irq_data_get_irq_chip_data(data));
175 u32 level;
176
177 guard(gpio_generic_lock_irqsave)(&hlwd->gpioc);
178
179 hlwd->edge_emulation &= ~BIT(data->hwirq);
180
181 switch (flow_type) {
182 case IRQ_TYPE_LEVEL_HIGH:
183 level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
184 level |= BIT(data->hwirq);
185 iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
186 break;
187 case IRQ_TYPE_LEVEL_LOW:
188 level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
189 level &= ~BIT(data->hwirq);
190 iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
191 break;
192 case IRQ_TYPE_EDGE_RISING:
193 case IRQ_TYPE_EDGE_FALLING:
194 case IRQ_TYPE_EDGE_BOTH:
195 hlwd_gpio_irq_setup_emulation(hlwd, data->hwirq, flow_type);
196 break;
197 default:
198 return -EINVAL;
199 }
200
201 return 0;
202}
203
204static void hlwd_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p)
205{
206 struct hlwd_gpio *hlwd =
207 gpiochip_get_data(irq_data_get_irq_chip_data(data));
208
209 seq_puts(p, dev_name(hlwd->dev));
210}
211
212static const struct irq_chip hlwd_gpio_irq_chip = {
213 .irq_mask = hlwd_gpio_irq_mask,
214 .irq_unmask = hlwd_gpio_irq_unmask,
215 .irq_enable = hlwd_gpio_irq_enable,
216 .irq_set_type = hlwd_gpio_irq_set_type,
217 .irq_print_chip = hlwd_gpio_irq_print_chip,
218 .flags = IRQCHIP_IMMUTABLE,
219 GPIOCHIP_IRQ_RESOURCE_HELPERS,
220};
221
222static int hlwd_gpio_probe(struct platform_device *pdev)
223{
224 struct gpio_generic_chip_config config;
225 struct hlwd_gpio *hlwd;
226 u32 ngpios;
227 int res;
228
229 hlwd = devm_kzalloc(&pdev->dev, sizeof(*hlwd), GFP_KERNEL);
230 if (!hlwd)
231 return -ENOMEM;
232
233 hlwd->regs = devm_platform_ioremap_resource(pdev, 0);
234 if (IS_ERR(hlwd->regs))
235 return PTR_ERR(hlwd->regs);
236
237 hlwd->dev = &pdev->dev;
238
239 /*
240 * Claim all GPIOs using the OWNER register. This will not work on
241 * systems where the AHBPROT memory firewall hasn't been configured to
242 * permit PPC access to HW_GPIO_*.
243 *
244 * Note that this has to happen before gpio_generic_chip_init() reads
245 * the HW_GPIOB_OUT and HW_GPIOB_DIR, because otherwise it reads the
246 * wrong values.
247 */
248 iowrite32be(0xffffffff, hlwd->regs + HW_GPIO_OWNER);
249
250 config = (struct gpio_generic_chip_config) {
251 .dev = &pdev->dev,
252 .sz = 4,
253 .dat = hlwd->regs + HW_GPIOB_IN,
254 .set = hlwd->regs + HW_GPIOB_OUT,
255 .dirout = hlwd->regs + HW_GPIOB_DIR,
256 .flags = GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER,
257 };
258
259 res = gpio_generic_chip_init(&hlwd->gpioc, &config);
260 if (res < 0) {
261 dev_warn(&pdev->dev, "failed to initialize generic GPIO chip: %d\n", res);
262 return res;
263 }
264
265 res = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios);
266 if (res)
267 ngpios = 32;
268 hlwd->gpioc.gc.ngpio = ngpios;
269
270 /* Mask and ack all interrupts */
271 iowrite32be(0, hlwd->regs + HW_GPIOB_INTMASK);
272 iowrite32be(0xffffffff, hlwd->regs + HW_GPIOB_INTFLAG);
273
274 /*
275 * If this GPIO controller is not marked as an interrupt controller in
276 * the DT, skip interrupt support.
277 */
278 if (of_property_read_bool(pdev->dev.of_node, "interrupt-controller")) {
279 struct gpio_irq_chip *girq;
280
281 hlwd->irq = platform_get_irq(pdev, 0);
282 if (hlwd->irq < 0) {
283 dev_info(&pdev->dev, "platform_get_irq returned %d\n",
284 hlwd->irq);
285 return hlwd->irq;
286 }
287
288 girq = &hlwd->gpioc.gc.irq;
289 gpio_irq_chip_set_chip(girq, &hlwd_gpio_irq_chip);
290 girq->parent_handler = hlwd_gpio_irqhandler;
291 girq->num_parents = 1;
292 girq->parents = devm_kcalloc(&pdev->dev, 1,
293 sizeof(*girq->parents),
294 GFP_KERNEL);
295 if (!girq->parents)
296 return -ENOMEM;
297 girq->parents[0] = hlwd->irq;
298 girq->default_type = IRQ_TYPE_NONE;
299 girq->handler = handle_level_irq;
300 }
301
302 return devm_gpiochip_add_data(&pdev->dev, &hlwd->gpioc.gc, hlwd);
303}
304
305static const struct of_device_id hlwd_gpio_match[] = {
306 { .compatible = "nintendo,hollywood-gpio", },
307 {},
308};
309MODULE_DEVICE_TABLE(of, hlwd_gpio_match);
310
311static struct platform_driver hlwd_gpio_driver = {
312 .driver = {
313 .name = "gpio-hlwd",
314 .of_match_table = hlwd_gpio_match,
315 },
316 .probe = hlwd_gpio_probe,
317};
318module_platform_driver(hlwd_gpio_driver);
319
320MODULE_AUTHOR("Jonathan Neuschäfer <j.neuschaefer@gmx.net>");
321MODULE_DESCRIPTION("Nintendo Wii GPIO driver");
322MODULE_LICENSE("GPL");