Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: GPL-2.0 */
2
3/***************************************************************************
4 * copyright : (C) 2002 by Frank Mori Hess
5 ***************************************************************************/
6
7#ifndef _NEC7210_REGISTERS_H
8#define _NEC7210_REGISTERS_H
9
10enum nec7210_chipset {
11 NEC7210, // The original
12 TNT4882, // NI
13 NAT4882, // NI
14 CB7210, // measurement computing
15 IOT7210, // iotech
16 IGPIB7210, // Ines
17 TNT5004, // NI (minor differences to TNT4882)
18};
19
20/*
21 * nec7210 register numbers (might need to be multiplied by
22 * a board-dependent offset to get actually io address offset)
23 */
24// write registers
25enum nec7210_write_regs {
26 CDOR, // command/data out
27 IMR1, // interrupt mask 1
28 IMR2, // interrupt mask 2
29 SPMR, // serial poll mode
30 ADMR, // address mode
31 AUXMR, // auxiliary mode
32 ADR, // address
33 EOSR, // end-of-string
34
35 // nec7210 has 8 registers
36 nec7210_num_registers = 8,
37};
38
39// read registers
40enum nec7210_read_regs {
41 DIR, // data in
42 ISR1, // interrupt status 1
43 ISR2, // interrupt status 2
44 SPSR, // serial poll status
45 ADSR, // address status
46 CPTR, // command pass though
47 ADR0, // address 1
48 ADR1, // address 2
49};
50
51// bit definitions common to nec-7210 compatible registers
52
53// ISR1: interrupt status register 1
54enum isr1_bits {
55 HR_DI = (1 << 0),
56 HR_DO = (1 << 1),
57 HR_ERR = (1 << 2),
58 HR_DEC = (1 << 3),
59 HR_END = (1 << 4),
60 HR_DET = (1 << 5),
61 HR_APT = (1 << 6),
62 HR_CPT = (1 << 7),
63};
64
65// IMR1: interrupt mask register 1
66enum imr1_bits {
67 HR_DIIE = (1 << 0),
68 HR_DOIE = (1 << 1),
69 HR_ERRIE = (1 << 2),
70 HR_DECIE = (1 << 3),
71 HR_ENDIE = (1 << 4),
72 HR_DETIE = (1 << 5),
73 HR_APTIE = (1 << 6),
74 HR_CPTIE = (1 << 7),
75};
76
77// ISR2, interrupt status register 2
78enum isr2_bits {
79 HR_ADSC = (1 << 0),
80 HR_REMC = (1 << 1),
81 HR_LOKC = (1 << 2),
82 HR_CO = (1 << 3),
83 HR_REM = (1 << 4),
84 HR_LOK = (1 << 5),
85 HR_SRQI = (1 << 6),
86 HR_INT = (1 << 7),
87};
88
89// IMR2, interrupt mask register 2
90enum imr2_bits {
91 // all the bits in this register that enable interrupts
92 IMR2_ENABLE_INTR_MASK = 0x4f,
93 HR_ACIE = (1 << 0),
94 HR_REMIE = (1 << 1),
95 HR_LOKIE = (1 << 2),
96 HR_COIE = (1 << 3),
97 HR_DMAI = (1 << 4),
98 HR_DMAO = (1 << 5),
99 HR_SRQIE = (1 << 6),
100};
101
102// SPSR, serial poll status register
103enum spsr_bits {
104 HR_PEND = (1 << 6),
105};
106
107// SPMR, serial poll mode register
108enum spmr_bits {
109 HR_RSV = (1 << 6),
110};
111
112// ADSR, address status register
113enum adsr_bits {
114 HR_MJMN = (1 << 0),
115 HR_TA = (1 << 1),
116 HR_LA = (1 << 2),
117 HR_TPAS = (1 << 3),
118 HR_LPAS = (1 << 4),
119 HR_SPMS = (1 << 5),
120 HR_NATN = (1 << 6),
121 HR_CIC = (1 << 7),
122};
123
124// ADMR, address mode register
125enum admr_bits {
126 HR_ADM0 = (1 << 0),
127 HR_ADM1 = (1 << 1),
128 HR_TRM0 = (1 << 4),
129 HR_TRM1 = (1 << 5),
130 HR_TRM_EOIOE_TRIG = 0,
131 HR_TRM_CIC_TRIG = HR_TRM0,
132 HR_TRM_CIC_EOIOE = HR_TRM1,
133 HR_TRM_CIC_PE = HR_TRM0 | HR_TRM1,
134 HR_LON = (1 << 6),
135 HR_TON = (1 << 7),
136};
137
138// ADR, bits used in address0, address1 and address0/1 registers
139enum adr_bits {
140 ADDRESS_MASK = 0x1f, /* mask to specify lower 5 bits */
141 HR_DL = (1 << 5),
142 HR_DT = (1 << 6),
143 HR_ARS = (1 << 7),
144};
145
146// ADR1, address1 register
147enum adr1_bits {
148 HR_EOI = (1 << 7),
149};
150
151// AUXMR, auxiliary mode register
152enum auxmr_bits {
153 ICR = 0x20,
154 PPR = 0x60,
155 AUXRA = 0x80,
156 AUXRB = 0xa0,
157 AUXRE = 0xc0,
158};
159
160// auxra, auxiliary register A
161enum auxra_bits {
162 HR_HANDSHAKE_MASK = 0x3,
163 HR_HLDA = 0x1,
164 HR_HLDE = 0x2,
165 HR_LCM = 0x3, /* auxra listen continuous */
166 HR_REOS = 0x4,
167 HR_XEOS = 0x8,
168 HR_BIN = 0x10,
169};
170
171// auxrb, auxiliary register B
172enum auxrb_bits {
173 HR_CPTE = (1 << 0),
174 HR_SPEOI = (1 << 1),
175 HR_TRI = (1 << 2),
176 HR_INV = (1 << 3),
177 HR_ISS = (1 << 4),
178};
179
180enum auxre_bits {
181 HR_DAC_HLD_DCAS = 0x1, /* perform DAC holdoff on receiving clear */
182 HR_DAC_HLD_DTAS = 0x2, /* perform DAC holdoff on receiving trigger */
183};
184
185// parallel poll register
186enum ppr_bits {
187 HR_PPS = (1 << 3),
188 HR_PPU = (1 << 4),
189};
190
191/* 7210 Auxiliary Commands */
192enum aux_cmds {
193 AUX_PON = 0x0, /* Immediate Execute pon */
194 AUX_CPPF = 0x1, /* Clear Parallel Poll Flag */
195 AUX_CR = 0x2, /* Chip Reset */
196 AUX_FH = 0x3, /* Finish Handshake */
197 AUX_TRIG = 0x4, /* Trigger */
198 AUX_RTL = 0x5, /* Return to local */
199 AUX_SEOI = 0x6, /* Send EOI */
200 AUX_NVAL = 0x7, /* Non-Valid Secondary Command or Address */
201 AUX_SPPF = 0x9, /* Set Parallel Poll Flag */
202 AUX_VAL = 0xf, /* Valid Secondary Command or Address */
203 AUX_GTS = 0x10, /* Go To Standby */
204 AUX_TCA = 0x11, /* Take Control Asynchronously */
205 AUX_TCS = 0x12, /* Take Control Synchronously */
206 AUX_LTN = 0x13, /* Listen */
207 AUX_DSC = 0x14, /* Disable System Control */
208 AUX_CIFC = 0x16, /* Clear IFC */
209 AUX_CREN = 0x17, /* Clear REN */
210 AUX_TCSE = 0x1a, /* Take Control Synchronously on End */
211 AUX_LTNC = 0x1b, /* Listen in Continuous Mode */
212 AUX_LUN = 0x1c, /* Local Unlisten */
213 AUX_EPP = 0x1d, /* Execute Parallel Poll */
214 AUX_SIFC = 0x1e, /* Set IFC */
215 AUX_SREN = 0x1f, /* Set REN */
216};
217
218#endif //_NEC7210_REGISTERS_H