Linux kernel mirror (for testing)
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linux
1#
2# EDAC Kconfig
3# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
4# Licensed and distributed under the GPL
5
6config EDAC_ATOMIC_SCRUB
7 bool
8
9config EDAC_SUPPORT
10 bool
11
12menuconfig EDAC
13 tristate "EDAC (Error Detection And Correction) reporting"
14 depends on HAS_IOMEM && EDAC_SUPPORT && RAS
15 help
16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
18 in the CPU or supporting chipset or other subsystems:
19 memory errors, cache errors, PCI errors, thermal throttling, etc..
20 If unsure, select 'Y'.
21
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
23
24if EDAC
25
26config EDAC_DEBUG
27 bool "Debugging"
28 select DEBUG_FS
29 help
30 This turns on debugging information for the entire EDAC subsystem.
31 You do so by inserting edac_module with "edac_debug_level=x." Valid
32 levels are 0-4 (from low to high) and by default it is set to 2.
33 Usually you should select 'N' here.
34
35config EDAC_DECODE_MCE
36 tristate "Decode MCEs in human-readable form (only on AMD for now)"
37 depends on CPU_SUP_AMD && X86_MCE_AMD
38 default y
39 help
40 Enable this option if you want to decode Machine Check Exceptions
41 occurring on your machine in human-readable form.
42
43 You should definitely say Y here in case you want to decode MCEs
44 which occur really early upon boot, before the module infrastructure
45 has been initialized.
46
47config EDAC_GHES
48 tristate "Output ACPI APEI/GHES BIOS detected errors via EDAC"
49 depends on ACPI_APEI_GHES
50 select UEFI_CPER
51 help
52 Not all machines support hardware-driven error report. Some of those
53 provide a BIOS-driven error report mechanism via ACPI, using the
54 APEI/GHES driver. By enabling this option, the error reports provided
55 by GHES are sent to userspace via the EDAC API.
56
57 When this option is enabled, it will disable the hardware-driven
58 mechanisms, if a GHES BIOS is detected, entering into the
59 "Firmware First" mode.
60
61 It should be noticed that keeping both GHES and a hardware-driven
62 error mechanism won't work well, as BIOS will race with OS, while
63 reading the error registers. So, if you want to not use "Firmware
64 first" GHES error mechanism, you should disable GHES either at
65 compilation time or by passing "ghes.disable=1" Kernel parameter
66 at boot time.
67
68 In doubt, say 'Y'.
69
70config EDAC_SCRUB
71 bool "EDAC scrub feature"
72 help
73 The EDAC scrub feature is optional and is designed to control the
74 memory scrubbers in the system. The common sysfs scrub interface
75 abstracts the control of various arbitrary scrubbing functionalities
76 into a unified set of functions.
77 Say 'y/n' to enable/disable EDAC scrub feature.
78
79config EDAC_ECS
80 bool "EDAC ECS (Error Check Scrub) feature"
81 help
82 The EDAC ECS feature is optional and is designed to control on-die
83 error check scrub (e.g., DDR5 ECS) in the system. The common sysfs
84 ECS interface abstracts the control of various ECS functionalities
85 into a unified set of functions.
86 Say 'y/n' to enable/disable EDAC ECS feature.
87
88config EDAC_MEM_REPAIR
89 bool "EDAC memory repair feature"
90 help
91 The EDAC memory repair feature is optional and is designed to control
92 the memory devices with repair features, such as Post Package Repair
93 (PPR), memory sparing etc. The common sysfs memory repair interface
94 abstracts the control of various memory repair functionalities into
95 a unified set of functions.
96 Say 'y/n' to enable/disable EDAC memory repair feature.
97
98config EDAC_AMD64
99 tristate "AMD64 (Opteron, Athlon64)"
100 depends on AMD_NB && EDAC_DECODE_MCE
101 depends on AMD_NODE
102 imply AMD_ATL
103 help
104 Support for error detection and correction of DRAM ECC errors on
105 the AMD64 families (>= K8) of memory controllers.
106
107 When EDAC_DEBUG is enabled, hardware error injection facilities
108 through sysfs are available:
109
110 AMD CPUs up to and excluding family 0x17 provide for Memory
111 Error Injection into the ECC detection circuits. The amd64_edac
112 module allows the operator/user to inject Uncorrectable and
113 Correctable errors into DRAM.
114
115 When enabled, in each of the respective memory controller directories
116 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
117
118 - inject_section (0..3, 16-byte section of 64-byte cacheline),
119 - inject_word (0..8, 16-bit word of 16-byte section),
120 - inject_ecc_vector (hex ecc vector: select bits of inject word)
121
122 In addition, there are two control files, inject_read and inject_write,
123 which trigger the DRAM ECC Read and Write respectively.
124
125config EDAC_AL_MC
126 tristate "Amazon's Annapurna Lab Memory Controller"
127 depends on (ARCH_ALPINE || COMPILE_TEST)
128 help
129 Support for error detection and correction for Amazon's Annapurna
130 Labs Alpine chips which allow 1 bit correction and 2 bits detection.
131
132config EDAC_AMD76X
133 tristate "AMD 76x (760, 762, 768)"
134 depends on PCI && X86_32
135 help
136 Support for error detection and correction on the AMD 76x
137 series of chipsets used with the Athlon processor.
138
139config EDAC_E7XXX
140 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
141 depends on PCI && X86_32
142 help
143 Support for error detection and correction on the Intel
144 E7205, E7500, E7501 and E7505 server chipsets.
145
146config EDAC_E752X
147 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
148 depends on PCI && X86
149 help
150 Support for error detection and correction on the Intel
151 E7520, E7525, E7320 server chipsets.
152
153config EDAC_I82443BXGX
154 tristate "Intel 82443BX/GX (440BX/GX)"
155 depends on PCI && X86_32
156 depends on BROKEN
157 help
158 Support for error detection and correction on the Intel
159 82443BX/GX memory controllers (440BX/GX chipsets).
160
161config EDAC_I82875P
162 tristate "Intel 82875p (D82875P, E7210)"
163 depends on PCI && X86_32
164 help
165 Support for error detection and correction on the Intel
166 DP82785P and E7210 server chipsets.
167
168config EDAC_I82975X
169 tristate "Intel 82975x (D82975x)"
170 depends on PCI && X86
171 help
172 Support for error detection and correction on the Intel
173 DP82975x server chipsets.
174
175config EDAC_I3000
176 tristate "Intel 3000/3010"
177 depends on PCI && X86
178 help
179 Support for error detection and correction on the Intel
180 3000 and 3010 server chipsets.
181
182config EDAC_I3200
183 tristate "Intel 3200"
184 depends on PCI && X86
185 help
186 Support for error detection and correction on the Intel
187 3200 and 3210 server chipsets.
188
189config EDAC_IE31200
190 tristate "Intel e312xx"
191 depends on PCI && X86 && X86_MCE_INTEL
192 help
193 Support for error detection and correction on the Intel
194 E3-1200 based DRAM controllers.
195
196config EDAC_X38
197 tristate "Intel X38"
198 depends on PCI && X86
199 help
200 Support for error detection and correction on the Intel
201 X38 server chipsets.
202
203config EDAC_I5400
204 tristate "Intel 5400 (Seaburg) chipsets"
205 depends on PCI && X86
206 help
207 Support for error detection and correction the Intel
208 i5400 MCH chipset (Seaburg).
209
210config EDAC_I7CORE
211 tristate "Intel i7 Core (Nehalem) processors"
212 depends on PCI && X86 && X86_MCE_INTEL
213 help
214 Support for error detection and correction the Intel
215 i7 Core (Nehalem) Integrated Memory Controller that exists on
216 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
217 and Xeon 55xx processors.
218
219config EDAC_I82860
220 tristate "Intel 82860"
221 depends on PCI && X86_32
222 help
223 Support for error detection and correction on the Intel
224 82860 chipset.
225
226config EDAC_R82600
227 tristate "Radisys 82600 embedded chipset"
228 depends on PCI && X86_32
229 help
230 Support for error detection and correction on the Radisys
231 82600 embedded chipset.
232
233config EDAC_I5000
234 tristate "Intel Greencreek/Blackford chipset"
235 depends on X86 && PCI
236 depends on BROKEN
237 help
238 Support for error detection and correction the Intel
239 Greekcreek/Blackford chipsets.
240
241config EDAC_I5100
242 tristate "Intel San Clemente MCH"
243 depends on X86 && PCI
244 help
245 Support for error detection and correction the Intel
246 San Clemente MCH.
247
248config EDAC_I7300
249 tristate "Intel Clarksboro MCH"
250 depends on X86 && PCI
251 help
252 Support for error detection and correction the Intel
253 Clarksboro MCH (Intel 7300 chipset).
254
255config EDAC_SBRIDGE
256 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
257 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
258 help
259 Support for error detection and correction the Intel
260 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
261
262config EDAC_SKX
263 tristate "Intel Skylake server Integrated MC"
264 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
265 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y
266 select DMI
267 select ACPI_ADXL
268 help
269 Support for error detection and correction the Intel
270 Skylake server Integrated Memory Controllers. If your
271 system has non-volatile DIMMs you should also manually
272 select CONFIG_ACPI_NFIT.
273
274config EDAC_I10NM
275 tristate "Intel 10nm server Integrated MC"
276 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
277 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y
278 select DMI
279 select ACPI_ADXL
280 help
281 Support for error detection and correction the Intel
282 10nm server Integrated Memory Controllers. If your
283 system has non-volatile DIMMs you should also manually
284 select CONFIG_ACPI_NFIT.
285
286config EDAC_IMH
287 tristate "Intel Integrated Memory/IO Hub MC"
288 depends on X86_64 && X86_MCE_INTEL && ACPI
289 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_IMH can't be y
290 select DMI
291 select ACPI_ADXL
292 help
293 Support for error detection and correction the Intel
294 Integrated Memory/IO Hub Memory Controller. This MC IP is
295 first used on the Diamond Rapids servers but may appear on
296 others in the future.
297
298config EDAC_PND2
299 tristate "Intel Pondicherry2"
300 depends on PCI && X86_64 && X86_MCE_INTEL
301 select P2SB if X86
302 help
303 Support for error detection and correction on the Intel
304 Pondicherry2 Integrated Memory Controller. This SoC IP is
305 first used on the Apollo Lake platform and Denverton
306 micro-server but may appear on others in the future.
307
308config EDAC_IGEN6
309 tristate "Intel client SoC Integrated MC"
310 depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG
311 depends on X86_64 && X86_MCE_INTEL
312 help
313 Support for error detection and correction on the Intel
314 client SoC Integrated Memory Controller using In-Band ECC IP.
315 This In-Band ECC is first used on the Elkhart Lake SoC but
316 may appear on others in the future.
317
318config EDAC_MPC85XX
319 bool "Freescale MPC83xx / MPC85xx"
320 depends on FSL_SOC && EDAC=y
321 help
322 Support for error detection and correction on the Freescale
323 MPC8349, MPC8560, MPC8540, MPC8548, T4240
324
325config EDAC_LAYERSCAPE
326 tristate "Freescale Layerscape DDR"
327 depends on ARCH_LAYERSCAPE || SOC_LS1021A
328 help
329 Support for error detection and correction on Freescale memory
330 controllers on Layerscape SoCs.
331
332config EDAC_PASEMI
333 tristate "PA Semi PWRficient"
334 depends on PPC_PASEMI && PCI
335 help
336 Support for error detection and correction on PA Semi
337 PWRficient.
338
339config EDAC_CPC925
340 tristate "IBM CPC925 Memory Controller (PPC970FX)"
341 depends on PPC64
342 help
343 Support for error detection and correction on the
344 IBM CPC925 Bridge and Memory Controller, which is
345 a companion chip to the PowerPC 970 family of
346 processors.
347
348config EDAC_HIGHBANK_MC
349 tristate "Highbank Memory Controller"
350 depends on ARCH_HIGHBANK
351 help
352 Support for error detection and correction on the
353 Calxeda Highbank memory controller.
354
355config EDAC_HIGHBANK_L2
356 tristate "Highbank L2 Cache"
357 depends on ARCH_HIGHBANK
358 help
359 Support for error detection and correction on the
360 Calxeda Highbank memory controller.
361
362config EDAC_OCTEON_PC
363 tristate "Cavium Octeon Primary Caches"
364 depends on CPU_CAVIUM_OCTEON
365 help
366 Support for error detection and correction on the primary caches of
367 the cnMIPS cores of Cavium Octeon family SOCs.
368
369config EDAC_OCTEON_L2C
370 tristate "Cavium Octeon Secondary Caches (L2C)"
371 depends on CAVIUM_OCTEON_SOC
372 help
373 Support for error detection and correction on the
374 Cavium Octeon family of SOCs.
375
376config EDAC_OCTEON_LMC
377 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
378 depends on CAVIUM_OCTEON_SOC
379 help
380 Support for error detection and correction on the
381 Cavium Octeon family of SOCs.
382
383config EDAC_OCTEON_PCI
384 tristate "Cavium Octeon PCI Controller"
385 depends on PCI && CAVIUM_OCTEON_SOC
386 help
387 Support for error detection and correction on the
388 Cavium Octeon family of SOCs.
389
390config EDAC_THUNDERX
391 tristate "Cavium ThunderX EDAC"
392 depends on ARM64
393 depends on PCI
394 help
395 Support for error detection and correction on the
396 Cavium ThunderX memory controllers (LMC), Cache
397 Coherent Processor Interconnect (CCPI) and L2 cache
398 blocks (TAD, CBC, MCI).
399
400config EDAC_ALTERA
401 bool "Altera SOCFPGA ECC"
402 depends on EDAC=y && ARCH_INTEL_SOCFPGA
403 help
404 Support for error detection and correction on the
405 Altera SOCs. This is the global enable for the
406 various Altera peripherals.
407
408config EDAC_ALTERA_SDRAM
409 bool "Altera SDRAM ECC"
410 depends on EDAC_ALTERA=y
411 help
412 Support for error detection and correction on the
413 Altera SDRAM Memory for Altera SoCs. Note that the
414 preloader must initialize the SDRAM before loading
415 the kernel.
416
417config EDAC_ALTERA_L2C
418 bool "Altera L2 Cache ECC"
419 depends on EDAC_ALTERA=y && CACHE_L2X0
420 help
421 Support for error detection and correction on the
422 Altera L2 cache Memory for Altera SoCs. This option
423 requires L2 cache.
424
425config EDAC_ALTERA_OCRAM
426 bool "Altera On-Chip RAM ECC"
427 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
428 help
429 Support for error detection and correction on the
430 Altera On-Chip RAM Memory for Altera SoCs.
431
432config EDAC_ALTERA_ETHERNET
433 bool "Altera Ethernet FIFO ECC"
434 depends on EDAC_ALTERA=y
435 help
436 Support for error detection and correction on the
437 Altera Ethernet FIFO Memory for Altera SoCs.
438
439config EDAC_ALTERA_NAND
440 bool "Altera NAND FIFO ECC"
441 depends on EDAC_ALTERA=y && MTD_NAND_DENALI
442 help
443 Support for error detection and correction on the
444 Altera NAND FIFO Memory for Altera SoCs.
445
446config EDAC_ALTERA_DMA
447 bool "Altera DMA FIFO ECC"
448 depends on EDAC_ALTERA=y && PL330_DMA=y
449 help
450 Support for error detection and correction on the
451 Altera DMA FIFO Memory for Altera SoCs.
452
453config EDAC_ALTERA_USB
454 bool "Altera USB FIFO ECC"
455 depends on EDAC_ALTERA=y && USB_DWC2
456 help
457 Support for error detection and correction on the
458 Altera USB FIFO Memory for Altera SoCs.
459
460config EDAC_ALTERA_QSPI
461 bool "Altera QSPI FIFO ECC"
462 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
463 help
464 Support for error detection and correction on the
465 Altera QSPI FIFO Memory for Altera SoCs.
466
467config EDAC_ALTERA_SDMMC
468 bool "Altera SDMMC FIFO ECC"
469 depends on EDAC_ALTERA=y && MMC_DW
470 help
471 Support for error detection and correction on the
472 Altera SDMMC FIFO Memory for Altera SoCs.
473
474config EDAC_SIFIVE
475 bool "Sifive platform EDAC driver"
476 depends on EDAC=y && SIFIVE_CCACHE
477 help
478 Support for error detection and correction on the SiFive SoCs.
479
480config EDAC_ARMADA_XP
481 bool "Marvell Armada XP DDR and L2 Cache ECC"
482 depends on MACH_MVEBU_V7
483 help
484 Support for error correction and detection on the Marvell Aramada XP
485 DDR RAM and L2 cache controllers.
486
487config EDAC_SYNOPSYS
488 tristate "Synopsys DDR Memory Controller"
489 depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || ARCH_MXC
490 help
491 Support for error detection and correction on the Synopsys DDR
492 memory controller.
493
494config EDAC_XGENE
495 tristate "APM X-Gene SoC"
496 depends on (ARM64 || COMPILE_TEST)
497 help
498 Support for error detection and correction on the
499 APM X-Gene family of SOCs.
500
501config EDAC_TI
502 tristate "Texas Instruments DDR3 ECC Controller"
503 depends on ARCH_KEYSTONE || SOC_DRA7XX
504 help
505 Support for error detection and correction on the TI SoCs.
506
507config EDAC_QCOM
508 tristate "QCOM EDAC Controller"
509 depends on ARCH_QCOM && QCOM_LLCC
510 help
511 Support for error detection and correction on the
512 Qualcomm Technologies, Inc. SoCs.
513
514 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).
515 As of now, it supports error reporting for Last Level Cache Controller (LLCC)
516 of Tag RAM and Data RAM.
517
518 For debugging issues having to do with stability and overall system
519 health, you should probably say 'Y' here.
520
521config EDAC_ASPEED
522 tristate "Aspeed AST BMC SoC"
523 depends on ARCH_ASPEED
524 help
525 Support for error detection and correction on the Aspeed AST BMC SoC.
526
527 First, ECC must be configured in the bootloader. Then, this driver
528 will expose error counters via the EDAC kernel framework.
529
530config EDAC_BLUEFIELD
531 tristate "Mellanox BlueField Memory ECC"
532 depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST)
533 help
534 Support for error detection and correction on the
535 Mellanox BlueField SoCs.
536
537config EDAC_DMC520
538 tristate "ARM DMC-520 ECC"
539 depends on ARM64
540 help
541 Support for error detection and correction on the
542 SoCs with ARM DMC-520 DRAM controller.
543
544config EDAC_ZYNQMP
545 tristate "Xilinx ZynqMP OCM Controller"
546 depends on ARCH_ZYNQMP || COMPILE_TEST
547 help
548 This driver supports error detection and correction for the
549 Xilinx ZynqMP OCM (On Chip Memory) controller. It can also be
550 built as a module. In that case it will be called zynqmp_edac.
551
552config EDAC_NPCM
553 tristate "Nuvoton NPCM DDR Memory Controller"
554 depends on (ARCH_NPCM || COMPILE_TEST)
555 help
556 Support for error detection and correction on the Nuvoton NPCM DDR
557 memory controller.
558
559 The memory controller supports single bit error correction, double bit
560 error detection (in-line ECC in which a section 1/8th of the memory
561 device used to store data is used for ECC storage).
562
563config EDAC_VERSAL
564 tristate "Xilinx Versal DDR Memory Controller"
565 depends on ARCH_ZYNQMP || COMPILE_TEST
566 help
567 Support for error detection and correction on the Xilinx Versal DDR
568 memory controller.
569
570 Report both single bit errors (CE) and double bit errors (UE).
571 Support injecting both correctable and uncorrectable errors
572 for debugging purposes.
573
574config EDAC_LOONGSON
575 tristate "Loongson Memory Controller"
576 depends on LOONGARCH && ACPI
577 help
578 Support for error detection and correction on the Loongson
579 family memory controller. This driver reports single bit
580 errors (CE) only. Loongson-3A5000/3C5000/3D5000/3A6000/3C6000
581 are compatible.
582
583config EDAC_CORTEX_A72
584 tristate "ARM Cortex A72"
585 depends on ARM64
586 help
587 Support for L1/L2 cache error detection for ARM Cortex A72 processor.
588 The detected and reported errors are from reading CPU/L2 memory error
589 syndrome registers.
590
591config EDAC_VERSALNET
592 tristate "AMD VersalNET DDR Controller"
593 depends on CDX_CONTROLLER && ARCH_ZYNQMP
594 help
595 Support for single bit error correction, double bit error detection
596 and other system errors from various IP subsystems like RPU, NOCs,
597 HNICX, PL on the AMD Versal NET DDR memory controller.
598
599endif # EDAC