tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2024, Advanced Micro Devices, Inc.
4 */
5
6#include <drm/amdxdna_accel.h>
7#include <drm/drm_device.h>
8#include <drm/gpu_scheduler.h>
9#include <linux/sizes.h>
10
11#include "aie2_pci.h"
12#include "amdxdna_mailbox.h"
13#include "amdxdna_pci_drv.h"
14
15/* NPU Public Registers on MpNPUAxiXbar (refer to Diag npu_registers.h) */
16#define MPNPU_PWAITMODE 0x301003C
17#define MPNPU_PUB_SEC_INTR 0x3010060
18#define MPNPU_PUB_PWRMGMT_INTR 0x3010064
19#define MPNPU_PUB_SCRATCH0 0x301006C
20#define MPNPU_PUB_SCRATCH1 0x3010070
21#define MPNPU_PUB_SCRATCH2 0x3010074
22#define MPNPU_PUB_SCRATCH3 0x3010078
23#define MPNPU_PUB_SCRATCH4 0x301007C
24#define MPNPU_PUB_SCRATCH5 0x3010080
25#define MPNPU_PUB_SCRATCH6 0x3010084
26#define MPNPU_PUB_SCRATCH7 0x3010088
27#define MPNPU_PUB_SCRATCH8 0x301008C
28#define MPNPU_PUB_SCRATCH9 0x3010090
29#define MPNPU_PUB_SCRATCH10 0x3010094
30#define MPNPU_PUB_SCRATCH11 0x3010098
31#define MPNPU_PUB_SCRATCH12 0x301009C
32#define MPNPU_PUB_SCRATCH13 0x30100A0
33#define MPNPU_PUB_SCRATCH14 0x30100A4
34#define MPNPU_PUB_SCRATCH15 0x30100A8
35#define MP0_C2PMSG_73 0x3810A24
36#define MP0_C2PMSG_123 0x3810AEC
37
38#define MP1_C2PMSG_0 0x3B10900
39#define MP1_C2PMSG_60 0x3B109F0
40#define MP1_C2PMSG_61 0x3B109F4
41
42#define MPNPU_SRAM_X2I_MAILBOX_0 0x3600000
43#define MPNPU_SRAM_X2I_MAILBOX_15 0x361E000
44#define MPNPU_SRAM_X2I_MAILBOX_31 0x363E000
45#define MPNPU_SRAM_I2X_MAILBOX_31 0x363F000
46
47#define MMNPU_APERTURE0_BASE 0x3000000
48#define MMNPU_APERTURE1_BASE 0x3600000
49#define MMNPU_APERTURE3_BASE 0x3810000
50#define MMNPU_APERTURE4_BASE 0x3B10000
51
52/* PCIe BAR Index for NPU6 */
53#define NPU6_REG_BAR_INDEX 0
54#define NPU6_MBOX_BAR_INDEX 0
55#define NPU6_PSP_BAR_INDEX 4
56#define NPU6_SMU_BAR_INDEX 5
57#define NPU6_SRAM_BAR_INDEX 2
58/* Associated BARs and Apertures */
59#define NPU6_REG_BAR_BASE MMNPU_APERTURE0_BASE
60#define NPU6_MBOX_BAR_BASE MMNPU_APERTURE0_BASE
61#define NPU6_PSP_BAR_BASE MMNPU_APERTURE3_BASE
62#define NPU6_SMU_BAR_BASE MMNPU_APERTURE4_BASE
63#define NPU6_SRAM_BAR_BASE MMNPU_APERTURE1_BASE
64
65static const struct amdxdna_dev_priv npu6_dev_priv = {
66 .fw_path = "amdnpu/17f0_10/",
67 .rt_config = npu4_default_rt_cfg,
68 .dpm_clk_tbl = npu4_dpm_clk_table,
69 .fw_feature_tbl = npu4_fw_feature_table,
70 .col_align = COL_ALIGN_NATURE,
71 .mbox_dev_addr = NPU6_MBOX_BAR_BASE,
72 .mbox_size = 0, /* Use BAR size */
73 .sram_dev_addr = NPU6_SRAM_BAR_BASE,
74 .hwctx_limit = 16,
75 .sram_offs = {
76 DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU6_SRAM, MPNPU_SRAM_X2I_MAILBOX_0),
77 DEFINE_BAR_OFFSET(FW_ALIVE_OFF, NPU6_SRAM, MPNPU_SRAM_X2I_MAILBOX_15),
78 },
79 .psp_regs_off = {
80 DEFINE_BAR_OFFSET(PSP_CMD_REG, NPU6_PSP, MP0_C2PMSG_123),
81 DEFINE_BAR_OFFSET(PSP_ARG0_REG, NPU6_REG, MPNPU_PUB_SCRATCH3),
82 DEFINE_BAR_OFFSET(PSP_ARG1_REG, NPU6_REG, MPNPU_PUB_SCRATCH4),
83 DEFINE_BAR_OFFSET(PSP_ARG2_REG, NPU6_REG, MPNPU_PUB_SCRATCH9),
84 DEFINE_BAR_OFFSET(PSP_INTR_REG, NPU6_PSP, MP0_C2PMSG_73),
85 DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU6_PSP, MP0_C2PMSG_123),
86 DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU6_REG, MPNPU_PUB_SCRATCH3),
87 DEFINE_BAR_OFFSET(PSP_PWAITMODE_REG, NPU6_REG, MPNPU_PWAITMODE),
88 },
89 .smu_regs_off = {
90 DEFINE_BAR_OFFSET(SMU_CMD_REG, NPU6_SMU, MP1_C2PMSG_0),
91 DEFINE_BAR_OFFSET(SMU_ARG_REG, NPU6_SMU, MP1_C2PMSG_60),
92 DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU6_SMU, MMNPU_APERTURE4_BASE),
93 DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU6_SMU, MP1_C2PMSG_61),
94 DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU6_SMU, MP1_C2PMSG_60),
95 },
96 .hw_ops = {
97 .set_dpm = npu4_set_dpm,
98 },
99
100};
101
102const struct amdxdna_dev_info dev_npu6_info = {
103 .reg_bar = NPU6_REG_BAR_INDEX,
104 .mbox_bar = NPU6_MBOX_BAR_INDEX,
105 .sram_bar = NPU6_SRAM_BAR_INDEX,
106 .psp_bar = NPU6_PSP_BAR_INDEX,
107 .smu_bar = NPU6_SMU_BAR_INDEX,
108 .first_col = 0,
109 .dev_mem_buf_shift = 15, /* 32 KiB aligned */
110 .dev_mem_base = AIE2_DEVM_BASE,
111 .dev_mem_size = AIE2_DEVM_SIZE,
112 .vbnv = "RyzenAI-npu6",
113 .device_type = AMDXDNA_DEV_TYPE_KMQ,
114 .dev_priv = &npu6_dev_priv,
115 .ops = &aie2_ops,
116};