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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S
4 *
5 * Copyright (C) 1996-2000 Russell King
6 * Copyright (C) 2012 ARM Ltd.
7 */
8#ifndef __ASSEMBLER__
9#error "Only include this from assembly code"
10#endif
11
12#ifndef __ASM_ASSEMBLER_H
13#define __ASM_ASSEMBLER_H
14
15#include <linux/export.h>
16
17#include <asm/alternative.h>
18#include <asm/asm-bug.h>
19#include <asm/asm-extable.h>
20#include <asm/asm-offsets.h>
21#include <asm/cpufeature.h>
22#include <asm/cputype.h>
23#include <asm/debug-monitors.h>
24#include <asm/page.h>
25#include <asm/pgtable-hwdef.h>
26#include <asm/ptrace.h>
27#include <asm/thread_info.h>
28
29 /*
30 * Provide a wxN alias for each wN register so what we can paste a xN
31 * reference after a 'w' to obtain the 32-bit version.
32 */
33 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
34 wx\n .req w\n
35 .endr
36
37 .macro disable_daif
38 msr daifset, #0xf
39 .endm
40
41/*
42 * Save/restore interrupts.
43 */
44 .macro save_and_disable_daif, flags
45 mrs \flags, daif
46 msr daifset, #0xf
47 .endm
48
49 .macro save_and_disable_irq, flags
50 mrs \flags, daif
51 msr daifset, #3
52 .endm
53
54 .macro restore_irq, flags
55 msr daif, \flags
56 .endm
57
58 .macro disable_step_tsk, flgs, tmp
59 tbz \flgs, #TIF_SINGLESTEP, 9990f
60 mrs \tmp, mdscr_el1
61 bic \tmp, \tmp, #MDSCR_EL1_SS
62 msr mdscr_el1, \tmp
63 isb // Take effect before a subsequent clear of DAIF.D
649990:
65 .endm
66
67 /* call with daif masked */
68 .macro enable_step_tsk, flgs, tmp
69 tbz \flgs, #TIF_SINGLESTEP, 9990f
70 mrs \tmp, mdscr_el1
71 orr \tmp, \tmp, #MDSCR_EL1_SS
72 msr mdscr_el1, \tmp
739990:
74 .endm
75
76/*
77 * RAS Error Synchronization barrier
78 */
79 .macro esb
80#ifdef CONFIG_ARM64_RAS_EXTN
81 hint #16
82#else
83 nop
84#endif
85 .endm
86
87/*
88 * Value prediction barrier
89 */
90 .macro csdb
91 hint #20
92 .endm
93
94/*
95 * Clear Branch History instruction
96 */
97 .macro clearbhb
98 hint #22
99 .endm
100
101/*
102 * Speculation barrier
103 */
104 .macro sb
105alternative_if_not ARM64_HAS_SB
106 dsb nsh
107 isb
108alternative_else
109 SB_BARRIER_INSN
110 nop
111alternative_endif
112 .endm
113
114/*
115 * NOP sequence
116 */
117 .macro nops, num
118 .rept \num
119 nop
120 .endr
121 .endm
122
123/*
124 * Register aliases.
125 */
126lr .req x30 // link register
127
128/*
129 * Vector entry
130 */
131 .macro ventry label
132 .align 7
133 b \label
134 .endm
135
136/*
137 * Select code when configured for BE.
138 */
139#ifdef CONFIG_CPU_BIG_ENDIAN
140#define CPU_BE(code...) code
141#else
142#define CPU_BE(code...)
143#endif
144
145/*
146 * Select code when configured for LE.
147 */
148#ifdef CONFIG_CPU_BIG_ENDIAN
149#define CPU_LE(code...)
150#else
151#define CPU_LE(code...) code
152#endif
153
154/*
155 * Define a macro that constructs a 64-bit value by concatenating two
156 * 32-bit registers. Note that on big endian systems the order of the
157 * registers is swapped.
158 */
159#ifndef CONFIG_CPU_BIG_ENDIAN
160 .macro regs_to_64, rd, lbits, hbits
161#else
162 .macro regs_to_64, rd, hbits, lbits
163#endif
164 orr \rd, \lbits, \hbits, lsl #32
165 .endm
166
167/*
168 * Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
169 * <symbol> is within the range +/- 4 GB of the PC.
170 */
171 /*
172 * @dst: destination register (64 bit wide)
173 * @sym: name of the symbol
174 */
175 .macro adr_l, dst, sym
176 adrp \dst, \sym
177 add \dst, \dst, :lo12:\sym
178 .endm
179
180 /*
181 * @dst: destination register (32 or 64 bit wide)
182 * @sym: name of the symbol
183 * @tmp: optional 64-bit scratch register to be used if <dst> is a
184 * 32-bit wide register, in which case it cannot be used to hold
185 * the address
186 */
187 .macro ldr_l, dst, sym, tmp=
188 .ifb \tmp
189 adrp \dst, \sym
190 ldr \dst, [\dst, :lo12:\sym]
191 .else
192 adrp \tmp, \sym
193 ldr \dst, [\tmp, :lo12:\sym]
194 .endif
195 .endm
196
197 /*
198 * @src: source register (32 or 64 bit wide)
199 * @sym: name of the symbol
200 * @tmp: mandatory 64-bit scratch register to calculate the address
201 * while <src> needs to be preserved.
202 */
203 .macro str_l, src, sym, tmp
204 adrp \tmp, \sym
205 str \src, [\tmp, :lo12:\sym]
206 .endm
207
208 /*
209 * @dst: destination register
210 */
211#if defined(__KVM_NVHE_HYPERVISOR__) || defined(__KVM_VHE_HYPERVISOR__)
212 .macro get_this_cpu_offset, dst
213 mrs \dst, tpidr_el2
214 .endm
215#else
216 .macro get_this_cpu_offset, dst
217alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
218 mrs \dst, tpidr_el1
219alternative_else
220 mrs \dst, tpidr_el2
221alternative_endif
222 .endm
223
224 .macro set_this_cpu_offset, src
225alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
226 msr tpidr_el1, \src
227alternative_else
228 msr tpidr_el2, \src
229alternative_endif
230 .endm
231#endif
232
233 /*
234 * @dst: Result of per_cpu(sym, smp_processor_id()) (can be SP)
235 * @sym: The name of the per-cpu variable
236 * @tmp: scratch register
237 */
238 .macro adr_this_cpu, dst, sym, tmp
239 adrp \tmp, \sym
240 add \dst, \tmp, #:lo12:\sym
241 get_this_cpu_offset \tmp
242 add \dst, \dst, \tmp
243 .endm
244
245 /*
246 * @dst: Result of READ_ONCE(per_cpu(sym, smp_processor_id()))
247 * @sym: The name of the per-cpu variable
248 * @tmp: scratch register
249 */
250 .macro ldr_this_cpu dst, sym, tmp
251 adr_l \dst, \sym
252 get_this_cpu_offset \tmp
253 ldr \dst, [\dst, \tmp]
254 .endm
255
256/*
257 * read_ctr - read CTR_EL0. If the system has mismatched register fields,
258 * provide the system wide safe value from arm64_ftr_reg_ctrel0.sys_val
259 */
260 .macro read_ctr, reg
261#ifndef __KVM_NVHE_HYPERVISOR__
262alternative_if_not ARM64_MISMATCHED_CACHE_TYPE
263 mrs \reg, ctr_el0 // read CTR
264 nop
265alternative_else
266 ldr_l \reg, arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL
267alternative_endif
268#else
269alternative_if_not ARM64_KVM_PROTECTED_MODE
270 ASM_BUG()
271alternative_else_nop_endif
272alternative_cb ARM64_ALWAYS_SYSTEM, kvm_compute_final_ctr_el0
273 movz \reg, #0
274 movk \reg, #0, lsl #16
275 movk \reg, #0, lsl #32
276 movk \reg, #0, lsl #48
277alternative_cb_end
278#endif
279 .endm
280
281
282/*
283 * raw_dcache_line_size - get the minimum D-cache line size on this CPU
284 * from the CTR register.
285 */
286 .macro raw_dcache_line_size, reg, tmp
287 mrs \tmp, ctr_el0 // read CTR
288 ubfm \tmp, \tmp, #16, #19 // cache line size encoding
289 mov \reg, #4 // bytes per word
290 lsl \reg, \reg, \tmp // actual cache line size
291 .endm
292
293/*
294 * dcache_line_size - get the safe D-cache line size across all CPUs
295 */
296 .macro dcache_line_size, reg, tmp
297 read_ctr \tmp
298 ubfm \tmp, \tmp, #16, #19 // cache line size encoding
299 mov \reg, #4 // bytes per word
300 lsl \reg, \reg, \tmp // actual cache line size
301 .endm
302
303/*
304 * raw_icache_line_size - get the minimum I-cache line size on this CPU
305 * from the CTR register.
306 */
307 .macro raw_icache_line_size, reg, tmp
308 mrs \tmp, ctr_el0 // read CTR
309 and \tmp, \tmp, #0xf // cache line size encoding
310 mov \reg, #4 // bytes per word
311 lsl \reg, \reg, \tmp // actual cache line size
312 .endm
313
314/*
315 * icache_line_size - get the safe I-cache line size across all CPUs
316 */
317 .macro icache_line_size, reg, tmp
318 read_ctr \tmp
319 and \tmp, \tmp, #0xf // cache line size encoding
320 mov \reg, #4 // bytes per word
321 lsl \reg, \reg, \tmp // actual cache line size
322 .endm
323
324/*
325 * tcr_set_t0sz - update TCR.T0SZ so that we can load the ID map
326 */
327 .macro tcr_set_t0sz, valreg, t0sz
328 bfi \valreg, \t0sz, #TCR_EL1_T0SZ_SHIFT, #TCR_EL1_T0SZ_WIDTH
329 .endm
330
331/*
332 * tcr_set_t1sz - update TCR.T1SZ
333 */
334 .macro tcr_set_t1sz, valreg, t1sz
335 bfi \valreg, \t1sz, #TCR_EL1_T1SZ_SHIFT, #TCR_EL1_T1SZ_WIDTH
336 .endm
337
338/*
339 * tcr_compute_pa_size - set TCR.(I)PS to the highest supported
340 * ID_AA64MMFR0_EL1.PARange value
341 *
342 * tcr: register with the TCR_ELx value to be updated
343 * pos: IPS or PS bitfield position
344 * tmp{0,1}: temporary registers
345 */
346 .macro tcr_compute_pa_size, tcr, pos, tmp0, tmp1
347 mrs \tmp0, ID_AA64MMFR0_EL1
348 // Narrow PARange to fit the PS field in TCR_ELx
349 ubfx \tmp0, \tmp0, #ID_AA64MMFR0_EL1_PARANGE_SHIFT, #3
350 mov \tmp1, #ID_AA64MMFR0_EL1_PARANGE_MAX
351#ifdef CONFIG_ARM64_LPA2
352alternative_if_not ARM64_HAS_VA52
353 mov \tmp1, #ID_AA64MMFR0_EL1_PARANGE_48
354alternative_else_nop_endif
355#endif
356 cmp \tmp0, \tmp1
357 csel \tmp0, \tmp1, \tmp0, hi
358 bfi \tcr, \tmp0, \pos, #3
359 .endm
360
361 .macro __dcache_op_workaround_clean_cache, op, addr
362alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE
363 dc \op, \addr
364alternative_else
365 dc civac, \addr
366alternative_endif
367 .endm
368
369/*
370 * Macro to perform a data cache maintenance for the interval
371 * [start, end) with dcache line size explicitly provided.
372 *
373 * op: operation passed to dc instruction
374 * domain: domain used in dsb instruction
375 * start: starting virtual address of the region
376 * end: end virtual address of the region
377 * linesz: dcache line size
378 * fixup: optional label to branch to on user fault
379 * Corrupts: start, end, tmp
380 */
381 .macro dcache_by_myline_op op, domain, start, end, linesz, tmp, fixup
382 sub \tmp, \linesz, #1
383 bic \start, \start, \tmp
384.Ldcache_op\@:
385 .ifc \op, cvau
386 __dcache_op_workaround_clean_cache \op, \start
387 .else
388 .ifc \op, cvac
389 __dcache_op_workaround_clean_cache \op, \start
390 .else
391 .ifc \op, cvap
392 sys 3, c7, c12, 1, \start // dc cvap
393 .else
394 .ifc \op, cvadp
395 sys 3, c7, c13, 1, \start // dc cvadp
396 .else
397 dc \op, \start
398 .endif
399 .endif
400 .endif
401 .endif
402 add \start, \start, \linesz
403 cmp \start, \end
404 b.lo .Ldcache_op\@
405 dsb \domain
406
407 _cond_uaccess_extable .Ldcache_op\@, \fixup
408 .endm
409
410/*
411 * Macro to perform a data cache maintenance for the interval
412 * [start, end)
413 *
414 * op: operation passed to dc instruction
415 * domain: domain used in dsb instruction
416 * start: starting virtual address of the region
417 * end: end virtual address of the region
418 * fixup: optional label to branch to on user fault
419 * Corrupts: start, end, tmp1, tmp2
420 */
421 .macro dcache_by_line_op op, domain, start, end, tmp1, tmp2, fixup
422 dcache_line_size \tmp1, \tmp2
423 dcache_by_myline_op \op, \domain, \start, \end, \tmp1, \tmp2, \fixup
424 .endm
425
426/*
427 * Macro to perform an instruction cache maintenance for the interval
428 * [start, end)
429 *
430 * start, end: virtual addresses describing the region
431 * fixup: optional label to branch to on user fault
432 * Corrupts: tmp1, tmp2
433 */
434 .macro invalidate_icache_by_line start, end, tmp1, tmp2, fixup
435 icache_line_size \tmp1, \tmp2
436 sub \tmp2, \tmp1, #1
437 bic \tmp2, \start, \tmp2
438.Licache_op\@:
439 ic ivau, \tmp2 // invalidate I line PoU
440 add \tmp2, \tmp2, \tmp1
441 cmp \tmp2, \end
442 b.lo .Licache_op\@
443 dsb ish
444 isb
445
446 _cond_uaccess_extable .Licache_op\@, \fixup
447 .endm
448
449/*
450 * load_ttbr1 - install @pgtbl as a TTBR1 page table
451 * pgtbl preserved
452 * tmp1/tmp2 clobbered, either may overlap with pgtbl
453 */
454 .macro load_ttbr1, pgtbl, tmp1, tmp2
455 phys_to_ttbr \tmp1, \pgtbl
456 offset_ttbr1 \tmp1, \tmp2
457 msr ttbr1_el1, \tmp1
458 isb
459 .endm
460
461/*
462 * To prevent the possibility of old and new partial table walks being visible
463 * in the tlb, switch the ttbr to a zero page when we invalidate the old
464 * records. D4.7.1 'General TLB maintenance requirements' in ARM DDI 0487A.i
465 * Even switching to our copied tables will cause a changed output address at
466 * each stage of the walk.
467 */
468 .macro break_before_make_ttbr_switch zero_page, page_table, tmp, tmp2
469 phys_to_ttbr \tmp, \zero_page
470 msr ttbr1_el1, \tmp
471 isb
472 tlbi vmalle1
473 dsb nsh
474 load_ttbr1 \page_table, \tmp, \tmp2
475 .endm
476
477/*
478 * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present
479 */
480 .macro reset_pmuserenr_el0, tmpreg
481 mrs \tmpreg, id_aa64dfr0_el1
482 ubfx \tmpreg, \tmpreg, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
483 cmp \tmpreg, #ID_AA64DFR0_EL1_PMUVer_NI
484 ccmp \tmpreg, #ID_AA64DFR0_EL1_PMUVer_IMP_DEF, #4, ne
485 b.eq 9000f // Skip if no PMU present or IMP_DEF
486 msr pmuserenr_el0, xzr // Disable PMU access from EL0
4879000:
488 .endm
489
490/*
491 * reset_amuserenr_el0 - reset AMUSERENR_EL0 if AMUv1 present
492 */
493 .macro reset_amuserenr_el0, tmpreg
494 mrs \tmpreg, id_aa64pfr0_el1 // Check ID_AA64PFR0_EL1
495 ubfx \tmpreg, \tmpreg, #ID_AA64PFR0_EL1_AMU_SHIFT, #4
496 cbz \tmpreg, .Lskip_\@ // Skip if no AMU present
497 msr_s SYS_AMUSERENR_EL0, xzr // Disable AMU access from EL0
498.Lskip_\@:
499 .endm
500/*
501 * copy_page - copy src to dest using temp registers t1-t8
502 */
503 .macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req
5049998: ldp \t1, \t2, [\src]
505 ldp \t3, \t4, [\src, #16]
506 ldp \t5, \t6, [\src, #32]
507 ldp \t7, \t8, [\src, #48]
508 add \src, \src, #64
509 stnp \t1, \t2, [\dest]
510 stnp \t3, \t4, [\dest, #16]
511 stnp \t5, \t6, [\dest, #32]
512 stnp \t7, \t8, [\dest, #48]
513 add \dest, \dest, #64
514 tst \src, #(PAGE_SIZE - 1)
515 b.ne 9998b
516 .endm
517
518/*
519 * Annotate a function as being unsuitable for kprobes.
520 */
521#ifdef CONFIG_KPROBES
522#define NOKPROBE(x) \
523 .pushsection "_kprobe_blacklist", "aw"; \
524 .quad x; \
525 .popsection;
526#else
527#define NOKPROBE(x)
528#endif
529
530#if defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS)
531#define EXPORT_SYMBOL_NOKASAN(name)
532#else
533#define EXPORT_SYMBOL_NOKASAN(name) EXPORT_SYMBOL(name)
534#endif
535
536 /*
537 * Emit a 64-bit absolute little endian symbol reference in a way that
538 * ensures that it will be resolved at build time, even when building a
539 * PIE binary. This requires cooperation from the linker script, which
540 * must emit the lo32/hi32 halves individually.
541 */
542 .macro le64sym, sym
543 .long \sym\()_lo32
544 .long \sym\()_hi32
545 .endm
546
547 /*
548 * mov_q - move an immediate constant into a 64-bit register using
549 * between 2 and 4 movz/movk instructions (depending on the
550 * magnitude and sign of the operand)
551 */
552 .macro mov_q, reg, val
553 .if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff)
554 movz \reg, :abs_g1_s:\val
555 .else
556 .if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff)
557 movz \reg, :abs_g2_s:\val
558 .else
559 movz \reg, :abs_g3:\val
560 movk \reg, :abs_g2_nc:\val
561 .endif
562 movk \reg, :abs_g1_nc:\val
563 .endif
564 movk \reg, :abs_g0_nc:\val
565 .endm
566
567/*
568 * Return the current task_struct.
569 */
570 .macro get_current_task, rd
571 mrs \rd, sp_el0
572 .endm
573
574/*
575 * If the kernel is built for 52-bit virtual addressing but the hardware only
576 * supports 48 bits, we cannot program the pgdir address into TTBR1 directly,
577 * but we have to add an offset so that the TTBR1 address corresponds with the
578 * pgdir entry that covers the lowest 48-bit addressable VA.
579 *
580 * Note that this trick is only used for LVA/64k pages - LPA2/4k pages uses an
581 * additional paging level, and on LPA2/16k pages, we would end up with a root
582 * level table with only 2 entries, which is suboptimal in terms of TLB
583 * utilization, so there we fall back to 47 bits of translation if LPA2 is not
584 * supported.
585 *
586 * orr is used as it can cover the immediate value (and is idempotent).
587 * ttbr: Value of ttbr to set, modified.
588 */
589 .macro offset_ttbr1, ttbr, tmp
590#if defined(CONFIG_ARM64_VA_BITS_52) && !defined(CONFIG_ARM64_LPA2)
591 mrs \tmp, tcr_el1
592 and \tmp, \tmp, #TCR_EL1_T1SZ_MASK
593 cmp \tmp, #TCR_T1SZ(VA_BITS_MIN)
594 orr \tmp, \ttbr, #TTBR1_BADDR_4852_OFFSET
595 csel \ttbr, \tmp, \ttbr, eq
596#endif
597 .endm
598
599/*
600 * Arrange a physical address in a TTBR register, taking care of 52-bit
601 * addresses.
602 *
603 * phys: physical address, preserved
604 * ttbr: returns the TTBR value
605 */
606 .macro phys_to_ttbr, ttbr, phys
607#ifdef CONFIG_ARM64_PA_BITS_52
608 orr \ttbr, \phys, \phys, lsr #46
609 and \ttbr, \ttbr, #TTBR_BADDR_MASK_52
610#else
611 mov \ttbr, \phys
612#endif
613 .endm
614
615 .macro phys_to_pte, pte, phys
616#ifdef CONFIG_ARM64_PA_BITS_52
617 orr \pte, \phys, \phys, lsr #PTE_ADDR_HIGH_SHIFT
618 and \pte, \pte, #PHYS_TO_PTE_ADDR_MASK
619#else
620 mov \pte, \phys
621#endif
622 .endm
623
624/*
625 * tcr_clear_errata_bits - Clear TCR bits that trigger an errata on this CPU.
626 */
627 .macro tcr_clear_errata_bits, tcr, tmp1, tmp2
628#ifdef CONFIG_FUJITSU_ERRATUM_010001
629 mrs \tmp1, midr_el1
630
631 mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001_MASK
632 and \tmp1, \tmp1, \tmp2
633 mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001
634 cmp \tmp1, \tmp2
635 b.ne 10f
636
637 mov_q \tmp2, TCR_CLEAR_FUJITSU_ERRATUM_010001
638 bic \tcr, \tcr, \tmp2
63910:
640#endif /* CONFIG_FUJITSU_ERRATUM_010001 */
641 .endm
642
643/**
644 * Errata workaround prior to disable MMU. Insert an ISB immediately prior
645 * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.
646 */
647 .macro pre_disable_mmu_workaround
648#ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041
649 isb
650#endif
651 .endm
652
653 /*
654 * frame_push - Push @regcount callee saved registers to the stack,
655 * starting at x19, as well as x29/x30, and set x29 to
656 * the new value of sp. Add @extra bytes of stack space
657 * for locals.
658 */
659 .macro frame_push, regcount:req, extra
660 __frame st, \regcount, \extra
661 .endm
662
663 /*
664 * frame_pop - Pop the callee saved registers from the stack that were
665 * pushed in the most recent call to frame_push, as well
666 * as x29/x30 and any extra stack space that may have been
667 * allocated.
668 */
669 .macro frame_pop
670 __frame ld
671 .endm
672
673 .macro __frame_regs, reg1, reg2, op, num
674 .if .Lframe_regcount == \num
675 \op\()r \reg1, [sp, #(\num + 1) * 8]
676 .elseif .Lframe_regcount > \num
677 \op\()p \reg1, \reg2, [sp, #(\num + 1) * 8]
678 .endif
679 .endm
680
681 .macro __frame, op, regcount, extra=0
682 .ifc \op, st
683 .if (\regcount) < 0 || (\regcount) > 10
684 .error "regcount should be in the range [0 ... 10]"
685 .endif
686 .if ((\extra) % 16) != 0
687 .error "extra should be a multiple of 16 bytes"
688 .endif
689 .ifdef .Lframe_regcount
690 .if .Lframe_regcount != -1
691 .error "frame_push/frame_pop may not be nested"
692 .endif
693 .endif
694 .set .Lframe_regcount, \regcount
695 .set .Lframe_extra, \extra
696 .set .Lframe_local_offset, ((\regcount + 3) / 2) * 16
697 stp x29, x30, [sp, #-.Lframe_local_offset - .Lframe_extra]!
698 mov x29, sp
699 .endif
700
701 __frame_regs x19, x20, \op, 1
702 __frame_regs x21, x22, \op, 3
703 __frame_regs x23, x24, \op, 5
704 __frame_regs x25, x26, \op, 7
705 __frame_regs x27, x28, \op, 9
706
707 .ifc \op, ld
708 .if .Lframe_regcount == -1
709 .error "frame_push/frame_pop may not be nested"
710 .endif
711 ldp x29, x30, [sp], #.Lframe_local_offset + .Lframe_extra
712 .set .Lframe_regcount, -1
713 .endif
714 .endm
715
716/*
717 * Set SCTLR_ELx to the @reg value, and invalidate the local icache
718 * in the process. This is called when setting the MMU on.
719 */
720.macro set_sctlr, sreg, reg
721 msr \sreg, \reg
722 isb
723 /*
724 * Invalidate the local I-cache so that any instructions fetched
725 * speculatively from the PoC are discarded, since they may have
726 * been dynamically patched at the PoU.
727 */
728 ic iallu
729 dsb nsh
730 isb
731.endm
732
733.macro set_sctlr_el1, reg
734 set_sctlr sctlr_el1, \reg
735.endm
736
737.macro set_sctlr_el2, reg
738 set_sctlr sctlr_el2, \reg
739.endm
740
741 /*
742 * Check whether asm code should yield as soon as it is able. This is
743 * the case if we are currently running in task context, and the
744 * TIF_NEED_RESCHED flag is set. (Note that the TIF_NEED_RESCHED flag
745 * is stored negated in the top word of the thread_info::preempt_count
746 * field)
747 */
748 .macro cond_yield, lbl:req, tmp:req, tmp2
749#ifdef CONFIG_PREEMPT_VOLUNTARY
750 get_current_task \tmp
751 ldr \tmp, [\tmp, #TSK_TI_PREEMPT]
752 /*
753 * If we are serving a softirq, there is no point in yielding: the
754 * softirq will not be preempted no matter what we do, so we should
755 * run to completion as quickly as we can. The preempt_count field will
756 * have BIT(SOFTIRQ_SHIFT) set in this case, so the zero check will
757 * catch this case too.
758 */
759 cbz \tmp, \lbl
760#endif
761 .endm
762
763/*
764 * Branch Target Identifier (BTI)
765 */
766 .macro bti, targets
767 .equ .L__bti_targets_c, 34
768 .equ .L__bti_targets_j, 36
769 .equ .L__bti_targets_jc,38
770 hint #.L__bti_targets_\targets
771 .endm
772
773/*
774 * This macro emits a program property note section identifying
775 * architecture features which require special handling, mainly for
776 * use in assembly files included in the VDSO.
777 */
778
779#define NT_GNU_PROPERTY_TYPE_0 5
780#define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000
781
782#define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1U << 0)
783#define GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1U << 1)
784
785#ifdef CONFIG_ARM64_BTI_KERNEL
786#define GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT \
787 ((GNU_PROPERTY_AARCH64_FEATURE_1_BTI | \
788 GNU_PROPERTY_AARCH64_FEATURE_1_PAC))
789#endif
790
791#ifdef GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT
792.macro emit_aarch64_feature_1_and, feat=GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT
793 .pushsection .note.gnu.property, "a"
794 .align 3
795 .long 2f - 1f
796 .long 6f - 3f
797 .long NT_GNU_PROPERTY_TYPE_0
7981: .string "GNU"
7992:
800 .align 3
8013: .long GNU_PROPERTY_AARCH64_FEATURE_1_AND
802 .long 5f - 4f
8034:
804 /*
805 * This is described with an array of char in the Linux API
806 * spec but the text and all other usage (including binutils,
807 * clang and GCC) treat this as a 32 bit value so no swizzling
808 * is required for big endian.
809 */
810 .long \feat
8115:
812 .align 3
8136:
814 .popsection
815.endm
816
817#else
818.macro emit_aarch64_feature_1_and, feat=0
819.endm
820
821#endif /* GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT */
822
823 .macro __mitigate_spectre_bhb_loop tmp
824#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY
825alternative_cb ARM64_ALWAYS_SYSTEM, spectre_bhb_patch_loop_iter
826 mov \tmp, #32 // Patched to correct the immediate
827alternative_cb_end
828.Lspectre_bhb_loop\@:
829 b . + 4
830 subs \tmp, \tmp, #1
831 b.ne .Lspectre_bhb_loop\@
832 sb
833#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */
834 .endm
835
836 .macro mitigate_spectre_bhb_loop tmp
837#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY
838alternative_cb ARM64_ALWAYS_SYSTEM, spectre_bhb_patch_loop_mitigation_enable
839 b .L_spectre_bhb_loop_done\@ // Patched to NOP
840alternative_cb_end
841 __mitigate_spectre_bhb_loop \tmp
842.L_spectre_bhb_loop_done\@:
843#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */
844 .endm
845
846 /* Save/restores x0-x3 to the stack */
847 .macro __mitigate_spectre_bhb_fw
848#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY
849 stp x0, x1, [sp, #-16]!
850 stp x2, x3, [sp, #-16]!
851 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_3
852alternative_cb ARM64_ALWAYS_SYSTEM, smccc_patch_fw_mitigation_conduit
853 nop // Patched to SMC/HVC #0
854alternative_cb_end
855 ldp x2, x3, [sp], #16
856 ldp x0, x1, [sp], #16
857#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */
858 .endm
859
860 .macro mitigate_spectre_bhb_clear_insn
861#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY
862alternative_cb ARM64_ALWAYS_SYSTEM, spectre_bhb_patch_clearbhb
863 /* Patched to NOP when not supported */
864 clearbhb
865 isb
866alternative_cb_end
867#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */
868 .endm
869#endif /* __ASM_ASSEMBLER_H */