tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2023, Intel Corporation
4 */
5
6/dts-v1/;
7#include <dt-bindings/reset/altr,rst-mgr-s10.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/clock/intel,agilex5-clkmgr.h>
12
13/ {
14 compatible = "intel,socfpga-agilex5";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 reserved-memory {
19 #address-cells = <2>;
20 #size-cells = <2>;
21 ranges;
22
23 service_reserved: svcbuffer@0 {
24 compatible = "shared-dma-pool";
25 reg = <0x0 0x80000000 0x0 0x2000000>;
26 alignment = <0x1000>;
27 no-map;
28 };
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu0: cpu@0 {
36 compatible = "arm,cortex-a55";
37 reg = <0x0>;
38 device_type = "cpu";
39 enable-method = "psci";
40 next-level-cache = <&L2>;
41 };
42
43 cpu1: cpu@1 {
44 compatible = "arm,cortex-a55";
45 reg = <0x100>;
46 device_type = "cpu";
47 enable-method = "psci";
48 next-level-cache = <&L2>;
49 };
50
51 cpu2: cpu@2 {
52 compatible = "arm,cortex-a76";
53 reg = <0x200>;
54 device_type = "cpu";
55 enable-method = "psci";
56 next-level-cache = <&L2>;
57 };
58
59 cpu3: cpu@3 {
60 compatible = "arm,cortex-a76";
61 reg = <0x300>;
62 device_type = "cpu";
63 enable-method = "psci";
64 next-level-cache = <&L2>;
65 };
66
67 L2: l2-cache {
68 compatible = "cache";
69 cache-level = <2>;
70 next-level-cache = <&L3>;
71 cache-unified;
72 };
73
74 L3: l3-cache {
75 compatible = "cache";
76 cache-level = <3>;
77 cache-unified;
78 };
79
80 };
81
82 firmware {
83 svc {
84 compatible = "intel,agilex5-svc";
85 method = "smc";
86 memory-region = <&service_reserved>;
87 iommus = <&smmu 10>;
88 };
89 };
90
91 psci {
92 compatible = "arm,psci-0.2";
93 method = "smc";
94 };
95
96 intc: interrupt-controller@1d000000 {
97 compatible = "arm,gic-v3";
98 reg = <0x0 0x1d000000 0 0x10000>,
99 <0x0 0x1d060000 0 0x100000>;
100 ranges;
101 #interrupt-cells = <3>;
102 #address-cells = <2>;
103 #size-cells = <2>;
104 interrupt-controller;
105 interrupt-parent = <&intc>;
106 #redistributor-regions = <1>;
107 redistributor-stride = <0x0 0x20000>;
108 /* VGIC maintenance interrupt */
109 interrupts = <GIC_PPI 25 IRQ_TYPE_LEVEL_HIGH>;
110
111 its: msi-controller@1d040000 {
112 compatible = "arm,gic-v3-its";
113 reg = <0x0 0x1d040000 0x0 0x20000>;
114 msi-controller;
115 #msi-cells = <1>;
116 };
117 };
118
119 /* Clock tree 5 main sources*/
120 clocks {
121 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
122 #clock-cells = <0>;
123 compatible = "fixed-clock";
124 clock-frequency = <0>;
125 };
126
127 cb_intosc_ls_clk: cb-intosc-ls-clk {
128 #clock-cells = <0>;
129 compatible = "fixed-clock";
130 clock-frequency = <0>;
131 };
132
133 f2s_free_clk: f2s-free-clk {
134 #clock-cells = <0>;
135 compatible = "fixed-clock";
136 clock-frequency = <0>;
137 };
138
139 osc1: osc1 {
140 #clock-cells = <0>;
141 compatible = "fixed-clock";
142 clock-frequency = <0>;
143 };
144
145 qspi_clk: qspi-clk {
146 #clock-cells = <0>;
147 compatible = "fixed-clock";
148 clock-frequency = <200000000>;
149 };
150 };
151
152 timer {
153 compatible = "arm,armv8-timer";
154 interrupt-parent = <&intc>;
155 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
156 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
157 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
158 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
159 };
160
161 usbphy0: usbphy {
162 #phy-cells = <0>;
163 compatible = "usb-nop-xceiv";
164 };
165
166 pmu0: pmu {
167 compatible = "arm,armv8-pmuv3";
168 interrupt-parent = <&intc>;
169 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
170 };
171
172 soc: soc@0 {
173 compatible = "simple-bus";
174 ranges = <0 0 0 0xffffffff>;
175 #address-cells = <1>;
176 #size-cells = <1>;
177 device_type = "soc";
178 interrupt-parent = <&intc>;
179
180 clkmgr: clock-controller@10d10000 {
181 compatible = "intel,agilex5-clkmgr";
182 reg = <0x10d10000 0x1000>;
183 #clock-cells = <1>;
184 };
185
186 i2c0: i2c@10c02800 {
187 compatible = "snps,designware-i2c";
188 reg = <0x10c02800 0x100>;
189 #address-cells = <1>;
190 #size-cells = <0>;
191 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
192 resets = <&rst I2C0_RESET>;
193 clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
194 status = "disabled";
195 };
196
197 i2c1: i2c@10c02900 {
198 compatible = "snps,designware-i2c";
199 reg = <0x10c02900 0x100>;
200 #address-cells = <1>;
201 #size-cells = <0>;
202 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
203 resets = <&rst I2C1_RESET>;
204 clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
205 status = "disabled";
206 };
207
208 i2c2: i2c@10c02a00 {
209 compatible = "snps,designware-i2c";
210 reg = <0x10c02a00 0x100>;
211 #address-cells = <1>;
212 #size-cells = <0>;
213 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
214 resets = <&rst I2C2_RESET>;
215 clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
216 status = "disabled";
217 };
218
219 i2c3: i2c@10c02b00 {
220 compatible = "snps,designware-i2c";
221 reg = <0x10c02b00 0x100>;
222 #address-cells = <1>;
223 #size-cells = <0>;
224 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
225 resets = <&rst I2C3_RESET>;
226 clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
227 status = "disabled";
228 };
229
230 i2c4: i2c@10c02c00 {
231 compatible = "snps,designware-i2c";
232 reg = <0x10c02c00 0x100>;
233 #address-cells = <1>;
234 #size-cells = <0>;
235 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
236 resets = <&rst I2C4_RESET>;
237 clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
238 status = "disabled";
239 };
240
241 i3c0: i3c@10da0000 {
242 compatible = "altr,agilex5-dw-i3c-master",
243 "snps,dw-i3c-master-1.00a";
244 reg = <0x10da0000 0x1000>;
245 #address-cells = <3>;
246 #size-cells = <0>;
247 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
249 status = "disabled";
250 };
251
252 i3c1: i3c@10da1000 {
253 compatible = "altr,agilex5-dw-i3c-master",
254 "snps,dw-i3c-master-1.00a";
255 reg = <0x10da1000 0x1000>;
256 #address-cells = <3>;
257 #size-cells = <0>;
258 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
260 status = "disabled";
261 };
262
263 gpio0: gpio@10c03200 {
264 compatible = "snps,dw-apb-gpio";
265 reg = <0x10c03200 0x100>;
266 #address-cells = <1>;
267 #size-cells = <0>;
268 resets = <&rst GPIO0_RESET>;
269 status = "disabled";
270
271 porta: gpio-controller@0 {
272 compatible = "snps,dw-apb-gpio-port";
273 reg = <0>;
274 gpio-controller;
275 #gpio-cells = <2>;
276 snps,nr-gpios = <24>;
277 interrupt-controller;
278 #interrupt-cells = <2>;
279 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
280 };
281 };
282
283 gpio1: gpio@10c03300 {
284 compatible = "snps,dw-apb-gpio";
285 reg = <0x10c03300 0x100>;
286 #address-cells = <1>;
287 #size-cells = <0>;
288 resets = <&rst GPIO1_RESET>;
289 status = "disabled";
290
291 portb: gpio-controller@0 {
292 compatible = "snps,dw-apb-gpio-port";
293 reg = <0>;
294 gpio-controller;
295 #gpio-cells = <2>;
296 snps,nr-gpios = <24>;
297 interrupt-controller;
298 #interrupt-cells = <2>;
299 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
300 };
301 };
302
303 nand: nand-controller@10b80000 {
304 compatible = "cdns,hp-nfc";
305 reg = <0x10b80000 0x10000>,
306 <0x10840000 0x10000>;
307 reg-names = "reg", "sdma";
308 #address-cells = <1>;
309 #size-cells = <0>;
310 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&clkmgr AGILEX5_NAND_NF_CLK>;
312 clock-names = "nf_clk";
313 cdns,board-delay-ps = <4830>;
314 iommus = <&smmu 4>;
315 dma-coherent;
316 status = "disabled";
317 };
318
319 ocram: sram@0 {
320 compatible = "mmio-sram";
321 reg = <0x00000000 0x80000>;
322 ranges = <0 0 0x80000>;
323 #address-cells = <1>;
324 #size-cells = <1>;
325 };
326
327 dma: dma-bus@10db0000 {
328 compatible = "simple-bus";
329 #address-cells = <1>;
330 #size-cells = <2>;
331 ranges = <0x00 0x10db0000 0x00 0x20000>;
332 dma-ranges = <0x00 0x00 0x100 0x00>;
333
334 dmac0: dma-controller@0 {
335 compatible = "altr,agilex5-axi-dma",
336 "snps,axi-dma-1.01a";
337 reg = <0x0 0x0 0x500>;
338 clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
339 <&clkmgr AGILEX5_L4_MP_CLK>;
340 clock-names = "core-clk", "cfgr-clk";
341 interrupt-parent = <&intc>;
342 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
343 #dma-cells = <1>;
344 dma-channels = <4>;
345 snps,dma-masters = <1>;
346 snps,data-width = <2>;
347 snps,block-size = <32767 32767 32767 32767>;
348 snps,priority = <0 1 2 3>;
349 snps,axi-max-burst-len = <8>;
350 iommus = <&smmu 8>;
351 };
352
353 dmac1: dma-controller@10000 {
354 compatible = "altr,agilex5-axi-dma",
355 "snps,axi-dma-1.01a";
356 reg = <0x10000 0x0 0x500>;
357 clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
358 <&clkmgr AGILEX5_L4_MP_CLK>;
359 clock-names = "core-clk", "cfgr-clk";
360 interrupt-parent = <&intc>;
361 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
362 #dma-cells = <1>;
363 dma-channels = <4>;
364 snps,dma-masters = <1>;
365 snps,data-width = <2>;
366 snps,block-size = <32767 32767 32767 32767>;
367 snps,priority = <0 1 2 3>;
368 snps,axi-max-burst-len = <8>;
369 iommus = <&smmu 9>;
370 };
371 };
372
373 rst: rstmgr@10d11000 {
374 compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr";
375 reg = <0x10d11000 0x1000>;
376 #reset-cells = <1>;
377 };
378
379 smmu: iommu@16000000 {
380 compatible = "arm,smmu-v3";
381 reg = <0x16000000 0x30000>;
382 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
383 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
384 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>;
385 interrupt-names = "eventq", "gerror", "priq";
386 dma-coherent;
387 #iommu-cells = <1>;
388 status = "disabled";
389 };
390
391 spi0: spi@10da4000 {
392 compatible = "snps,dw-apb-ssi";
393 reg = <0x10da4000 0x1000>;
394 #address-cells = <1>;
395 #size-cells = <0>;
396 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
397 resets = <&rst SPIM0_RESET>;
398 reset-names = "spi";
399 reg-io-width = <4>;
400 num-cs = <4>;
401 clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
402 dmas = <&dmac0 16>, <&dmac0 17>;
403 dma-names = "tx", "rx";
404 status = "disabled";
405
406 };
407
408 spi1: spi@10da5000 {
409 compatible = "snps,dw-apb-ssi";
410 reg = <0x10da5000 0x1000>;
411 #address-cells = <1>;
412 #size-cells = <0>;
413 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
414 resets = <&rst SPIM1_RESET>;
415 reset-names = "spi";
416 reg-io-width = <4>;
417 num-cs = <4>;
418 clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
419 dmas = <&dmac0 20>, <&dmac0 21>;
420 dma-names = "tx", "rx";
421 status = "disabled";
422 };
423
424 sysmgr: sysmgr@10d12000 {
425 compatible = "altr,sys-mgr-s10","altr,sys-mgr";
426 reg = <0x10d12000 0x500>;
427 };
428
429 timer0: timer0@10c03000 {
430 compatible = "snps,dw-apb-timer";
431 reg = <0x10c03000 0x100>;
432 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
434 clock-names = "timer";
435 };
436
437 timer1: timer1@10c03100 {
438 compatible = "snps,dw-apb-timer";
439 reg = <0x10c03100 0x100>;
440 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
442 clock-names = "timer";
443 };
444
445 timer2: timer2@10d00000 {
446 compatible = "snps,dw-apb-timer";
447 reg = <0x10d00000 0x100>;
448 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
450 clock-names = "timer";
451 };
452
453 timer3: timer3@10d00100 {
454 compatible = "snps,dw-apb-timer";
455 reg = <0x10d00100 0x100>;
456 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
458 clock-names = "timer";
459 };
460
461 uart0: serial@10c02000 {
462 compatible = "snps,dw-apb-uart";
463 reg = <0x10c02000 0x100>;
464 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
465 reg-shift = <2>;
466 reg-io-width = <4>;
467 resets = <&rst UART0_RESET>;
468 status = "disabled";
469 clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
470 };
471
472 uart1: serial@10c02100 {
473 compatible = "snps,dw-apb-uart";
474 reg = <0x10c02100 0x100>;
475 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
476 reg-shift = <2>;
477 reg-io-width = <4>;
478 resets = <&rst UART1_RESET>;
479 status = "disabled";
480 clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
481 };
482
483 usb0: usb@10b00000 {
484 compatible = "snps,dwc2";
485 reg = <0x10b00000 0x40000>;
486 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
487 phys = <&usbphy0>;
488 phy-names = "usb2-phy";
489 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
490 reset-names = "dwc2", "dwc2-ecc";
491 iommus = <&smmu 6>;
492 clocks = <&clkmgr AGILEX5_USB2OTG_HCLK>;
493 clock-names = "otg";
494 status = "disabled";
495 };
496
497 watchdog0: watchdog@10d00200 {
498 compatible = "snps,dw-wdt";
499 reg = <0x10d00200 0x100>;
500 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
501 resets = <&rst WATCHDOG0_RESET>;
502 clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
503 status = "disabled";
504 };
505
506 watchdog1: watchdog@10d00300 {
507 compatible = "snps,dw-wdt";
508 reg = <0x10d00300 0x100>;
509 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
510 resets = <&rst WATCHDOG1_RESET>;
511 clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
512 status = "disabled";
513 };
514
515 watchdog2: watchdog@10d00400 {
516 compatible = "snps,dw-wdt";
517 reg = <0x10d00400 0x100>;
518 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
519 resets = <&rst WATCHDOG2_RESET>;
520 clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
521 status = "disabled";
522 };
523
524 watchdog3: watchdog@10d00500 {
525 compatible = "snps,dw-wdt";
526 reg = <0x10d00500 0x100>;
527 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
528 resets = <&rst WATCHDOG3_RESET>;
529 clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
530 status = "disabled";
531 };
532
533 watchdog4: watchdog@10d00600 {
534 compatible = "snps,dw-wdt";
535 reg = <0x10d00600 0x100>;
536 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
537 resets = <&rst WATCHDOG4_RESET>;
538 clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
539 status = "disabled";
540 };
541
542 qspi: spi@108d2000 {
543 compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
544 reg = <0x108d2000 0x100>,
545 <0x10900000 0x100000>;
546 #address-cells = <1>;
547 #size-cells = <0>;
548 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
549 cdns,fifo-depth = <128>;
550 cdns,fifo-width = <4>;
551 cdns,trigger-address = <0x00000000>;
552 clocks = <&qspi_clk>;
553 status = "disabled";
554 };
555
556 gmac0: ethernet@10810000 {
557 compatible = "altr,socfpga-stmmac-agilex5",
558 "snps,dwxgmac-2.10";
559 reg = <0x10810000 0x3500>;
560 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
561 interrupt-names = "macirq";
562 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
563 reset-names = "stmmaceth", "ahb";
564 clocks = <&clkmgr AGILEX5_EMAC0_CLK>,
565 <&clkmgr AGILEX5_EMAC_PTP_CLK>;
566 clock-names = "stmmaceth", "ptp_ref";
567 mac-address = [00 00 00 00 00 00];
568 tx-fifo-depth = <32768>;
569 rx-fifo-depth = <16384>;
570 snps,multicast-filter-bins = <64>;
571 snps,perfect-filter-entries = <64>;
572 snps,axi-config = <&stmmac_axi_emac0_setup>;
573 snps,mtl-rx-config = <&mtl_rx_emac0_setup>;
574 snps,mtl-tx-config = <&mtl_tx_emac0_setup>;
575 snps,pbl = <32>;
576 snps,tso;
577 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
578 snps,clk-csr = <0>;
579 iommus = <&smmu 1>;
580 status = "disabled";
581
582 stmmac_axi_emac0_setup: stmmac-axi-config {
583 snps,wr_osr_lmt = <31>;
584 snps,rd_osr_lmt = <31>;
585 snps,blen = <0 0 0 32 16 8 4>;
586 };
587
588 mtl_rx_emac0_setup: rx-queues-config {
589 snps,rx-queues-to-use = <8>;
590 snps,rx-sched-sp;
591 queue0 {
592 snps,dcb-algorithm;
593 snps,map-to-dma-channel = <0x0>;
594 };
595 queue1 {
596 snps,dcb-algorithm;
597 snps,map-to-dma-channel = <0x1>;
598 };
599 queue2 {
600 snps,dcb-algorithm;
601 snps,map-to-dma-channel = <0x2>;
602 };
603 queue3 {
604 snps,dcb-algorithm;
605 snps,map-to-dma-channel = <0x3>;
606 };
607 queue4 {
608 snps,dcb-algorithm;
609 snps,map-to-dma-channel = <0x4>;
610 };
611 queue5 {
612 snps,dcb-algorithm;
613 snps,map-to-dma-channel = <0x5>;
614 };
615 queue6 {
616 snps,dcb-algorithm;
617 snps,map-to-dma-channel = <0x6>;
618 };
619 queue7 {
620 snps,dcb-algorithm;
621 snps,map-to-dma-channel = <0x7>;
622 };
623 };
624
625 mtl_tx_emac0_setup: tx-queues-config {
626 snps,tx-queues-to-use = <8>;
627 snps,tx-sched-wrr;
628 queue0 {
629 snps,weight = <0x09>;
630 snps,dcb-algorithm;
631 };
632 queue1 {
633 snps,weight = <0x0a>;
634 snps,dcb-algorithm;
635 };
636 queue2 {
637 snps,weight = <0x0b>;
638 snps,coe-unsupported;
639 snps,dcb-algorithm;
640 };
641 queue3 {
642 snps,weight = <0x0c>;
643 snps,coe-unsupported;
644 snps,dcb-algorithm;
645 };
646 queue4 {
647 snps,weight = <0x0d>;
648 snps,coe-unsupported;
649 snps,dcb-algorithm;
650 };
651 queue5 {
652 snps,weight = <0x0e>;
653 snps,coe-unsupported;
654 snps,dcb-algorithm;
655 };
656 queue6 {
657 snps,weight = <0x0f>;
658 snps,coe-unsupported;
659 snps,dcb-algorithm;
660 };
661 queue7 {
662 snps,weight = <0x10>;
663 snps,coe-unsupported;
664 snps,dcb-algorithm;
665 };
666 };
667 };
668
669 gmac1: ethernet@10820000 {
670 compatible = "altr,socfpga-stmmac-agilex5",
671 "snps,dwxgmac-2.10";
672 reg = <0x10820000 0x3500>;
673 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
674 interrupt-names = "macirq";
675 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
676 reset-names = "stmmaceth", "ahb";
677 clocks = <&clkmgr AGILEX5_EMAC1_CLK>,
678 <&clkmgr AGILEX5_EMAC_PTP_CLK>;
679 clock-names = "stmmaceth", "ptp_ref";
680 mac-address = [00 00 00 00 00 00];
681 tx-fifo-depth = <32768>;
682 rx-fifo-depth = <16384>;
683 snps,multicast-filter-bins = <64>;
684 snps,perfect-filter-entries = <64>;
685 snps,axi-config = <&stmmac_axi_emac1_setup>;
686 snps,mtl-rx-config = <&mtl_rx_emac1_setup>;
687 snps,mtl-tx-config = <&mtl_tx_emac1_setup>;
688 snps,pbl = <32>;
689 snps,tso;
690 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
691 snps,clk-csr = <0>;
692 iommus = <&smmu 2>;
693 status = "disabled";
694
695 stmmac_axi_emac1_setup: stmmac-axi-config {
696 snps,wr_osr_lmt = <31>;
697 snps,rd_osr_lmt = <31>;
698 snps,blen = <0 0 0 32 16 8 4>;
699 };
700
701 mtl_rx_emac1_setup: rx-queues-config {
702 snps,rx-queues-to-use = <8>;
703 snps,rx-sched-sp;
704 queue0 {
705 snps,dcb-algorithm;
706 snps,map-to-dma-channel = <0x0>;
707 };
708 queue1 {
709 snps,dcb-algorithm;
710 snps,map-to-dma-channel = <0x1>;
711 };
712 queue2 {
713 snps,dcb-algorithm;
714 snps,map-to-dma-channel = <0x2>;
715 };
716 queue3 {
717 snps,dcb-algorithm;
718 snps,map-to-dma-channel = <0x3>;
719 };
720 queue4 {
721 snps,dcb-algorithm;
722 snps,map-to-dma-channel = <0x4>;
723 };
724 queue5 {
725 snps,dcb-algorithm;
726 snps,map-to-dma-channel = <0x5>;
727 };
728 queue6 {
729 snps,dcb-algorithm;
730 snps,map-to-dma-channel = <0x6>;
731 };
732 queue7 {
733 snps,dcb-algorithm;
734 snps,map-to-dma-channel = <0x7>;
735 };
736 };
737
738 mtl_tx_emac1_setup: tx-queues-config {
739 snps,tx-queues-to-use = <8>;
740 snps,tx-sched-wrr;
741 queue0 {
742 snps,weight = <0x09>;
743 snps,dcb-algorithm;
744 };
745 queue1 {
746 snps,weight = <0x0a>;
747 snps,dcb-algorithm;
748 };
749 queue2 {
750 snps,weight = <0x0b>;
751 snps,coe-unsupported;
752 snps,dcb-algorithm;
753 };
754 queue3 {
755 snps,weight = <0x0c>;
756 snps,coe-unsupported;
757 snps,dcb-algorithm;
758 };
759 queue4 {
760 snps,weight = <0x0d>;
761 snps,coe-unsupported;
762 snps,dcb-algorithm;
763 };
764 queue5 {
765 snps,weight = <0x0e>;
766 snps,coe-unsupported;
767 snps,dcb-algorithm;
768 };
769 queue6 {
770 snps,weight = <0x0f>;
771 snps,coe-unsupported;
772 snps,dcb-algorithm;
773 };
774 queue7 {
775 snps,weight = <0x10>;
776 snps,coe-unsupported;
777 snps,dcb-algorithm;
778 };
779 };
780 };
781
782 gmac2: ethernet@10830000 {
783 compatible = "altr,socfpga-stmmac-agilex5",
784 "snps,dwxgmac-2.10";
785 reg = <0x10830000 0x3500>;
786 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
787 interrupt-names = "macirq";
788 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
789 reset-names = "stmmaceth", "ahb";
790 clocks = <&clkmgr AGILEX5_EMAC2_CLK>,
791 <&clkmgr AGILEX5_EMAC_PTP_CLK>;
792 clock-names = "stmmaceth", "ptp_ref";
793 mac-address = [00 00 00 00 00 00];
794 tx-fifo-depth = <32768>;
795 rx-fifo-depth = <16384>;
796 snps,multicast-filter-bins = <64>;
797 snps,perfect-filter-entries = <64>;
798 snps,axi-config = <&stmmac_axi_emac2_setup>;
799 snps,mtl-rx-config = <&mtl_rx_emac2_setup>;
800 snps,mtl-tx-config = <&mtl_tx_emac2_setup>;
801 snps,pbl = <32>;
802 snps,tso;
803 altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
804 snps,clk-csr = <0>;
805 iommus = <&smmu 3>;
806 status = "disabled";
807
808 stmmac_axi_emac2_setup: stmmac-axi-config {
809 snps,wr_osr_lmt = <31>;
810 snps,rd_osr_lmt = <31>;
811 snps,blen = <0 0 0 32 16 8 4>;
812 };
813
814 mtl_rx_emac2_setup: rx-queues-config {
815 snps,rx-queues-to-use = <8>;
816 snps,rx-sched-sp;
817 queue0 {
818 snps,dcb-algorithm;
819 snps,map-to-dma-channel = <0x0>;
820 };
821 queue1 {
822 snps,dcb-algorithm;
823 snps,map-to-dma-channel = <0x1>;
824 };
825 queue2 {
826 snps,dcb-algorithm;
827 snps,map-to-dma-channel = <0x2>;
828 };
829 queue3 {
830 snps,dcb-algorithm;
831 snps,map-to-dma-channel = <0x3>;
832 };
833 queue4 {
834 snps,dcb-algorithm;
835 snps,map-to-dma-channel = <0x4>;
836 };
837 queue5 {
838 snps,dcb-algorithm;
839 snps,map-to-dma-channel = <0x5>;
840 };
841 queue6 {
842 snps,dcb-algorithm;
843 snps,map-to-dma-channel = <0x6>;
844 };
845 queue7 {
846 snps,dcb-algorithm;
847 snps,map-to-dma-channel = <0x7>;
848 };
849 };
850
851 mtl_tx_emac2_setup: tx-queues-config {
852 snps,tx-queues-to-use = <8>;
853 snps,tx-sched-wrr;
854 queue0 {
855 snps,weight = <0x09>;
856 snps,dcb-algorithm;
857 };
858 queue1 {
859 snps,weight = <0x0a>;
860 snps,dcb-algorithm;
861 };
862 queue2 {
863 snps,weight = <0x0b>;
864 snps,coe-unsupported;
865 snps,dcb-algorithm;
866 };
867 queue3 {
868 snps,weight = <0x0c>;
869 snps,coe-unsupported;
870 snps,dcb-algorithm;
871 };
872 queue4 {
873 snps,weight = <0x0d>;
874 snps,coe-unsupported;
875 snps,dcb-algorithm;
876 };
877 queue5 {
878 snps,weight = <0x0e>;
879 snps,coe-unsupported;
880 snps,dcb-algorithm;
881 };
882 queue6 {
883 snps,weight = <0x0f>;
884 snps,coe-unsupported;
885 snps,dcb-algorithm;
886 };
887 queue7 {
888 snps,weight = <0x10>;
889 snps,coe-unsupported;
890 snps,dcb-algorithm;
891 };
892 };
893 };
894
895 pmu0_tcu: pmu@16002000 {
896 compatible = "arm,smmu-v3-pmcg";
897 reg = <0x16002000 0x1000>,
898 <0x16022000 0x1000>;
899 interrupt-parent = <&intc>;
900 interrupts = <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>;
901 };
902
903 pmu0_tbu0: pmu@16042000 {
904 compatible = "arm,smmu-v3-pmcg";
905 reg = <0x16042000 0x1000>,
906 <0x16052000 0x1000>;
907 interrupt-parent = <&intc>;
908 interrupts = <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>;
909 };
910
911 pmu0_tbu1: pmu@16062000 {
912 compatible = "arm,smmu-v3-pmcg";
913 reg = <0x16062000 0x1000>,
914 <0x16072000 0x1000>;
915 interrupt-parent = <&intc>;
916 interrupts = <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
917 };
918
919 pmu0_tbu2: pmu@16082000 {
920 compatible = "arm,smmu-v3-pmcg";
921 reg = <0x16082000 0x1000>,
922 <0x16092000 0x1000>;
923 interrupt-parent = <&intc>;
924 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
925 };
926
927 pmu0_tbu3: pmu@160a2000 {
928 compatible = "arm,smmu-v3-pmcg";
929 reg = <0x160a2000 0x1000>,
930 <0x160b2000 0x1000>;
931 interrupt-parent = <&intc>;
932 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
933 };
934
935 pmu0_tbu4: pmu@160c2000 {
936 compatible = "arm,smmu-v3-pmcg";
937 reg = <0x160c2000 0x1000>,
938 <0x160d2000 0x1000>;
939 interrupt-parent = <&intc>;
940 interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
941 };
942
943 pmu0_tbu5: pmu@160e2000 {
944 compatible = "arm,smmu-v3-pmcg";
945 reg = <0x160e2000 0x1000>,
946 <0x160f2000 0x1000>;
947 interrupt-parent = <&intc>;
948 interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
949 };
950 };
951};