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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * arch/arm/include/asm/pgtable.h
4 *
5 * Copyright (C) 1995-2002 Russell King
6 */
7#ifndef _ASMARM_PGTABLE_H
8#define _ASMARM_PGTABLE_H
9
10#include <linux/const.h>
11#include <asm/proc-fns.h>
12
13#ifndef __ASSEMBLY__
14/*
15 * ZERO_PAGE is a global shared page that is always zero: used
16 * for zero-mapped memory areas etc..
17 */
18extern struct page *empty_zero_page;
19#define ZERO_PAGE(vaddr) (empty_zero_page)
20#endif
21
22#include <asm-generic/pgtable-nopud.h>
23
24#ifndef CONFIG_MMU
25#include <asm/pgtable-nommu.h>
26
27#else
28
29#include <asm/page.h>
30#include <asm/pgtable-hwdef.h>
31
32
33#include <asm/tlbflush.h>
34
35#ifdef CONFIG_ARM_LPAE
36#include <asm/pgtable-3level.h>
37#else
38#include <asm/pgtable-2level.h>
39#endif
40
41/*
42 * Just any arbitrary offset to the start of the vmalloc VM area: the
43 * current 8MB value just means that there will be a 8MB "hole" after the
44 * physical memory until the kernel virtual memory starts. That means that
45 * any out-of-bounds memory accesses will hopefully be caught.
46 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
47 * area for the same reason. ;)
48 */
49#define VMALLOC_OFFSET (8*1024*1024)
50#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
51#define VMALLOC_END 0xff800000UL
52
53#define LIBRARY_TEXT_START 0x0c000000
54
55#ifndef __ASSEMBLY__
56extern void __pte_error(const char *file, int line, pte_t);
57extern void __pmd_error(const char *file, int line, pmd_t);
58extern void __pgd_error(const char *file, int line, pgd_t);
59
60#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte)
61#define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd)
62#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd)
63
64/*
65 * This is the lowest virtual address we can permit any user space
66 * mapping to be mapped at. This is particularly important for
67 * non-high vector CPUs.
68 */
69#define FIRST_USER_ADDRESS (PAGE_SIZE * 2)
70
71/*
72 * Use TASK_SIZE as the ceiling argument for free_pgtables() and
73 * free_pgd_range() to avoid freeing the modules pmd when LPAE is enabled (pmd
74 * page shared between user and kernel).
75 */
76#ifdef CONFIG_ARM_LPAE
77#define USER_PGTABLES_CEILING TASK_SIZE
78#endif
79
80/*
81 * The pgprot_* and protection_map entries will be fixed up in runtime
82 * to include the cachable and bufferable bits based on memory policy,
83 * as well as any architecture dependent bits like global/ASID and SMP
84 * shared mapping bits.
85 */
86#define _L_PTE_DEFAULT L_PTE_PRESENT | L_PTE_YOUNG
87
88extern pgprot_t pgprot_user;
89extern pgprot_t pgprot_kernel;
90
91#define _MOD_PROT(p, b) __pgprot(pgprot_val(p) | (b))
92
93#define PAGE_NONE _MOD_PROT(pgprot_user, L_PTE_XN | L_PTE_RDONLY | L_PTE_NONE)
94#define PAGE_SHARED _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_XN)
95#define PAGE_SHARED_EXEC _MOD_PROT(pgprot_user, L_PTE_USER)
96#define PAGE_COPY _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
97#define PAGE_COPY_EXEC _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
98#define PAGE_READONLY _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
99#define PAGE_READONLY_EXEC _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
100#define PAGE_KERNEL _MOD_PROT(pgprot_kernel, L_PTE_XN)
101#define PAGE_KERNEL_EXEC pgprot_kernel
102
103#define __PAGE_NONE __pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN | L_PTE_NONE)
104#define __PAGE_SHARED __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN)
105#define __PAGE_SHARED_EXEC __pgprot(_L_PTE_DEFAULT | L_PTE_USER)
106#define __PAGE_COPY __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
107#define __PAGE_COPY_EXEC __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY)
108#define __PAGE_READONLY __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
109#define __PAGE_READONLY_EXEC __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY)
110
111#define __pgprot_modify(prot,mask,bits) \
112 __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
113
114#define pgprot_noncached(prot) \
115 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
116
117#define pgprot_writecombine(prot) \
118 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)
119
120#define pgprot_stronglyordered(prot) \
121 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
122
123#define pgprot_device(prot) \
124 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_SHARED | L_PTE_SHARED | L_PTE_DIRTY | L_PTE_XN)
125
126#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
127#define pgprot_dmacoherent(prot) \
128 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE | L_PTE_XN)
129#define __HAVE_PHYS_MEM_ACCESS_PROT
130struct file;
131extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
132 unsigned long size, pgprot_t vma_prot);
133#else
134#define pgprot_dmacoherent(prot) \
135 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED | L_PTE_XN)
136#endif
137
138#endif /* __ASSEMBLY__ */
139
140/*
141 * The table below defines the page protection levels that we insert into our
142 * Linux page table version. These get translated into the best that the
143 * architecture can perform. Note that on most ARM hardware:
144 * 1) We cannot do execute protection
145 * 2) If we could do execute protection, then read is implied
146 * 3) write implies read permissions
147 */
148
149#ifndef __ASSEMBLY__
150
151extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
152
153#define pgdp_get(pgpd) READ_ONCE(*pgdp)
154
155#define pud_page(pud) pmd_page(__pmd(pud_val(pud)))
156#define pud_write(pud) pmd_write(__pmd(pud_val(pud)))
157
158#define pmd_none(pmd) (!pmd_val(pmd))
159
160static inline pte_t *pmd_page_vaddr(pmd_t pmd)
161{
162 return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK);
163}
164
165#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
166
167#define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT)
168#define pfn_pte(pfn,prot) __pte(__pfn_to_phys(pfn) | pgprot_val(prot))
169
170#define pte_page(pte) pfn_to_page(pte_pfn(pte))
171
172#define pte_clear(mm,addr,ptep) set_pte_ext(ptep, __pte(0), 0)
173
174#define pte_isset(pte, val) ((u32)(val) == (val) ? pte_val(pte) & (val) \
175 : !!(pte_val(pte) & (val)))
176#define pte_isclear(pte, val) (!(pte_val(pte) & (val)))
177
178#define pte_none(pte) (!pte_val(pte))
179#define pte_present(pte) (pte_isset((pte), L_PTE_PRESENT))
180#define pte_valid(pte) (pte_isset((pte), L_PTE_VALID))
181#define pte_accessible(mm, pte) (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte))
182#define pte_write(pte) (pte_isclear((pte), L_PTE_RDONLY))
183#define pte_dirty(pte) (pte_isset((pte), L_PTE_DIRTY))
184#define pte_young(pte) (pte_isset((pte), L_PTE_YOUNG))
185#define pte_exec(pte) (pte_isclear((pte), L_PTE_XN))
186
187#define pte_valid_user(pte) \
188 (pte_valid(pte) && pte_isset((pte), L_PTE_USER) && pte_young(pte))
189
190static inline bool pte_access_permitted(pte_t pte, bool write)
191{
192 pteval_t mask = L_PTE_PRESENT | L_PTE_USER;
193 pteval_t needed = mask;
194
195 if (write)
196 mask |= L_PTE_RDONLY;
197
198 return (pte_val(pte) & mask) == needed;
199}
200#define pte_access_permitted pte_access_permitted
201
202#if __LINUX_ARM_ARCH__ < 6
203static inline void __sync_icache_dcache(pte_t pteval)
204{
205}
206#else
207extern void __sync_icache_dcache(pte_t pteval);
208#endif
209
210#define PFN_PTE_SHIFT PAGE_SHIFT
211
212void set_ptes(struct mm_struct *mm, unsigned long addr,
213 pte_t *ptep, pte_t pteval, unsigned int nr);
214#define set_ptes set_ptes
215
216static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
217{
218 pte_val(pte) &= ~pgprot_val(prot);
219 return pte;
220}
221
222static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
223{
224 pte_val(pte) |= pgprot_val(prot);
225 return pte;
226}
227
228static inline pte_t pte_wrprotect(pte_t pte)
229{
230 return set_pte_bit(pte, __pgprot(L_PTE_RDONLY));
231}
232
233static inline pte_t pte_mkwrite_novma(pte_t pte)
234{
235 return clear_pte_bit(pte, __pgprot(L_PTE_RDONLY));
236}
237
238static inline pte_t pte_mkclean(pte_t pte)
239{
240 return clear_pte_bit(pte, __pgprot(L_PTE_DIRTY));
241}
242
243static inline pte_t pte_mkdirty(pte_t pte)
244{
245 return set_pte_bit(pte, __pgprot(L_PTE_DIRTY));
246}
247
248static inline pte_t pte_mkold(pte_t pte)
249{
250 return clear_pte_bit(pte, __pgprot(L_PTE_YOUNG));
251}
252
253static inline pte_t pte_mkyoung(pte_t pte)
254{
255 return set_pte_bit(pte, __pgprot(L_PTE_YOUNG));
256}
257
258static inline pte_t pte_mkexec(pte_t pte)
259{
260 return clear_pte_bit(pte, __pgprot(L_PTE_XN));
261}
262
263static inline pte_t pte_mknexec(pte_t pte)
264{
265 return set_pte_bit(pte, __pgprot(L_PTE_XN));
266}
267
268static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
269{
270 const pteval_t mask = L_PTE_XN | L_PTE_RDONLY | L_PTE_USER |
271 L_PTE_NONE | L_PTE_VALID;
272 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
273 return pte;
274}
275
276/*
277 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
278 * are !pte_none() && !pte_present().
279 *
280 * Format of swap PTEs:
281 *
282 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
283 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
284 * <------------------- offset ------------------> E < type -> 0 0
285 *
286 * E is the exclusive marker that is not stored in swap entries.
287 *
288 * This gives us up to 31 swap files and 64GB per swap file. Note that
289 * the offset field is always non-zero.
290 */
291#define __SWP_TYPE_SHIFT 2
292#define __SWP_TYPE_BITS 5
293#define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
294#define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT + 1)
295
296#define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
297#define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT)
298#define __swp_entry(type, offset) ((swp_entry_t) { (((type) & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT) | \
299 ((offset) << __SWP_OFFSET_SHIFT) })
300
301#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
302#define __swp_entry_to_pte(swp) __pte((swp).val)
303
304static inline bool pte_swp_exclusive(pte_t pte)
305{
306 return pte_isset(pte, L_PTE_SWP_EXCLUSIVE);
307}
308
309static inline pte_t pte_swp_mkexclusive(pte_t pte)
310{
311 return set_pte_bit(pte, __pgprot(L_PTE_SWP_EXCLUSIVE));
312}
313
314static inline pte_t pte_swp_clear_exclusive(pte_t pte)
315{
316 return clear_pte_bit(pte, __pgprot(L_PTE_SWP_EXCLUSIVE));
317}
318
319/*
320 * It is an error for the kernel to have more swap files than we can
321 * encode in the PTEs. This ensures that we know when MAX_SWAPFILES
322 * is increased beyond what we presently support.
323 */
324#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
325
326/*
327 * We provide our own arch_get_unmapped_area to cope with VIPT caches.
328 */
329#define HAVE_ARCH_UNMAPPED_AREA
330#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
331
332#endif /* !__ASSEMBLY__ */
333
334#endif /* CONFIG_MMU */
335
336#endif /* _ASMARM_PGTABLE_H */