tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) Ultratronik GmbH 2024-2025 - All Rights Reserved
4 */
5
6/dts-v1/;
7#include "stm32mp157.dtsi"
8#include "stm32mp15xc.dtsi"
9#include "stm32mp15-pinctrl.dtsi"
10#include "stm32mp15xxac-pinctrl.dtsi"
11#include <dt-bindings/pinctrl/stm32-pinfunc.h>
12#include <dt-bindings/mfd/st,stpmic1.h>
13#include <dt-bindings/gpio/gpio.h>
14
15/ {
16 model = "STM STM32MP15x Ultratronik MMI_A7 board";
17 compatible = "ultratronik,stm32mp157c-ultra-fly-sbc", "st,stm32mp157";
18
19 aliases {
20 ethernet0 = ðernet0;
21 serial0 = &uart4;
22 serial1 = &uart5;
23 serial2 = &uart7;
24 serial3 = &usart1;
25 };
26
27 chosen {
28 stdout-path = "serial0:115200n8";
29 };
30
31 memory@c0000000 {
32 device_type = "memory";
33 reg = <0xC0000000 0x40000000>;
34 };
35
36 usb_otg_vbus: regulator-0 {
37 compatible = "regulator-fixed";
38 regulator-name = "usb_otg_vbus";
39 regulator-min-microvolt = <5000000>;
40 regulator-max-microvolt = <5000000>;
41 gpio = <&gpioh 3 GPIO_ACTIVE_HIGH>;
42 enable-active-high;
43 };
44
45 reserved-memory {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 ranges;
49
50 retram: retram@38000000 {
51 compatible = "shared-dma-pool";
52 reg = <0x38000000 0x10000>;
53 no-map;
54 };
55
56 mcuram: mcuram@30000000 {
57 compatible = "shared-dma-pool";
58 reg = <0x30000000 0x40000>;
59 no-map;
60 };
61
62 mcuram2: mcuram2@10000000 {
63 compatible = "shared-dma-pool";
64 reg = <0x10000000 0x40000>;
65 no-map;
66 };
67
68 vdev0vring0: vdev0vring0@10040000 {
69 compatible = "shared-dma-pool";
70 reg = <0x10040000 0x2000>;
71 no-map;
72 };
73
74 vdev0vring1: vdev0vring1@10042000 {
75 compatible = "shared-dma-pool";
76 reg = <0x10042000 0x2000>;
77 no-map;
78 };
79
80 vdev0buffer: vdev0buffer@10044000 {
81 compatible = "shared-dma-pool";
82 reg = <0x10044000 0x4000>;
83 no-map;
84 };
85
86 gpu_reserved: gpu@f8000000 {
87 reg = <0xf8000000 0x8000000>;
88 no-map;
89 };
90 };
91
92 leds: leds {
93 compatible = "gpio-leds";
94
95 led0 {
96 label = "buzzer";
97 gpios = <&gpiof 2 GPIO_ACTIVE_HIGH>;
98 default-state = "off";
99 linux,default-trigger = "none";
100 };
101
102 led1 {
103 label = "led1";
104 gpios = <&gpioa 12 GPIO_ACTIVE_LOW>;
105 default-state = "off";
106 };
107
108 led2 {
109 label = "led2";
110 gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
111 default-state = "off";
112 };
113
114 led3 {
115 label = "led3";
116 gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
117 default-state = "off";
118 };
119 };
120
121 gpio_keys: gpio-keys {
122 compatible = "gpio-keys";
123
124 key-1 {
125 label = "KEY1";
126 gpios = <&gpiod 1 GPIO_ACTIVE_HIGH>;
127 wakeup-source;
128 linux,code = <2>;
129 };
130
131 key-2 {
132 label = "KEY2";
133 gpios = <&gpiod 7 GPIO_ACTIVE_HIGH>;
134 wakeup-source;
135 linux,code = <3>;
136 };
137 };
138};
139
140&adc {
141 pinctrl-names = "default";
142 pinctrl-0 = <&adc1_ux_ain_pins_a>;
143 vdd-supply = <&vdd>;
144 vdda-supply = <&vdd>;
145 vref-supply = <&vrefbuf>;
146 status = "okay";
147
148 adc1: adc@0 {
149 st,min-sample-time-nsecs = <5000>;
150 st,adc-channels = <0 1 6 13>; /* ANA0 ANA1 PF12 PC3 */
151 status = "okay";
152 };
153
154 adc2: adc@100 {
155 st,adc-channels = <0 1 12>; /* ANA0 ANA1 INT_TEMP*/
156 st,min-sample-time-nsecs = <10000>;
157 status = "okay";
158
159 channel@12 {
160 reg = <12>; /* Channel 12 = internal temperature sensor */
161 label = "internal_temp";
162 };
163 };
164};
165
166&dac {
167 pinctrl-names = "default";
168 pinctrl-0 = <&dac_ux_ch1_pins_a &dac_ux_ch2_pins_a>;
169 vref-supply = <&vrefbuf>;
170 status = "okay";
171
172 dac1: dac@1 {
173 status = "okay";
174 };
175
176 dac2: dac@2 {
177 status = "okay";
178 };
179};
180
181&dts {
182 compatible = "st,stm32-thermal";
183 status = "okay";
184};
185
186ðernet0 {
187 status = "okay";
188 pinctrl-0 = <ðernet0_ux_rgmii_pins_a>;
189 pinctrl-1 = <ðernet0_ux_rgmii_pins_sleep_a>;
190 pinctrl-names = "default", "sleep";
191 phy-mode = "rgmii-id";
192 phy-handle = <&phy1>;
193
194 mdio {
195 #address-cells = <1>;
196 #size-cells = <0>;
197 compatible = "snps,dwmac-mdio";
198 phy1: ethernet-phy@1 {
199 reg = <1>;
200 };
201 };
202};
203
204&gpioa {
205 gpio-line-names =
206 "#PMIC_IRQ", "", "", "", "DAC1", "DAC2", "", "",
207 "", "", "OTG_ID", "TIM1_4", "#LED1", "#LED2", "#LED3", "";
208};
209
210&gpiob {
211 gpio-line-names =
212 "", "", "", "", "", "", "", "",
213 "", "", "", "", "", "", "", "";
214};
215
216&gpioc {
217 gpio-line-names =
218 "#AMP_SD", "", "", "ANA5", "", "", "", "",
219 "", "", "", "", "", "PMIC_WAKEUP", "", "";
220};
221
222&gpiod {
223 gpio-line-names =
224 "#G_INT", "#TASTER1", "", "", "GPIO1", "GPIO2", "", "#TASTER2",
225 "", "", "", "", "", "", "TIM4_3", "TIM4_4";
226};
227
228&gpioe {
229 gpio-line-names =
230 "", "", "", "", "", "", "", "",
231 "", "", "PWM2", "", "", "", "", "";
232};
233
234&gpiof {
235 gpio-line-names =
236 "#SD1_CD", "SD1_WP", "BUZZER", "#DISP_POW", "BKL_POW", "#CAM_RES", "", "",
237 "", "TIM17_1N", "", "CAM_PWDN", "ANA6", "ENA_USB", "", "";
238};
239
240&gpiog {
241 gpio-line-names =
242 "#ESP_RES", "#ESP_BOOT", "GPIO3", "GPIO4", "", "", "", "",
243 "", "#TOUCH_IRQ", "", "", "", "", "", "#PCAP_RES";
244};
245
246&gpioh {
247 gpio-line-names =
248 "", "CAM_LED", "", "USB_OTG_PWR", "", "USB_OTG_OC", "", "",
249 "", "", "", "", "", "", "", "";
250};
251
252&gpioi {
253 gpio-line-names =
254 "BKL_PWM", "", "", "", "", "", "", "",
255 "#SPI_CS0", "", "", "#SPI_CS1", "", "", "", "";
256};
257
258&gpioj {
259 gpio-line-names =
260 "", "", "", "", "", "", "", "",
261 "", "", "", "", "", "", "", "";
262};
263
264&gpiok {
265 gpio-line-names =
266 "", "", "", "", "", "", "", "",
267 "", "", "", "", "", "", "", "";
268};
269
270&gpioz {
271 gpio-line-names =
272 "", "", "", "#SPI_CS2", "", "", "", "",
273 "", "", "", "", "", "", "", "";
274};
275
276&gpu {
277 status = "okay";
278};
279
280&i2c1 {
281 pinctrl-names = "default", "sleep";
282 pinctrl-0 = <&i2c1_ux_pins_a>;
283 pinctrl-1 = <&i2c1_ux_pins_sleep_a>;
284 i2c-scl-rising-time-ns = <100>;
285 i2c-scl-falling-time-ns = <7>;
286 status = "okay";
287 /delete-property/dmas;
288 /delete-property/dma-names;
289
290 rtc@32 {
291 compatible = "epson,rx8900";
292 reg = <0x32>;
293 epson,vdet-disable;
294 trickle-diode-disable;
295 };
296};
297
298&i2c4 {
299 pinctrl-names = "default", "sleep";
300 pinctrl-0 = <&i2c4_ux_pins_a>;
301 pinctrl-1 = <&i2c4_ux_pins_sleep_a>;
302 i2c-scl-rising-time-ns = <185>;
303 i2c-scl-falling-time-ns = <20>;
304 status = "okay";
305 /delete-property/dmas;
306 /delete-property/dma-names;
307
308 pmic: pmic@33 {
309 compatible = "st,stpmic1";
310 reg = <0x33>;
311 interrupts-extended = <&exti 0 IRQ_TYPE_EDGE_FALLING>;
312 interrupt-controller;
313 #interrupt-cells = <2>;
314
315 regulators {
316 compatible = "st,stpmic1-regulators";
317
318 ldo1-supply = <&v3v3>;
319 ldo3-supply = <&vdd_ddr>;
320 ldo6-supply = <&v3v3>;
321 pwr_sw1-supply = <&bst_out>;
322 pwr_sw2-supply = <&bst_out>;
323
324 vddcore: buck1 {
325 regulator-name = "vddcore";
326 regulator-min-microvolt = <1250000>;
327 regulator-max-microvolt = <1350000>;
328 regulator-always-on;
329 regulator-initial-mode = <0>;
330 regulator-over-current-protection;
331 };
332
333 vdd_ddr: buck2 {
334 regulator-name = "vdd_ddr";
335 regulator-min-microvolt = <1350000>;
336 regulator-max-microvolt = <1350000>;
337 regulator-always-on;
338 regulator-initial-mode = <0>;
339 regulator-over-current-protection;
340 };
341
342 vdd: buck3 {
343 regulator-name = "vdd";
344 regulator-min-microvolt = <3300000>;
345 regulator-max-microvolt = <3300000>;
346 regulator-always-on;
347 st,mask-reset;
348 regulator-initial-mode = <0>;
349 regulator-over-current-protection;
350 };
351
352 v3v3: buck4 {
353 regulator-name = "v3v3";
354 regulator-min-microvolt = <3300000>;
355 regulator-max-microvolt = <3300000>;
356 regulator-always-on;
357 regulator-over-current-protection;
358 regulator-initial-mode = <0>;
359 };
360
361 vtt_ddr: ldo3 {
362 regulator-name = "vtt_ddr";
363 regulator-min-microvolt = <500000>;
364 regulator-max-microvolt = <750000>;
365 regulator-always-on;
366 regulator-over-current-protection;
367 };
368
369 vdd_usb: ldo4 {
370 regulator-name = "vdd_usb";
371 regulator-min-microvolt = <3300000>;
372 regulator-max-microvolt = <3300000>;
373 regulator-always-on;
374 interrupts = <IT_CURLIM_LDO4 0>;
375 };
376
377 v1v8: ldo6 {
378 regulator-name = "v1v8";
379 regulator-min-microvolt = <1600000>;/* offset +200 mv ??? */
380 regulator-max-microvolt = <1600000>;/* real 1800000 */
381 regulator-always-on;
382 interrupts = <IT_CURLIM_LDO6 0>;
383 };
384
385 vref_ddr: vref_ddr {
386 regulator-name = "vref_ddr";
387 regulator-always-on;
388 };
389
390 bst_out: boost {
391 regulator-name = "bst_out";
392 interrupts = <IT_OCP_BOOST 0>;
393 };
394
395 vbus_otg: pwr_sw1 {
396 regulator-name = "vbus_otg";
397 interrupts = <IT_OCP_OTG 0>;
398 regulator-active-discharge = <1>;
399 };
400
401 vbus_sw: pwr_sw2 {
402 regulator-name = "vbus_sw";
403 interrupts = <IT_OCP_SWOUT 0>;
404 regulator-active-discharge = <1>;
405 };
406 };
407 };
408};
409
410&iwdg2 {
411 timeout-sec = <32>;
412 status = "okay";
413};
414
415&m_can2 {
416 pinctrl-names = "default", "sleep";
417 pinctrl-0 = <&m_can2_ux_pins_a>;
418 pinctrl-1 = <&m_can2_ux_sleep_pins_a>;
419 status = "okay";
420};
421
422&pinctrl {
423
424 adc1_ux_ain_pins_a: adc1-ux-ain-0 {
425 pins {
426 pinmux = <STM32_PINMUX('F',12, ANALOG)>, /* ADC1 in6 */
427 <STM32_PINMUX('C', 3, ANALOG)>; /* ADC2 in13 */
428 };
429 };
430
431 dac_ux_ch1_pins_a: dac-ux-ch1-0 {
432 pins {
433 pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
434 };
435 };
436
437 dac_ux_ch2_pins_a: dac-ux-ch2-0 {
438 pins {
439 pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
440 };
441 };
442
443 ethernet0_ux_rgmii_pins_a: rgmii-ux-0 {
444 pins1 {
445 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
446 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
447 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
448 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
449 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
450 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
451 <STM32_PINMUX('B', 11, AF11)>; /* ETH_RGMII_TX_CTL */
452 bias-disable;
453 drive-push-pull;
454 slew-rate = <2>;
455 };
456 pins2 {
457 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
458 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
459 <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
460 <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */
461 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
462 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
463 bias-disable;
464 };
465 pins3 {
466 pinmux = <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
467 bias-disable;
468 drive-push-pull;
469 slew-rate = <0>;
470 };
471 pins4 {
472 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
473 bias-disable;
474 drive-open-drain;
475 slew-rate = <0>;
476 };
477 };
478
479 ethernet0_ux_rgmii_pins_sleep_a: rgmii-ux-sleep-0 {
480 pins1 {
481 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
482 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
483 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
484 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
485 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
486 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
487 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
488 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
489 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
490 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
491 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
492 <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
493 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
494 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
495 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
496 };
497 };
498
499 i2c1_ux_pins_a: i2c1-0 {
500 pins {
501 pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
502 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
503 bias-disable;
504 drive-open-drain;
505 slew-rate = <0>;
506 };
507 };
508
509 i2c1_ux_pins_sleep_a: i2c1-1 {
510 pins {
511 pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */
512 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
513 };
514 };
515
516 m_can2_ux_pins_a: m-can2-ux-0 {
517 pins1 {
518 pinmux = <STM32_PINMUX('B', 6, AF9)>; /* CAN1_TX */
519 slew-rate = <0>;
520 drive-push-pull;
521 bias-disable;
522 };
523
524 pins2 {
525 pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN1_RX */
526 bias-disable;
527 };
528 };
529
530 m_can2_ux_sleep_pins_a: m-can2-ux-sleep-0 {
531 pins {
532 pinmux = <STM32_PINMUX('B', 6, ANALOG)>, /* CAN1_TX */
533 <STM32_PINMUX('B', 5, ANALOG)>; /* CAN1_RX */
534 };
535 };
536 pwm1_ux_pins_a: pwm1-0 {
537 pins {
538 pinmux = <STM32_PINMUX('A',11, AF1)>, /* TIM1_CH4 */
539 <STM32_PINMUX('E',10, AF1)>; /* TIM1_CH2N */
540 bias-pull-down;
541 drive-push-pull;
542 slew-rate = <0>;
543 };
544 };
545
546 pwm1_ux_sleep_pins_a: pwm1-sleep-0 {
547 pins {
548 pinmux = <STM32_PINMUX('A',11, ANALOG)>, /* TIM1_CH4 */
549 <STM32_PINMUX('E',10, ANALOG)>; /* TIM1_CH2N */
550 };
551 };
552
553 pwm4_ux_pins_a: pwm4-0 {
554 pins {
555 pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */
556 <STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */
557 bias-disable;
558 };
559 };
560
561 pwm4_ux_sleep_pins_a: pwm4-sleep-0 {
562 pins {
563 pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */
564 <STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */
565 };
566 };
567
568 pwm5_ux_pins_a: pwm5-0 {
569 pins {
570 pinmux = <STM32_PINMUX('I', 0, AF2)>; /* TIM5_CH4 */
571 bias-pull-down;
572 drive-push-pull;
573 slew-rate = <0>;
574 };
575 };
576
577 pwm5_ux_sleep_pins_a: pwm5-sleep-0 {
578 pins {
579 pinmux = <STM32_PINMUX('I', 0, ANALOG)>; /* TIM5_CH4 */
580 };
581 };
582
583 pwm17_ux_pins_a: pwm17-0 {
584 pins {
585 pinmux = <STM32_PINMUX('F', 9, AF1)>; /* TIM17_CH1N */
586 bias-pull-down;
587 drive-push-pull;
588 slew-rate = <0>;
589 };
590 };
591
592 pwm17_ux_sleep_pins_a: pwm17-sleep-0 {
593 pins {
594 pinmux = <STM32_PINMUX('F', 9, ANALOG)>; /* TIM17_CH1N */
595 };
596 };
597
598 qspi_bk1_ux_pins_a: qspi-bk1-ux-0 {
599 pins1 {
600 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
601 <STM32_PINMUX('D',12, AF9)>, /* QSPI_BK1_IO1 */
602 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
603 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
604 bias-disable;
605 drive-push-pull;
606 slew-rate = <1>;
607 };
608
609 pins2 {
610 pinmux = <STM32_PINMUX('B',10, AF9)>; /* QSPI_BK1_NCS */
611 bias-pull-up;
612 drive-push-pull;
613 slew-rate = <1>;
614 };
615 };
616
617 qspi_bk1_ux_sleep_pins_a: qspi-bk1-ux-sleep-0 {
618 pins {
619 pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
620 <STM32_PINMUX('D',12, ANALOG)>, /* QSPI_BK1_IO1 */
621 <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
622 <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
623 <STM32_PINMUX('B',10, ANALOG)>; /* QSPI_BK1_NCS */
624 };
625 };
626
627 qspi_clk_ux_pins_a: qspi-clk_ux-0 {
628 pins {
629 pinmux = <STM32_PINMUX('G', 7, AF9)>; /* QSPI_CLK */
630 bias-disable;
631 drive-push-pull;
632 slew-rate = <3>;
633 };
634 };
635
636 qspi_clk_ux_sleep_pins_a: qspi-clk-ux-sleep-0 {
637 pins {
638 pinmux = <STM32_PINMUX('G', 7, ANALOG)>; /* QSPI_CLK */
639 };
640 };
641
642 sai2a_ux_pins_a: sai2a-0 {
643 pins {
644 pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
645 <STM32_PINMUX('D',11, AF10)>, /* SAI2_SD_A */
646 <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
647 <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
648 slew-rate = <0>;
649 drive-push-pull;
650 bias-disable;
651 };
652 };
653
654 sai2a_ux_sleep_pins_a: sai2a-1 {
655 pins {
656 pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */
657 <STM32_PINMUX('D',11, ANALOG)>, /* SAI2_SD_A */
658 <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
659 <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */
660 };
661 };
662
663 sdmmc1_ux_b4_pins_a: sdmmc1-ux-b4-0 {
664 pins1 {
665 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
666 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
667 <STM32_PINMUX('C',10, AF12)>, /* SDMMC1_D2 */
668 <STM32_PINMUX('C',11, AF12)>, /* SDMMC1_D3 */
669 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
670 slew-rate = <1>;
671 drive-push-pull;
672 bias-disable;
673 };
674 pins2 {
675 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
676 slew-rate = <2>;
677 drive-push-pull;
678 bias-disable;
679 };
680 };
681
682 sdmmc1_ux_b4_od_pins_a: sdmmc1-b4-od-0 {
683 pins1 {
684 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
685 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
686 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
687 <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
688 slew-rate = <1>;
689 drive-push-pull;
690 bias-disable;
691 };
692 pins2 {
693 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
694 slew-rate = <2>;
695 drive-push-pull;
696 bias-disable;
697 };
698 pins3 {
699 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
700 slew-rate = <1>;
701 drive-open-drain;
702 bias-disable;
703 };
704 };
705
706 sdmmc1_ux_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
707 pins {
708 pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
709 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
710 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
711 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
712 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
713 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
714 };
715 };
716
717 sdmmc2_ux_b4_pins_a: sdmmc2-ux-b4-0 {
718 pins1 {
719 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
720 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
721 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
722 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
723 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
724 slew-rate = <1>;
725 drive-push-pull;
726 bias-pull-up;
727 };
728 pins2 {
729 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
730 slew-rate = <2>;
731 drive-push-pull;
732 bias-pull-up;
733 };
734 };
735
736 sdmmc2_ux_b4_od_pins_a: sdmmc2-ux-b4-od-0 {
737 pins1 {
738 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
739 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
740 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
741 <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
742 slew-rate = <1>;
743 drive-push-pull;
744 bias-pull-up;
745 };
746 pins2 {
747 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
748 slew-rate = <2>;
749 drive-push-pull;
750 bias-pull-up;
751 };
752 pins3 {
753 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
754 slew-rate = <1>;
755 drive-open-drain;
756 bias-pull-up;
757 };
758 };
759
760 sdmmc2_ux_b4_sleep_pins_a: sdmmc2-ux-b4-sleep-0 {
761 pins {
762 pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
763 <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
764 <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
765 <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
766 <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
767 <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
768 };
769 };
770
771 sdmmc2_ux_d47_pins_a: sdmmc2-ux-d47-0 {
772 pins {
773 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
774 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
775 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
776 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
777 slew-rate = <1>;
778 drive-push-pull;
779 bias-pull-up;
780 };
781 };
782
783 sdmmc2_ux_d47_sleep_pins_a: sdmmc2-ux-d47-sleep-0 {
784 pins {
785 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
786 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
787 <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */
788 <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
789 };
790 };
791
792 uart4_ux_pins_a: uart4-ux-0 {
793 pins1 {
794 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
795 bias-disable;
796 drive-push-pull;
797 slew-rate = <0>;
798 };
799 pins2 {
800 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
801 bias-disable;
802 };
803 };
804
805 uart4_ux_idle_pins_a: uart4-ux-idle-0 {
806 pins1 {
807 pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
808 };
809 pins2 {
810 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
811 bias-disable;
812 };
813 };
814
815 uart4_ux_sleep_pins_a: uart4-ux-sleep-0 {
816 pins {
817 pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */
818 <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
819 };
820 };
821
822 uart5_ux_pins_a: uart5-0 {
823 pins1 {
824 pinmux = <STM32_PINMUX('B', 13, AF14)>; /* UART5_TX */
825 bias-disable;
826 drive-push-pull;
827 slew-rate = <0>;
828 };
829 pins2 {
830 pinmux = <STM32_PINMUX('B', 12, AF14)>; /* UART5_RX */
831 bias-disable;
832 };
833 };
834
835 uart5_ux_idle_pins_a: uart5-idle-0 {
836 pins1 {
837 pinmux = <STM32_PINMUX('B', 13, ANALOG)>; /* UART5_TX */
838 };
839 pins2 {
840 pinmux = <STM32_PINMUX('B', 12, AF14)>; /* UART5_RX*/
841 bias-disable;
842 };
843 };
844
845 uart5_ux_sleep_pins_a: uart5-sleep-0 {
846 pins {
847 pinmux = <STM32_PINMUX('B', 13, ANALOG)>, /* UART5_TX */
848 <STM32_PINMUX('B', 12, ANALOG)>; /* UART5_RX */
849 };
850 };
851
852 uart7_ux_pins_a: uart7-0 {
853 pins1 {
854 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* USART7_TX */
855 bias-pull-up;
856 drive-push-pull;
857 slew-rate = <0>;
858 };
859
860 pins2 {
861 pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */
862 bias-pull-up;
863 };
864 pins3 {
865 pinmux = <STM32_PINMUX('E', 9, AF7)>; /* USART7_RTS/DE */
866 };
867 };
868
869 uart7_ux_idle_pins_a: uart7-idle-0 {
870 pins1 {
871 pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* USART7_TX */
872 <STM32_PINMUX('E', 9, AF7)>; /* USART7_RTS/DE */
873 };
874 pins2 {
875 pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */
876 bias-disable;
877 };
878 };
879
880 uart7_ux_sleep_pins_a: uart7-sleep-0 {
881 pins {
882 pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* USART7_TX */
883 <STM32_PINMUX('E', 9, AF7)>, /* USART7_RTS/DE */
884 <STM32_PINMUX('E', 7, ANALOG)>; /* USART7_RX */
885 };
886 };
887};
888
889&pinctrl_z {
890
891 i2c4_ux_pins_a: i2c4-ux-0 {
892 pins {
893 pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
894 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
895 bias-disable;
896 drive-open-drain;
897 slew-rate = <0>;
898 };
899 };
900
901 i2c4_ux_pins_sleep_a: i2c4-1 {
902 pins {
903 pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
904 <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
905 };
906 };
907
908 spi1_ux_pins_a: spi1-ux-0 {
909 pins1 {
910 pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
911 <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
912 bias-disable;
913 drive-push-pull;
914 slew-rate = <1>;
915 };
916
917 pins2 {
918 pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
919 bias-disable;
920 };
921 };
922
923 spi1_ux_sleep_pins_a: spi1-ux-sleep-0 {
924 pins {
925 pinmux = <STM32_PINMUX('Z', 0, ANALOG)>, /* SPI1_SCK */
926 <STM32_PINMUX('Z', 1, ANALOG)>, /* SPI1_MISO */
927 <STM32_PINMUX('Z', 2, ANALOG)>; /* SPI1_MOSI */
928 };
929 };
930};
931
932&pwr_regulators {
933 vdd-supply = <&vdd>;
934 vdd_3v3_usbfs-supply = <&vdd_usb>;
935};
936
937&qspi {
938 pinctrl-names = "default", "sleep";
939 pinctrl-0 = <&qspi_clk_ux_pins_a &qspi_bk1_ux_pins_a>;
940 pinctrl-1 = <&qspi_clk_ux_sleep_pins_a &qspi_bk1_ux_sleep_pins_a>;
941 reg = <0x58003000 0x1000>, <0x70000000 0x1000000>;
942 #address-cells = <1>;
943 #size-cells = <0>;
944 status = "okay";
945
946 flash0: flash@0 {
947 compatible = "jedec,spi-nor";
948 reg = <0>;
949 spi-rx-bus-width = <4>;
950 spi-max-frequency = <133000000>;
951 #address-cells = <1>;
952 #size-cells = <1>;
953 };
954};
955
956&sdmmc1 {
957 pinctrl-names = "default", "opendrain", "sleep";
958 pinctrl-0 = <&sdmmc1_ux_b4_pins_a>;
959 pinctrl-1 = <&sdmmc1_ux_b4_od_pins_a>;
960 pinctrl-2 = <&sdmmc1_ux_b4_sleep_pins_a>;
961 broken-cd;
962 st,neg-edge;
963 bus-width = <4>;
964 vmmc-supply = <&v3v3>;
965 no-1-8-v;
966 status = "okay";
967};
968
969&sdmmc2 {
970 pinctrl-names = "default", "opendrain", "sleep";
971 pinctrl-0 = <&sdmmc2_ux_b4_pins_a &sdmmc2_ux_d47_pins_a>;
972 pinctrl-1 = <&sdmmc2_ux_b4_od_pins_a &sdmmc2_ux_d47_pins_a>;
973 pinctrl-2 = <&sdmmc2_ux_b4_sleep_pins_a &sdmmc2_ux_d47_sleep_pins_a>;
974 non-removable;
975 no-sd;
976 no-sdio;
977 st,neg-edge;
978 bus-width = <8>;
979 vmmc-supply = <&v3v3>;
980 vqmmc-supply = <&v3v3>;
981 mmc-ddr-3_3v;
982 status = "okay";
983};
984
985&spi1 {
986 pinctrl-names = "default", "sleep";
987 pinctrl-0 = <&spi1_ux_pins_a>;
988 pinctrl-1 = <&spi1_ux_sleep_pins_a>;
989 status = "okay";
990 cs-gpios = <&gpioi 8 0>, <&gpioi 11 0>, <&gpioz 3 0>;
991
992 flash: flash@0 {
993 #address-cells = <1>;
994 #size-cells = <1>;
995 compatible = "jedec,spi-nor";
996 spi-max-frequency = <20000000>;
997 reg = <0>;
998 };
999};
1000
1001&timers1 {
1002 /* spare dmas for other usage */
1003 /delete-property/dmas;
1004 /delete-property/dma-names;
1005 status = "okay";
1006
1007 pwm {
1008 pinctrl-0 = <&pwm1_ux_pins_a>;
1009 pinctrl-1 = <&pwm1_ux_sleep_pins_a>;
1010 pinctrl-names = "default", "sleep";
1011 status = "okay";
1012 };
1013
1014 timer@0 {
1015 status = "okay";
1016 };
1017};
1018
1019&timers4 {
1020 dmas = <&dmamux1 31 0x400 0x5>;
1021 dma-names = "ch3";
1022 status = "okay";
1023
1024 pwm4_4: pwm {
1025 pinctrl-0 = <&pwm4_ux_pins_a>;
1026 pinctrl-1 = <&pwm4_ux_sleep_pins_a>;
1027 pinctrl-names = "default", "sleep";
1028 status = "okay";
1029 };
1030};
1031
1032&timers5 {
1033 /delete-property/dmas;
1034 /delete-property/dma-names;
1035 status = "okay";
1036
1037 pwm5_4: pwm {
1038 pinctrl-0 = <&pwm5_ux_pins_a>;
1039 pinctrl-1 = <&pwm5_ux_sleep_pins_a>;
1040 pinctrl-names = "default", "sleep";
1041 status = "okay";
1042 };
1043
1044 timer@4 {
1045 status = "okay";
1046 };
1047};
1048
1049&timers17 {
1050 /delete-property/dmas;
1051 /delete-property/dma-names;
1052 status = "okay";
1053
1054 pwm17_4: pwm {
1055 pinctrl-0 = <&pwm17_ux_pins_a>;
1056 pinctrl-1 = <&pwm17_ux_sleep_pins_a>;
1057 pinctrl-names = "default", "sleep";
1058 status = "okay";
1059 };
1060
1061 timer@16 {
1062 status = "okay";
1063 };
1064};
1065
1066&uart4 {
1067 /delete-property/dmas;
1068 /delete-property/dma-names;
1069 pinctrl-names = "default", "sleep", "idle", "no_console_suspend";
1070 pinctrl-0 = <&uart4_ux_pins_a>;
1071 pinctrl-1 = <&uart4_ux_sleep_pins_a>;
1072 pinctrl-2 = <&uart4_ux_idle_pins_a>;
1073 pinctrl-3 = <&uart4_ux_pins_a>;
1074 status = "okay";
1075};
1076
1077&uart5 {
1078 pinctrl-names = "default", "sleep", "idle";
1079 pinctrl-0 = <&uart5_ux_pins_a>;
1080 pinctrl-1 = <&uart5_ux_sleep_pins_a>;
1081 pinctrl-2 = <&uart5_ux_idle_pins_a>;
1082 status = "okay";
1083};
1084
1085&uart7 {
1086 /delete-property/dmas;
1087 /delete-property/dma-names;
1088 pinctrl-names = "default", "sleep", "idle";
1089 pinctrl-0 = <&uart7_ux_pins_a>;
1090 pinctrl-1 = <&uart7_ux_sleep_pins_a>;
1091 pinctrl-2 = <&uart7_ux_idle_pins_a>;
1092 status = "okay";
1093};
1094
1095&usart1 {
1096 /*Muxing happens in uboot*/
1097 status = "okay";
1098};
1099
1100&usbh_ehci {
1101 phys = <&usbphyc_port0>;
1102 phy-names = "usb";
1103 status = "okay";
1104};
1105
1106&usbh_ohci {
1107 phys = <&usbphyc_port0>;
1108 phy-names = "usb";
1109 status = "okay";
1110};
1111
1112&usbotg_hs {
1113 phys = <&usbphyc_port1 0>;
1114 phy-names = "usb2-phy";
1115 vbus-supply = <&usb_otg_vbus>;
1116 status = "okay";
1117};
1118
1119&usbphyc {
1120 status = "okay";
1121};
1122
1123&usbphyc_port0 {
1124 phy-supply = <&vdd_usb>;
1125 st,tune-hs-dc-level = <2>;
1126 st,enable-fs-rftime-tuning;
1127 st,enable-hs-rftime-reduction;
1128 st,trim-hs-current = <15>;
1129 st,trim-hs-impedance = <1>;
1130 st,tune-squelch-level = <3>;
1131 st,tune-hs-rx-offset = <2>;
1132 st,no-lsfs-sc;
1133};
1134
1135&usbphyc_port1 {
1136 phy-supply = <&vdd_usb>;
1137 st,tune-hs-dc-level = <2>;
1138 st,enable-fs-rftime-tuning;
1139 st,enable-hs-rftime-reduction;
1140 st,trim-hs-current = <15>;
1141 st,trim-hs-impedance = <1>;
1142 st,tune-squelch-level = <3>;
1143 st,tune-hs-rx-offset = <2>;
1144 st,no-lsfs-sc;
1145};
1146
1147&vrefbuf {
1148 regulator-min-microvolt = <2500000>;
1149 regulator-max-microvolt = <2500000>;
1150 vdda-supply = <&vdd>;
1151 status = "okay";
1152};