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(I'm so sorry!) Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596============= Ring Buffer=============
To handle communication between user space and kernel space, AMD GPUs use aring buffer design to feed the engines (GFX, Compute, SDMA, UVD, VCE, VCN, VPE,etc.). See the figure below that illustrates how this communication works:
.. kernel-figure:: ring_buffers.svg
Ring buffers in the amdgpu work as a producer-consumer model, where userspaceacts as the producer, constantly filling the ring buffer with GPU commands tobe executed. Meanwhile, the GPU retrieves the information from the ring, parsesit, and distributes the specific set of instructions between the differentamdgpu blocks.
Notice from the diagram that the ring has a Read Pointer (rptr), whichindicates where the engine is currently reading packets from the ring, and aWrite Pointer (wptr), which indicates how many packets software has added tothe ring. When the rptr and wptr are equal, the ring is idle. When softwareadds packets to the ring, it updates the wptr, this causes the engine to startfetching and processing packets. As the engine processes packets, the rptr getsupdates until the rptr catches up to the wptr and they are equal again.
Usually, ring buffers in the driver have a limited size (search for occurrencesof `amdgpu_ring_init()`). One of the reasons for the small ring buffer size isthat CP (Command Processor) is capable of following addresses inserted into thering; this is illustrated in the image by the reference to the IB (IndirectBuffer). The IB gives userspace the possibility to have an area in memory thatCP can read and feed the hardware with extra instructions.
All ASICs pre-GFX11 use what is called a kernel queue, which meansthe ring is allocated in kernel space and has some restrictions, such as notbeing able to be :ref:`preempted directly by the scheduler<amdgpu-mes>`. GFX11and newer support kernel queues, but also provide a new mechanism named:ref:`user queues<amdgpu-userq>`, where the queue is moved to the user spaceand can be mapped and unmapped via the scheduler. In practice, both queuesinsert user-space-generated GPU commands from different jobs into the requestedcomponent ring.
Enforce Isolation=================
.. note:: After reading this section, you might want to check the :ref:`Process Isolation<amdgpu-process-isolation>` page for more details.
Before examining the Enforce Isolation mechanism in the ring buffer context, itis helpful to briefly discuss how instructions from the ring buffer areprocessed in the graphics pipeline. Let’s expand on this topic by checking thediagram below that illustrates the graphics pipeline:
.. kernel-figure:: gfx_pipeline_seq.svg
In terms of executing instructions, the GFX pipeline follows the sequence:Shader Export (SX), Geometry Engine (GE), Shader Process or Input (SPI), ScanConverter (SC), Primitive Assembler (PA), and cache manipulation (which mayvary across ASICs). Another common way to describe the pipeline is to use PixelShader (PS), raster, and Vertex Shader (VS) to symbolize the two shader stages.Now, with this pipeline in mind, let's assume that Job B causes a hang issue,but Job C's instruction might already be executing, leading developers toincorrectly identify Job C as the problematic one. This problem can bemitigated on multiple levels; the diagram below illustrates how to minimizepart of this problem:
.. kernel-figure:: no_enforce_isolation.svg
Note from the diagram that there is no guarantee of order or a clear separationbetween instructions, which is not a problem most of the time, and is also goodfor performance. Furthermore, notice some circles between jobs in the diagramthat represent a **fence wait** used to avoid overlapping work in the ring. Atthe end of the fence, a cache flush occurs, ensuring that when the next jobstarts, it begins in a clean state and, if issues arise, the developer canpinpoint the problematic process more precisely.
To increase the level of isolation between jobs, there is the "EnforceIsolation" method described in the picture below:
.. kernel-figure:: enforce_isolation.svg
As shown in the diagram, enforcing isolation introduces ordering betweensubmissions, since the access to GFX/Compute is serialized, think about it assingle process at a time mode for gfx/compute. Notice that this approach has asignificant performance impact, as it allows only one job to submit commands ata time. However, this option can help pinpoint the job that caused the problem.Although enforcing isolation improves the situation, it does not fully resolvethe issue of precisely pinpointing bad jobs, since isolation might mask theproblem. In summary, identifying which job caused the issue may not be precise,but enforcing isolation might help with the debugging.
Ring Operations===============
.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c :internal: