tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/timer/andestech,plmt0.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Andes machine-level timer
8
9description:
10 The Andes machine-level timer device (PLMT0) provides machine-level timer
11 functionality for a set of HARTs on a RISC-V platform. It has a single
12 fixed-frequency monotonic time counter (MTIME) register and a time compare
13 register (MTIMECMP) for each HART connected to the PLMT0. A timer interrupt is
14 generated if MTIME >= MTIMECMP.
15
16maintainers:
17 - Ben Zong-You Xie <ben717@andestech.com>
18
19properties:
20 compatible:
21 items:
22 - enum:
23 - andestech,qilai-plmt
24 - const: andestech,plmt0
25
26 reg:
27 maxItems: 1
28
29 interrupts-extended:
30 minItems: 1
31 maxItems: 32
32 description:
33 Specifies which harts are connected to the PLMT0. Each item must points
34 to a riscv,cpu-intc node, which has a riscv cpu node as parent. The
35 PLMT0 supports 1 hart up to 32 harts.
36
37additionalProperties: false
38
39required:
40 - compatible
41 - reg
42 - interrupts-extended
43
44examples:
45 - |
46 interrupt-controller@100000 {
47 compatible = "andestech,qilai-plmt", "andestech,plmt0";
48 reg = <0x100000 0x100000>;
49 interrupts-extended = <&cpu0intc 7>,
50 <&cpu1intc 7>,
51 <&cpu2intc 7>,
52 <&cpu3intc 7>;
53 };