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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: TI K3 R5F processor subsystems
8
9maintainers:
10 - Suman Anna <s-anna@ti.com>
11
12description: |
13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
14 processor subsystems/clusters (R5FSS). The dual core cluster can be used
15 either in a LockStep mode providing safety/fault tolerance features or in a
16 Split mode providing two individual compute cores for doubling the compute
17 capacity on most SoCs. These are used together with other processors present
18 on the SoC to achieve various system level goals.
19
20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
21 called "Single-CPU" mode, where only Core0 is used, but with ability to use
22 Core1's TCMs as well.
23
24 AM62 SoC family support a single R5F core only which runs Device Manager
25 firmware and can also be used as a remote processor with IPC communication.
26
27 Each Dual-Core R5F sub-system is represented as a single DTS node
28 representing the cluster, with a pair of child DT nodes representing
29 the individual R5F cores. Each node has a number of required or optional
30 properties that enable the OS running on the host processor to perform
31 the device management of the remote processor and to communicate with the
32 remote processor.
33
34properties:
35 $nodename:
36 pattern: "^r5fss(@.*)?"
37
38 compatible:
39 enum:
40 - ti,am62-r5fss
41 - ti,am64-r5fss
42 - ti,am654-r5fss
43 - ti,j7200-r5fss
44 - ti,j721e-r5fss
45 - ti,j721s2-r5fss
46
47 power-domains:
48 description: |
49 Should contain a phandle to a PM domain provider node and an args
50 specifier containing the R5FSS device id value.
51 maxItems: 1
52
53 "#address-cells":
54 const: 1
55
56 "#size-cells":
57 const: 1
58
59 ranges:
60 description: |
61 Standard ranges definition providing address translations for
62 local R5F TCM address spaces to bus addresses.
63
64# Optional properties:
65# --------------------
66
67 ti,cluster-mode:
68 $ref: /schemas/types.yaml#/definitions/uint32
69 description: |
70 Configuration Mode for the Dual R5F cores within the R5F cluster.
71 For most SoCs (AM65x, J721E, J7200, J721s2),
72 It should be either a value of 1 (LockStep mode) or 0 (Split mode) on
73 most SoCs (AM65x, J721E, J7200, J721s2), default is LockStep mode if
74 omitted.
75 For AM64x SoCs,
76 It should be either a value of 0 (Split mode) or 2 (Single-CPU mode) and
77 default is Split mode if omitted.
78 For AM62x SoCs,
79 It should be set as 3 (Single-Core mode) which is also the default if
80 omitted.
81
82# R5F Processor Child Nodes:
83# ==========================
84
85patternProperties:
86 "^r5f@[a-f0-9]+$":
87 type: object
88 description: |
89 The R5F Sub-System device node should define two R5F child nodes, each
90 node representing a TI instantiation of the Arm Cortex R5F core. There
91 are some specific integration differences for the IP like the usage of
92 a Region Address Translator (RAT) for translating the larger SoC bus
93 addresses into a 32-bit address space for the processor. For AM62x,
94 the R5F Sub-System device node should only define one R5F child node
95 as it has only one core available.
96
97 Each R5F core has an associated 64 KB of Tightly-Coupled Memory (TCM)
98 internal memories split between two banks - TCMA and TCMB (further
99 interleaved into two banks TCMB0 and TCMB1). These memories (also called
100 ATCM and BTCM) provide read/write performance on par with the core's L1
101 caches. Each of the TCMs can be enabled or disabled independently and
102 either of them can be configured to appear at that R5F's address 0x0.
103
104 The cores do not use an MMU, but has a Region Address Translator
105 (RAT) module that is accessible only from the R5Fs for providing
106 translations between 32-bit CPU addresses into larger system bus
107 addresses. Cache and memory access settings are provided through a
108 Memory Protection Unit (MPU), programmable only from the R5Fs.
109
110 $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
111
112 properties:
113 compatible:
114 enum:
115 - ti,am62-r5f
116 - ti,am64-r5f
117 - ti,am654-r5f
118 - ti,j7200-r5f
119 - ti,j721e-r5f
120 - ti,j721s2-r5f
121
122 reg:
123 items:
124 - description: Address and Size of the ATCM internal memory region
125 - description: Address and Size of the BTCM internal memory region
126
127 reg-names:
128 items:
129 - const: atcm
130 - const: btcm
131
132 resets:
133 description: |
134 Should contain the phandle to the reset controller node managing the
135 local resets for this device, and a reset specifier.
136 maxItems: 1
137
138 firmware-name:
139 description: |
140 Should contain the name of the default firmware image
141 file located on the firmware search path
142
143# The following properties are mandatory for R5F Core0 in both LockStep and Split
144# modes, and are mandatory for R5F Core1 _only_ in Split mode. They are unused for
145# R5F Core1 in LockStep mode:
146
147 mboxes:
148 description: |
149 OMAP Mailbox specifier denoting the sub-mailbox, to be used for
150 communication with the remote processor. This property should match
151 with the sub-mailbox node used in the firmware image.
152 maxItems: 1
153
154 memory-region:
155 description: |
156 phandle to the reserved memory nodes to be associated with the
157 remoteproc device. There should be two reserved memory nodes defined
158 for the basic layout or 6 partitions for a detailed layout. The
159 reserved memory nodes should be carveout nodes, and should be defined
160 with a "no-map" property as per the bindings in
161 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
162 oneOf:
163 - description: Basic layout
164 items:
165 - description: region used for dynamic DMA allocations like vrings and
166 vring buffers
167 - description: region reserved for firmware image sections
168 - description: Detailed layout
169 items:
170 - description: region used for dynamic DMA allocations like vrings and
171 vring buffers
172 - description: region reserved for IPC resources
173 - description: LPM FS stub binary
174 - description: LPM metadata
175 - description: LPM FS context data and reserved sections
176 - description: DM RM/PM trace and firmware code/data
177
178 memory-region-names:
179 description: |
180 Names for the memory regions specified in the memory-region property.
181 The names must correspond with the entries in memory-region.
182 oneOf:
183 - description: Basic layout
184 items:
185 - const: dma
186 - const: firmware
187 - description: Detailed layout
188 items:
189 - const: dma
190 - const: ipc
191 - const: lpm-stub
192 - const: lpm-metadata
193 - const: lpm-context
194 - const: dm-firmware
195
196# Optional properties:
197# --------------------
198# The following properties are optional properties for each of the R5F cores:
199
200 ti,atcm-enable:
201 $ref: /schemas/types.yaml#/definitions/uint32
202 enum: [0, 1]
203 description: |
204 R5F core configuration mode dictating if ATCM should be enabled. The
205 R5F address of ATCM is dictated by ti,loczrama property. Should be
206 either a value of 1 (enabled) or 0 (disabled), default is disabled
207 if omitted. Recommended to enable it for maximizing TCMs.
208
209 ti,btcm-enable:
210 $ref: /schemas/types.yaml#/definitions/uint32
211 enum: [0, 1]
212 description: |
213 R5F core configuration mode dictating if BTCM should be enabled. The
214 R5F address of BTCM is dictated by ti,loczrama property. Should be
215 either a value of 1 (enabled) or 0 (disabled), default is enabled if
216 omitted.
217
218 ti,loczrama:
219 $ref: /schemas/types.yaml#/definitions/uint32
220 enum: [0, 1]
221 description: |
222 R5F core configuration mode dictating which TCM should appear at
223 address 0 (from core's view). Should be either a value of 1 (ATCM
224 at 0x0) or 0 (BTCM at 0x0), default value is 1 if omitted.
225
226 sram:
227 $ref: /schemas/types.yaml#/definitions/phandle-array
228 minItems: 1
229 maxItems: 4
230 items:
231 maxItems: 1
232 description: |
233 phandles to one or more reserved on-chip SRAM regions. The regions
234 should be defined as child nodes of the respective SRAM node, and
235 should be defined as per the generic bindings in,
236 Documentation/devicetree/bindings/sram/sram.yaml
237
238 required:
239 - compatible
240 - reg
241 - reg-names
242 - ti,sci
243 - ti,sci-dev-id
244 - ti,sci-proc-ids
245 - resets
246 - firmware-name
247
248 if:
249 required:
250 - memory-region
251 then:
252 required:
253 - memory-region-names
254
255 unevaluatedProperties: false
256
257allOf:
258 - if:
259 properties:
260 compatible:
261 enum:
262 - ti,am64-r5fss
263 then:
264 properties:
265 ti,cluster-mode:
266 enum: [0, 2]
267
268 - if:
269 properties:
270 compatible:
271 enum:
272 - ti,am654-r5fss
273 - ti,j7200-r5fss
274 - ti,j721e-r5fss
275 - ti,j721s2-r5fss
276 then:
277 properties:
278 ti,cluster-mode:
279 enum: [0, 1]
280
281 - if:
282 properties:
283 compatible:
284 enum:
285 - ti,am62-r5fss
286 then:
287 properties:
288 ti,cluster-mode:
289 enum: [3]
290
291required:
292 - compatible
293 - power-domains
294 - "#address-cells"
295 - "#size-cells"
296 - ranges
297
298additionalProperties: false
299
300examples:
301 - |
302 soc {
303 #address-cells = <2>;
304 #size-cells = <2>;
305
306 mailbox0: mailbox-0 {
307 #mbox-cells = <1>;
308 };
309
310 mailbox1: mailbox-1 {
311 #mbox-cells = <1>;
312 };
313
314 bus@100000 {
315 compatible = "simple-bus";
316 #address-cells = <2>;
317 #size-cells = <2>;
318 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
319 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
320 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
321 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>;
322
323 bus@28380000 {
324 compatible = "simple-bus";
325 #address-cells = <2>;
326 #size-cells = <2>;
327 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS */
328 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
329 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
330 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>; /* MCU SRAM */
331
332 /* AM65x MCU R5FSS node */
333 mcu_r5fss0: r5fss@41000000 {
334 compatible = "ti,am654-r5fss";
335 power-domains = <&k3_pds 129>;
336 ti,cluster-mode = <1>;
337 #address-cells = <1>;
338 #size-cells = <1>;
339 ranges = <0x41000000 0x00 0x41000000 0x20000>,
340 <0x41400000 0x00 0x41400000 0x20000>;
341
342 mcu_r5f0: r5f@41000000 {
343 compatible = "ti,am654-r5f";
344 reg = <0x41000000 0x00008000>,
345 <0x41010000 0x00008000>;
346 reg-names = "atcm", "btcm";
347 ti,sci = <&dmsc>;
348 ti,sci-dev-id = <159>;
349 ti,sci-proc-ids = <0x01 0xFF>;
350 resets = <&k3_reset 159 1>;
351 firmware-name = "am65x-mcu-r5f0_0-fw";
352 ti,atcm-enable = <1>;
353 ti,btcm-enable = <1>;
354 ti,loczrama = <1>;
355 mboxes = <&mailbox0 &mbox_mcu_r5fss0_core0>;
356 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
357 <&mcu_r5fss0_core0_memory_region>;
358 memory-region-names = "dma", "firmware";
359 sram = <&mcu_r5fss0_core0_sram>;
360 };
361
362 mcu_r5f1: r5f@41400000 {
363 compatible = "ti,am654-r5f";
364 reg = <0x41400000 0x00008000>,
365 <0x41410000 0x00008000>;
366 reg-names = "atcm", "btcm";
367 ti,sci = <&dmsc>;
368 ti,sci-dev-id = <245>;
369 ti,sci-proc-ids = <0x02 0xFF>;
370 resets = <&k3_reset 245 1>;
371 firmware-name = "am65x-mcu-r5f0_1-fw";
372 ti,atcm-enable = <1>;
373 ti,btcm-enable = <1>;
374 ti,loczrama = <1>;
375 mboxes = <&mailbox1 &mbox_mcu_r5fss0_core1>;
376 };
377 };
378 };
379 };
380 };