tjh.dev
Linux kernel mirror (for testing)
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linux
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright (C) STMicroelectronics 2019.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: STM32 GPIO and Pin Mux/Config controller
9
10maintainers:
11 - Alexandre TORGUE <alexandre.torgue@foss.st.com>
12
13description: |
14 STMicroelectronics's STM32 MCUs integrate a GPIO and Pin mux/config hardware
15 controller. It controls the input/output settings on the available pins and
16 also provides ability to multiplex and configure the output of various
17 on-chip controllers onto these pads.
18
19properties:
20 compatible:
21 enum:
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
25 - st,stm32f769-pinctrl
26 - st,stm32h743-pinctrl
27 - st,stm32mp135-pinctrl
28 - st,stm32mp157-pinctrl
29 - st,stm32mp157-z-pinctrl
30 - st,stm32mp257-pinctrl
31 - st,stm32mp257-z-pinctrl
32
33 '#address-cells':
34 const: 1
35
36 '#size-cells':
37 const: 1
38
39 ranges: true
40
41 pins-are-numbered:
42 $ref: /schemas/types.yaml#/definitions/flag
43 deprecated: true
44
45 hwlocks: true
46
47 interrupts:
48 maxItems: 1
49
50 st,syscfg:
51 description: Phandle+args to the syscon node which includes IRQ mux selection.
52 $ref: /schemas/types.yaml#/definitions/phandle-array
53 items:
54 - minItems: 2
55 items:
56 - description: syscon node which includes IRQ mux selection
57 - description: The offset of the IRQ mux selection register
58 - description: The field mask of IRQ mux, needed if different of 0xf
59
60 st,package:
61 description:
62 Indicates the SOC package used.
63 More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
64 $ref: /schemas/types.yaml#/definitions/uint32
65 enum: [0x1, 0x2, 0x4, 0x8, 0x100, 0x400, 0x800]
66
67patternProperties:
68 '^gpio@[0-9a-f]*$':
69 type: object
70 additionalProperties: false
71 properties:
72 gpio-controller: true
73
74 '#gpio-cells':
75 const: 2
76
77 interrupt-controller: true
78 '#interrupt-cells':
79 const: 2
80
81 reg:
82 maxItems: 1
83
84 clocks:
85 maxItems: 1
86
87 resets:
88 maxItems: 1
89
90 gpio-line-names: true
91
92 gpio-ranges:
93 minItems: 1
94 maxItems: 16
95
96 ngpios:
97 description:
98 Number of available gpios in a bank.
99 minimum: 1
100 maximum: 16
101
102 st,bank-name:
103 description:
104 Should be a name string for this bank as specified in the datasheet.
105 $ref: /schemas/types.yaml#/definitions/string
106 enum:
107 - GPIOA
108 - GPIOB
109 - GPIOC
110 - GPIOD
111 - GPIOE
112 - GPIOF
113 - GPIOG
114 - GPIOH
115 - GPIOI
116 - GPIOJ
117 - GPIOK
118 - GPIOZ
119
120 st,bank-ioport:
121 description:
122 Should correspond to the EXTI IOport selection (EXTI line used
123 to select GPIOs as interrupts).
124 $ref: /schemas/types.yaml#/definitions/uint32
125 minimum: 0
126 maximum: 11
127
128 patternProperties:
129 "^(.+-hog(-[0-9]+)?)$":
130 type: object
131 required:
132 - gpio-hog
133
134 required:
135 - gpio-controller
136 - '#gpio-cells'
137 - reg
138 - clocks
139 - st,bank-name
140
141 '-[0-9]*$':
142 type: object
143 additionalProperties: false
144
145 patternProperties:
146 '^pins':
147 type: object
148 additionalProperties: false
149 description: |
150 A pinctrl node should contain at least one subnode representing the
151 pinctrl group available on the machine. Each subnode will list the
152 pins it needs, and how they should be configured, with regard to muxer
153 configuration, pullups, drive, output high/low and output speed.
154 $ref: /schemas/pinctrl/pincfg-node.yaml
155
156 properties:
157 pinmux:
158 $ref: /schemas/types.yaml#/definitions/uint32-array
159 description: |
160 Integer array, represents gpio pin number and mux setting.
161 Supported pin number and mux varies for different SoCs, and are
162 defined in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
163 These defines are calculated as: ((port * 16 + line) << 8) | function
164 With:
165 - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
166 - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
167 - function: The function number, can be:
168 * 0 : GPIO
169 * 1 : Alternate Function 0
170 * 2 : Alternate Function 1
171 * 3 : Alternate Function 2
172 * ...
173 * 16 : Alternate Function 15
174 * 17 : Analog
175 * 18 : Reserved
176 To simplify the usage, macro is available to generate "pinmux" field.
177 This macro is available here:
178 - include/dt-bindings/pinctrl/stm32-pinfunc.h
179 Setting the pinmux's function to the Reserved (RSVD) value is used to inform
180 the driver that it shall not apply the mux setting. This can be used to
181 reserve some pins, for example to a co-processor not running Linux.
182 Some examples of using macro:
183 /* GPIO A9 set as alternate function 2 */
184 ... {
185 pinmux = <STM32_PINMUX('A', 9, AF2)>;
186 };
187 /* GPIO A9 set as GPIO */
188 ... {
189 pinmux = <STM32_PINMUX('A', 9, GPIO)>;
190 };
191 /* GPIO A9 set as analog */
192 ... {
193 pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
194 };
195 /* GPIO A9 reserved for co-processor */
196 ... {
197 pinmux = <STM32_PINMUX('A', 9, RSVD)>;
198 };
199
200 bias-disable: true
201
202 bias-pull-down: true
203
204 bias-pull-up: true
205
206 drive-push-pull: true
207
208 drive-open-drain: true
209
210 output-low: true
211
212 output-high: true
213
214 slew-rate:
215 description: |
216 0: Low speed
217 1: Medium speed
218 2: Fast speed
219 3: High speed
220 minimum: 0
221 maximum: 3
222
223 skew-delay-input-ps:
224 description: |
225 IO synchronization skew rate applied to the input path
226 enum: [0, 300, 500, 750, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250]
227
228 skew-delay-output-ps:
229 description: |
230 IO synchronization latch delay applied to the output path
231 enum: [0, 300, 500, 750, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250]
232
233 st,io-sync:
234 $ref: /schemas/types.yaml#/definitions/string
235 enum:
236 - pass-through
237 - clock inverted
238 - data on rising edge
239 - data on falling edge
240 - data on both edges
241 description: |
242 IO synchronization through re-sampling or inversion
243 "pass-through" - data or clock GPIO pass-through
244 "clock inverted" - clock GPIO inverted
245 "data on rising edge" - data GPIO re-sampled on clock rising edge
246 "data on falling edge" - data GPIO re-sampled on clock falling edge
247 "data on both edges" - data GPIO re-sampled on both clock edges
248 default: pass-through
249
250 required:
251 - pinmux
252
253 # Not allowed both skew-delay-input-ps and skew-delay-output-ps
254 if:
255 required:
256 - skew-delay-input-ps
257 then:
258 properties:
259 skew-delay-output-ps: false
260
261allOf:
262 - $ref: pinctrl.yaml#
263
264 - if:
265 not:
266 properties:
267 compatible:
268 contains:
269 enum:
270 - st,stm32mp257-pinctrl
271 - st,stm32mp257-z-pinctrl
272 then:
273 patternProperties:
274 '-[0-9]*$':
275 patternProperties:
276 '^pins':
277 properties:
278 skew-delay-input-ps: false
279 skew-delay-output-ps: false
280 st,io-sync: false
281
282required:
283 - compatible
284 - '#address-cells'
285 - '#size-cells'
286 - ranges
287
288additionalProperties: false
289
290examples:
291 - |
292 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
293 #include <dt-bindings/mfd/stm32f4-rcc.h>
294 //Example 1
295 pinctrl@40020000 {
296 #address-cells = <1>;
297 #size-cells = <1>;
298 compatible = "st,stm32f429-pinctrl";
299 ranges = <0 0x40020000 0x3000>;
300
301 gpioa: gpio@0 {
302 gpio-controller;
303 #gpio-cells = <2>;
304 reg = <0x0 0x400>;
305 resets = <&reset_ahb1 0>;
306 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
307 st,bank-name = "GPIOA";
308 };
309 };
310
311 //Example 2 (using gpio-ranges)
312 pinctrl@50020000 {
313 #address-cells = <1>;
314 #size-cells = <1>;
315 compatible = "st,stm32f429-pinctrl";
316 ranges = <0 0x50020000 0x3000>;
317
318 gpiob: gpio@1000 {
319 gpio-controller;
320 #gpio-cells = <2>;
321 reg = <0x1000 0x400>;
322 resets = <&reset_ahb1 0>;
323 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
324 st,bank-name = "GPIOB";
325 gpio-ranges = <&pinctrl 0 0 16>;
326 };
327
328 gpioc: gpio@2000 {
329 gpio-controller;
330 #gpio-cells = <2>;
331 reg = <0x2000 0x400>;
332 resets = <&reset_ahb1 0>;
333 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
334 st,bank-name = "GPIOC";
335 ngpios = <5>;
336 gpio-ranges = <&pinctrl 0 16 3>,
337 <&pinctrl 14 30 2>;
338 };
339 };
340
341 //Example 3 pin groups
342 pinctrl {
343 usart1_pins_a: usart1-0 {
344 pins1 {
345 pinmux = <STM32_PINMUX('A', 9, AF7)>;
346 bias-disable;
347 drive-push-pull;
348 slew-rate = <0>;
349 };
350 pins2 {
351 pinmux = <STM32_PINMUX('A', 10, AF7)>;
352 bias-disable;
353 };
354 };
355 };
356
357 usart1 {
358 pinctrl-0 = <&usart1_pins_a>;
359 pinctrl-names = "default";
360 };
361
362 - |
363 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
364 //Example 4 skew-delay and st,io-sync
365 pinctrl: pinctrl@44240000 {
366 compatible = "st,stm32mp257-pinctrl";
367 #address-cells = <1>;
368 #size-cells = <1>;
369 ranges = <0 0x44240000 0xa0400>;
370
371 eth3_rgmii_pins_a: eth3-rgmii-0 {
372 pins1 {
373 pinmux = <STM32_PINMUX('A', 6, AF14)>;
374 st,io-sync = "data on both edges";
375 };
376 pins2 {
377 pinmux = <STM32_PINMUX('H', 2, AF14)>;
378 skew-delay-output-ps = <500>;
379 };
380 };
381 };
382
383...