tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/N1 Pin Controller
8
9maintainers:
10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
12
13properties:
14 compatible:
15 items:
16 - const: renesas,r9a06g032-pinctrl # RZ/N1D
17 - const: renesas,rzn1-pinctrl # Generic RZ/N1
18
19 reg:
20 items:
21 - description: GPIO Multiplexing Level1 Register Block
22 - description: GPIO Multiplexing Level2 Register Block
23
24 clocks:
25 maxItems: 1
26
27 clock-names:
28 const: bus
29 description:
30 The bus clock, sometimes described as pclk, for register accesses.
31
32allOf:
33 - $ref: pinctrl.yaml#
34
35required:
36 - compatible
37 - reg
38 - clocks
39 - clock-names
40
41additionalProperties:
42 anyOf:
43 - type: object
44 allOf:
45 - $ref: pincfg-node.yaml#
46 - $ref: pinmux-node.yaml#
47
48 description:
49 A pin multiplexing sub-node describes how to configure a set of (or a
50 single) pin in some desired alternate function mode.
51 A single sub-node may define several pin configurations.
52
53 properties:
54 pinmux:
55 description: |
56 Integer array representing pin number and pin multiplexing
57 configuration.
58 When a pin has to be configured in alternate function mode, use
59 this property to identify the pin by its global index, and provide
60 its alternate function configuration number along with it.
61 When multiple pins are required to be configured as part of the
62 same alternate function they shall be specified as members of the
63 same argument list of a single "pinmux" property.
64 Integers values in the "pinmux" argument list are assembled as:
65 (PIN | MUX_FUNC << 8)
66 where PIN directly corresponds to the pl_gpio pin number and
67 MUX_FUNC is one of the alternate function identifiers defined in:
68 <include/dt-bindings/pinctrl/rzn1-pinctrl.h>
69 These identifiers collapse the IO Multiplex Configuration Level 1
70 and Level 2 numbers that are detailed in the hardware reference
71 manual into a single number. The identifiers for Level 2 are simply
72 offset by 10. Additional identifiers are provided to specify the
73 MDIO source peripheral.
74
75 bias-disable: true
76 bias-pull-up:
77 description: Pull up the pin with 50 kOhm
78 bias-pull-down:
79 description: Pull down the pin with 50 kOhm
80 bias-high-impedance: true
81 drive-strength:
82 enum: [ 4, 6, 8, 12 ]
83
84 required:
85 - pinmux
86
87 additionalProperties:
88 $ref: "#/additionalProperties/anyOf/0"
89
90 - type: object
91 additionalProperties:
92 $ref: "#/additionalProperties/anyOf/0"
93
94examples:
95 - |
96 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
97 #include <dt-bindings/pinctrl/rzn1-pinctrl.h>
98 pinctrl: pinctrl@40067000 {
99 compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
100 reg = <0x40067000 0x1000>, <0x51000000 0x480>;
101 clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
102 clock-names = "bus";
103
104 /*
105 * A serial communication interface with a TX output pin and an RX
106 * input pin.
107 */
108 pins_uart0: pins_uart0 {
109 pinmux = <
110 RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */
111 RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */
112 >;
113 };
114
115 /*
116 * Set the pull-up on the RXD pin of the UART.
117 */
118 pins_uart0_alt: pins_uart0_alt {
119 pinmux = <RZN1_PINMUX(103, RZN1_FUNC_UART0_I)>;
120
121 pins_uart6_rx {
122 pinmux = <RZN1_PINMUX(104, RZN1_FUNC_UART0_I)>;
123 bias-pull-up;
124 };
125 };
126 };