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1Lantiq XWAY pinmux controller
2
3Required properties:
4- compatible: "lantiq,<chip>-pinctrl", where <chip> is:
5 "ase" (XWAY AMAZON Family)
6 "danube" (XWAY DANUBE Family)
7 "xrx100" (XWAY xRX100 Family)
8 "xrx200" (XWAY xRX200 Family)
9 "xrx300" (XWAY xRX300 Family)
10- reg: Should contain the physical address and length of the gpio/pinmux
11 register range
12
13Please refer to pinctrl-bindings.txt in this directory for details of the
14common pinctrl bindings used by client devices, including the meaning of the
15phrase "pin configuration node".
16
17Lantiq's pin configuration nodes act as a container for an arbitrary number of
18subnodes. Each of these subnodes represents some desired configuration for a
19pin, a group, or a list of pins or groups. This configuration can include the
20mux function to select on those group(s), and two pin configuration parameters:
21pull-up and open-drain
22
23The name of each subnode is not important as long as it is unique; all subnodes
24should be enumerated and processed purely based on their content.
25
26Each subnode only affects those parameters that are explicitly listed. In
27other words, a subnode that lists a mux function but no pin configuration
28parameters implies no information about any pin configuration parameters.
29Similarly, a pin subnode that describes a pullup parameter implies no
30information about e.g. the mux function.
31
32We support 2 types of nodes.
33
34Definition of mux function groups:
35
36Required subnode-properties:
37- lantiq,groups : An array of strings. Each string contains the name of a group.
38 Valid values for these names are listed below.
39- lantiq,function: A string containing the name of the function to mux to the
40 group. Valid values for function names are listed below.
41
42Valid values for group and function names:
43
44AMAZON:
45 mux groups:
46 exin0, exin1, exin2, jtag, spi_di, spi_do, spi_clk, spi_cs1, spi_cs2,
47 spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc, stp, gpt1, gpt2, gpt3, clkout0,
48 clkout1, clkout2, mdio, dfe led0, dfe led1, ephy led0, ephy led1, ephy led2
49
50 functions:
51 spi, asc, cgu, jtag, exin, stp, gpt, mdio, ephy, dfe
52
53DANUBE:
54 mux groups:
55 exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,
56 ebu wait, nand ale, nand cs1, nand cle, spi_di, spi_do, spi_clk, spi_cs1,
57 spi_cs2, spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi,
58 gpt1, gpt2, gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3,
59 req1, req2, req3, dfe led0, dfe led1
60
61 functions:
62 spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, dfe
63
64xRX100:
65 mux groups:
66 exin0, exin1, exin2, exin3, exin4, ebu a23, ebu a24, ebu a25, ebu clk,
67 ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
68 spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5,
69 spi_cs6, asc0, asc0 cts rts, stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1,
70 clkout2, clkout3, gnt1, gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio,
71 dfe led0, dfe led1
72
73 functions:
74 spi, asc, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe
75
76xRX200:
77 mux groups:
78 exin0, exin1, exin2, exin3, exin4, ebu a23, ebu a24, ebu a25, ebu clk,
79 ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
80 spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5,
81 spi_cs6, usif uart_rx, usif uart_tx, usif uart_rts, usif uart_cts,
82 usif uart_dtr, usif uart_dsr, usif uart_dcd, usif uart_ri, usif spi_di,
83 usif spi_do, usif spi_clk, usif spi_cs0, usif spi_cs1, usif spi_cs2,
84 stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1, clkout2, clkout3, gnt1,
85 gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio, dfe led0, dfe led1,
86 gphy0 led0, gphy0 led1, gphy0 led2, gphy1 led0, gphy1 led1, gphy1 led2
87
88 functions:
89 spi, usif, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe, gphy
90
91xRX300:
92 mux groups:
93 exin0, exin1, exin2, exin4, nand ale, nand cs0, nand cs1, nand cle,
94 nand rdy, nand rd, nand_d0, nand_d1, nand_d2, nand_d3, nand_d4, nand_d5,
95 nand_d6, nand_d7, nand_d1, nand wr, nand wp, nand se, spi_di, spi_do,
96 spi_clk, spi_cs1, spi_cs4, spi_cs6, usif uart_rx, usif uart_tx,
97 usif spi_di, usif spi_do, usif spi_clk, usif spi_cs0, stp, clkout2,
98 mdio, dfe led0, dfe led1, ephy0 led0, ephy0 led1, ephy1 led0, ephy1 led1
99
100 functions:
101 spi, usif, cgu, exin, stp, ebu, mdio, dfe, ephy
102
103
104Definition of pin configurations:
105
106Required subnode-properties:
107- lantiq,pins : An array of strings. Each string contains the name of a pin.
108 Valid values for these names are listed below.
109
110Optional subnode-properties:
111- lantiq,pull: Integer, representing the pull-down/up to apply to the pin.
112 0: none, 1: down, 2: up.
113- lantiq,open-drain: Boolean, enables open-drain on the defined pin.
114
115Valid values for AMAZON pin names:
116 Pinconf pins can be referenced via the names io0-io31.
117
118Valid values for DANUBE pin names:
119 Pinconf pins can be referenced via the names io0-io31.
120
121Valid values for xRX100 pin names:
122 Pinconf pins can be referenced via the names io0-io55.
123
124Valid values for xRX200 pin names:
125 Pinconf pins can be referenced via the names io0-io49.
126
127Valid values for xRX300 pin names:
128 Pinconf pins can be referenced via the names io0-io1,io3-io6,io8-io11,
129 io13-io19,io23-io27,io34-io36,
130 io42-io43,io48-io61.
131
132Example:
133 gpio: pinmux@e100b10 {
134 compatible = "lantiq,danube-pinctrl";
135 pinctrl-names = "default";
136 pinctrl-0 = <&state_default>;
137
138 #gpio-cells = <2>;
139 gpio-controller;
140 reg = <0xE100B10 0xA0>;
141
142 state_default: pinmux {
143 stp {
144 lantiq,groups = "stp";
145 lantiq,function = "stp";
146 };
147 pci {
148 lantiq,groups = "gnt1";
149 lantiq,function = "pci";
150 };
151 conf_out {
152 lantiq,pins = "io4", "io5", "io6"; /* stp */
153 lantiq,open-drain;
154 lantiq,pull = <0>;
155 };
156 };
157 };
158