tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale i.MX6 PCIe host controller
8
9maintainers:
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
12
13description: |+
14 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
15 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
16 The controller instances are dual mode where in they can work either in
17 Root Port mode or Endpoint mode but one at a time.
18
19 See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree
20 bindings.
21
22properties:
23 compatible:
24 oneOf:
25 - enum:
26 - fsl,imx6q-pcie
27 - fsl,imx6qp-pcie
28 - fsl,imx6sx-pcie
29 - fsl,imx7d-pcie
30 - fsl,imx8mm-pcie
31 - fsl,imx8mp-pcie
32 - fsl,imx8mq-pcie
33 - fsl,imx8q-pcie
34 - fsl,imx95-pcie
35 - items:
36 - enum:
37 - fsl,imx94-pcie
38 - fsl,imx943-pcie
39 - const: fsl,imx95-pcie
40
41 clocks:
42 minItems: 3
43 items:
44 - description: PCIe bridge clock.
45 - description: PCIe bus clock.
46 - description: PCIe PHY clock.
47 - description: Additional required clock entry for imx6sx-pcie,
48 imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
49 - description: PCIe internal reference clock.
50 - description: PCIe additional external reference clock.
51
52 clock-names:
53 minItems: 3
54 maxItems: 6
55
56 interrupts:
57 minItems: 1
58 items:
59 - description: builtin MSI controller.
60 - description: builtin DMA controller.
61
62 interrupt-names:
63 minItems: 1
64 items:
65 - const: msi
66 - const: dma
67
68 reset-gpio:
69 description: Should specify the GPIO for controlling the PCI bus device
70 reset signal. It's not polarity aware and defaults to active-low reset
71 sequence (L=reset state, H=operation state) (optional required).
72
73 reset-gpio-active-high:
74 description: If present then the reset sequence using the GPIO
75 specified in the "reset-gpio" property is reversed (H=reset state,
76 L=operation state) (optional required).
77 type: boolean
78
79required:
80 - compatible
81 - reg
82 - reg-names
83 - "#address-cells"
84 - "#size-cells"
85 - device_type
86 - bus-range
87 - ranges
88 - interrupts
89 - interrupt-names
90 - "#interrupt-cells"
91 - interrupt-map-mask
92 - interrupt-map
93
94allOf:
95 - $ref: /schemas/pci/snps,dw-pcie.yaml#
96 - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
97 - if:
98 properties:
99 compatible:
100 enum:
101 - fsl,imx6q-pcie
102 - fsl,imx6sx-pcie
103 - fsl,imx6qp-pcie
104 - fsl,imx7d-pcie
105 - fsl,imx8mq-pcie
106 - fsl,imx8mm-pcie
107 - fsl,imx8mp-pcie
108 then:
109 properties:
110 reg:
111 maxItems: 2
112 reg-names:
113 items:
114 - const: dbi
115 - const: config
116
117 - if:
118 properties:
119 compatible:
120 enum:
121 - fsl,imx95-pcie
122 then:
123 properties:
124 reg:
125 minItems: 4
126 maxItems: 4
127 reg-names:
128 items:
129 - const: dbi
130 - const: config
131 - const: atu
132 - const: app
133
134 - if:
135 properties:
136 compatible:
137 enum:
138 - fsl,imx6sx-pcie
139 then:
140 properties:
141 clocks:
142 maxItems: 4
143 clock-names:
144 items:
145 - const: pcie
146 - const: pcie_bus
147 - const: pcie_phy
148 - const: pcie_inbound_axi
149
150 - if:
151 properties:
152 compatible:
153 enum:
154 - fsl,imx8mq-pcie
155 then:
156 properties:
157 clocks:
158 maxItems: 4
159 clock-names:
160 items:
161 - const: pcie
162 - const: pcie_bus
163 - const: pcie_phy
164 - const: pcie_aux
165
166 - if:
167 properties:
168 compatible:
169 enum:
170 - fsl,imx6q-pcie
171 - fsl,imx6qp-pcie
172 - fsl,imx7d-pcie
173 then:
174 properties:
175 clocks:
176 maxItems: 3
177 clock-names:
178 items:
179 - const: pcie
180 - const: pcie_bus
181 - const: pcie_phy
182
183 - if:
184 properties:
185 compatible:
186 enum:
187 - fsl,imx8mm-pcie
188 - fsl,imx8mp-pcie
189 then:
190 properties:
191 clocks:
192 maxItems: 3
193 clock-names:
194 items:
195 - const: pcie
196 - const: pcie_bus
197 - const: pcie_aux
198
199 - if:
200 properties:
201 compatible:
202 enum:
203 - fsl,imx8q-pcie
204 then:
205 properties:
206 clocks:
207 maxItems: 3
208 clock-names:
209 items:
210 - const: dbi
211 - const: mstr
212 - const: slv
213
214 - if:
215 properties:
216 compatible:
217 enum:
218 - fsl,imx95-pcie
219 then:
220 properties:
221 clocks:
222 minItems: 5
223 maxItems: 6
224 clock-names:
225 minItems: 5
226 items:
227 - const: pcie
228 - const: pcie_bus
229 - const: pcie_phy
230 - const: pcie_aux
231 - const: ref
232 - const: extref # Optional
233
234unevaluatedProperties: false
235
236examples:
237 - |
238 #include <dt-bindings/clock/imx6qdl-clock.h>
239 #include <dt-bindings/interrupt-controller/arm-gic.h>
240
241 pcie: pcie@1ffc000 {
242 compatible = "fsl,imx6q-pcie";
243 reg = <0x01ffc000 0x04000>,
244 <0x01f00000 0x80000>;
245 reg-names = "dbi", "config";
246 #address-cells = <3>;
247 #size-cells = <2>;
248 device_type = "pci";
249 bus-range = <0x00 0xff>;
250 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>,
251 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
252 num-lanes = <1>;
253 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
254 interrupt-names = "msi";
255 #interrupt-cells = <1>;
256 interrupt-map-mask = <0 0 0 0x7>;
257 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
258 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
259 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
260 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
261 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
262 <&clks IMX6QDL_CLK_LVDS1_GATE>,
263 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
264 clock-names = "pcie", "pcie_bus", "pcie_phy";
265 };
266...