tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MTK MSDC Storage Host Controller
8
9maintainers:
10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbin Mei <wenbin.mei@mediatek.com>
12
13properties:
14 compatible:
15 oneOf:
16 - enum:
17 - mediatek,mt2701-mmc
18 - mediatek,mt2712-mmc
19 - mediatek,mt6779-mmc
20 - mediatek,mt6795-mmc
21 - mediatek,mt7620-mmc
22 - mediatek,mt7622-mmc
23 - mediatek,mt7986-mmc
24 - mediatek,mt7988-mmc
25 - mediatek,mt8135-mmc
26 - mediatek,mt8173-mmc
27 - mediatek,mt8183-mmc
28 - mediatek,mt8189-mmc
29 - mediatek,mt8196-mmc
30 - mediatek,mt8516-mmc
31 - items:
32 - const: mediatek,mt7623-mmc
33 - const: mediatek,mt2701-mmc
34 - items:
35 - enum:
36 - mediatek,mt6893-mmc
37 - mediatek,mt8186-mmc
38 - mediatek,mt8188-mmc
39 - mediatek,mt8192-mmc
40 - mediatek,mt8195-mmc
41 - mediatek,mt8365-mmc
42 - const: mediatek,mt8183-mmc
43
44 reg:
45 minItems: 1
46 items:
47 - description: base register (required).
48 - description: top base register (required for MT8183).
49
50 clocks:
51 description:
52 Should contain phandle for the clock feeding the MMC controller.
53 minItems: 2
54 maxItems: 7
55
56 clock-names:
57 minItems: 2
58 maxItems: 7
59
60 interrupts:
61 description:
62 Should at least contain MSDC GIC interrupt. To support SDIO in-band wakeup, an extended
63 interrupt is required and be configured as wakeup source irq.
64 minItems: 1
65 maxItems: 2
66
67 interrupt-names:
68 items:
69 - const: msdc
70 - const: sdio_wakeup
71
72 pinctrl-names:
73 description:
74 Should at least contain default and state_uhs. To support SDIO in-band wakeup, dat1 pin
75 will be switched between GPIO mode and SDIO DAT1 mode, state_eint is mandatory in this
76 scenario.
77 minItems: 2
78 items:
79 - const: default
80 - const: state_uhs
81 - const: state_eint
82
83 pinctrl-0:
84 description:
85 should contain default/high speed pin ctrl.
86 maxItems: 1
87
88 pinctrl-1:
89 description:
90 should contain uhs mode pin ctrl.
91 maxItems: 1
92
93 pinctrl-2:
94 description:
95 should switch dat1 pin to GPIO mode.
96 maxItems: 1
97
98 hs400-ds-delay:
99 $ref: /schemas/types.yaml#/definitions/uint32
100 description:
101 HS400 DS delay setting.
102 minimum: 0
103 maximum: 0xffffffff
104
105 mediatek,hs200-cmd-int-delay:
106 $ref: /schemas/types.yaml#/definitions/uint32
107 description:
108 HS200 command internal delay setting.
109 This field has total 32 stages.
110 The value is an integer from 0 to 31.
111 minimum: 0
112 maximum: 31
113
114 mediatek,hs400-cmd-int-delay:
115 $ref: /schemas/types.yaml#/definitions/uint32
116 description:
117 HS400 command internal delay setting.
118 This field has total 32 stages.
119 The value is an integer from 0 to 31.
120 minimum: 0
121 maximum: 31
122
123 mediatek,hs400-cmd-resp-sel-rising:
124 $ref: /schemas/types.yaml#/definitions/flag
125 description:
126 HS400 command response sample selection.
127 If present, HS400 command responses are sampled on rising edges.
128 If not present, HS400 command responses are sampled on falling edges.
129
130 mediatek,hs400-ds-dly3:
131 $ref: /schemas/types.yaml#/definitions/uint32
132 description:
133 Gear of the third delay line for DS for input data latch in data
134 pad macro, there are 32 stages from 0 to 31.
135 For different corner IC, the time is different about one step, it is
136 about 100ps.
137 The value is confirmed by doing scan and calibration to find a best
138 value with corner IC and it is valid only for HS400 mode.
139 minimum: 0
140 maximum: 31
141
142 mediatek,latch-ck:
143 $ref: /schemas/types.yaml#/definitions/uint32
144 description:
145 Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
146 data crc error caused by stop clock(fifo full) Valid range = [0:0x7].
147 if not present, default value is 0.
148 applied to compatible "mediatek,mt2701-mmc".
149 minimum: 0
150 maximum: 7
151
152 mediatek,tuning-step:
153 $ref: /schemas/types.yaml#/definitions/uint32
154 description:
155 Some SoCs need extend tuning step for better delay value to avoid CRC issue.
156 If not present, default tuning step is 32. For eMMC and SD, this can yield
157 satisfactory calibration results in most cases.
158 enum: [32, 64]
159 default: 32
160
161 resets:
162 maxItems: 1
163
164 reset-names:
165 const: hrst
166
167required:
168 - compatible
169 - reg
170 - interrupts
171 - clocks
172 - clock-names
173 - pinctrl-names
174 - pinctrl-0
175 - pinctrl-1
176 - vmmc-supply
177 - vqmmc-supply
178
179allOf:
180 - $ref: mmc-controller.yaml#
181 - if:
182 properties:
183 compatible:
184 enum:
185 - mediatek,mt2701-mmc
186 - mediatek,mt6779-mmc
187 - mediatek,mt6795-mmc
188 - mediatek,mt7620-mmc
189 - mediatek,mt7622-mmc
190 - mediatek,mt7623-mmc
191 - mediatek,mt8135-mmc
192 - mediatek,mt8173-mmc
193 - mediatek,mt8183-mmc
194 - mediatek,mt8186-mmc
195 - mediatek,mt8188-mmc
196 - mediatek,mt8189-mmc
197 - mediatek,mt8195-mmc
198 - mediatek,mt8196-mmc
199 - mediatek,mt8516-mmc
200 then:
201 properties:
202 clocks:
203 minItems: 2
204 items:
205 - description: source clock
206 - description: HCLK which used for host
207 - description: independent source clock gate
208 clock-names:
209 minItems: 2
210 items:
211 - const: source
212 - const: hclk
213 - const: source_cg
214
215 - if:
216 properties:
217 compatible:
218 contains:
219 const: mediatek,mt2712-mmc
220 then:
221 properties:
222 clocks:
223 minItems: 3
224 items:
225 - description: source clock
226 - description: HCLK which used for host
227 - description: independent source clock gate
228 - description: bus clock used for internal register access (required for MSDC0/3).
229 clock-names:
230 minItems: 3
231 items:
232 - const: source
233 - const: hclk
234 - const: source_cg
235 - const: bus_clk
236
237 - if:
238 properties:
239 compatible:
240 contains:
241 enum:
242 - mediatek,mt7986-mmc
243 - mediatek,mt7988-mmc
244 - mediatek,mt8183-mmc
245 - mediatek,mt8189-mmc
246 - mediatek,mt8196-mmc
247 then:
248 properties:
249 reg:
250 minItems: 2
251 else:
252 properties:
253 reg:
254 maxItems: 1
255
256 - if:
257 properties:
258 compatible:
259 contains:
260 enum:
261 - mediatek,mt7986-mmc
262 then:
263 properties:
264 clocks:
265 minItems: 3
266 items:
267 - description: source clock
268 - description: HCLK which used for host
269 - description: independent source clock gate
270 - description: bus clock used for internal register access (required for MSDC0/3).
271 - description: msdc subsys clock gate
272 clock-names:
273 minItems: 3
274 items:
275 - const: source
276 - const: hclk
277 - const: source_cg
278 - const: bus_clk
279 - const: sys_cg
280
281 - if:
282 properties:
283 compatible:
284 contains:
285 enum:
286 - mediatek,mt7988-mmc
287 then:
288 properties:
289 clocks:
290 items:
291 - description: source clock
292 - description: HCLK which used for host
293 - description: Advanced eXtensible Interface
294 - description: Advanced High-performance Bus clock
295 clock-names:
296 items:
297 - const: source
298 - const: hclk
299 - const: axi_cg
300 - const: ahb_cg
301
302 - if:
303 properties:
304 compatible:
305 enum:
306 - mediatek,mt6893-mmc
307 - mediatek,mt8186-mmc
308 - mediatek,mt8188-mmc
309 - mediatek,mt8195-mmc
310 then:
311 properties:
312 clocks:
313 items:
314 - description: source clock
315 - description: HCLK which used for host
316 - description: independent source clock gate
317 - description: crypto clock used for data encrypt/decrypt (optional)
318 clock-names:
319 items:
320 - const: source
321 - const: hclk
322 - const: source_cg
323 - const: crypto
324
325 - if:
326 properties:
327 compatible:
328 contains:
329 const: mediatek,mt8192-mmc
330 then:
331 properties:
332 clocks:
333 items:
334 - description: source clock
335 - description: HCLK which used for host
336 - description: independent source clock gate
337 - description: msdc subsys clock gate
338 - description: peripheral bus clock gate
339 - description: AXI bus clock gate
340 - description: AHB bus clock gate
341 clock-names:
342 items:
343 - const: source
344 - const: hclk
345 - const: source_cg
346 - const: sys_cg
347 - const: pclk_cg
348 - const: axi_cg
349 - const: ahb_cg
350
351unevaluatedProperties: false
352
353examples:
354 - |
355 #include <dt-bindings/interrupt-controller/irq.h>
356 #include <dt-bindings/interrupt-controller/arm-gic.h>
357 #include <dt-bindings/clock/mt8173-clk.h>
358 mmc0: mmc@11230000 {
359 compatible = "mediatek,mt8173-mmc";
360 reg = <0x11230000 0x1000>;
361 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
362 vmmc-supply = <&mt6397_vemc_3v3_reg>;
363 vqmmc-supply = <&mt6397_vio18_reg>;
364 clocks = <&pericfg CLK_PERI_MSDC30_0>,
365 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
366 clock-names = "source", "hclk";
367 pinctrl-names = "default", "state_uhs";
368 pinctrl-0 = <&mmc0_pins_default>;
369 pinctrl-1 = <&mmc0_pins_uhs>;
370 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
371 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
372 hs400-ds-delay = <0x14015>;
373 mediatek,hs200-cmd-int-delay = <26>;
374 mediatek,hs400-cmd-int-delay = <14>;
375 mediatek,hs400-cmd-resp-sel-rising;
376 };
377
378 mmc3: mmc@11260000 {
379 compatible = "mediatek,mt8173-mmc";
380 reg = <0x11260000 0x1000>;
381 clock-names = "source", "hclk";
382 clocks = <&pericfg CLK_PERI_MSDC30_3>,
383 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
384 interrupt-names = "msdc", "sdio_wakeup";
385 interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_LOW 0>,
386 <&pio 23 IRQ_TYPE_LEVEL_LOW>;
387 pinctrl-names = "default", "state_uhs", "state_eint";
388 pinctrl-0 = <&mmc2_pins_default>;
389 pinctrl-1 = <&mmc2_pins_uhs>;
390 pinctrl-2 = <&mmc2_pins_eint>;
391 bus-width = <4>;
392 max-frequency = <200000000>;
393 cap-sd-highspeed;
394 sd-uhs-sdr104;
395 keep-power-in-suspend;
396 wakeup-source;
397 cap-sdio-irq;
398 no-mmc;
399 no-sd;
400 non-removable;
401 vmmc-supply = <&sdio_fixed_3v3>;
402 vqmmc-supply = <&mt6397_vgp3_reg>;
403 mmc-pwrseq = <&wifi_pwrseq>;
404 };
405
406...