tjh.dev
Linux kernel mirror (for testing)
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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/rockchip,rk3568-vicap.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip RK3568 Video Capture (VICAP)
8
9maintainers:
10 - Michael Riesch <michael.riesch@collabora.com>
11
12description:
13 The Rockchip RK3568 Video Capture (VICAP) block features a digital video
14 port (DVP, a parallel video interface) and a MIPI CSI-2 port. It receives
15 the data from camera sensors, video decoders, or other companion ICs and
16 transfers it into system main memory by AXI bus.
17
18properties:
19 compatible:
20 const: rockchip,rk3568-vicap
21
22 reg:
23 maxItems: 1
24
25 interrupts:
26 maxItems: 1
27
28 clocks:
29 items:
30 - description: ACLK
31 - description: HCLK
32 - description: DCLK
33 - description: ICLK
34
35 clock-names:
36 items:
37 - const: aclk
38 - const: hclk
39 - const: dclk
40 - const: iclk
41
42 iommus:
43 maxItems: 1
44
45 resets:
46 items:
47 - description: ARST
48 - description: HRST
49 - description: DRST
50 - description: PRST
51 - description: IRST
52
53 reset-names:
54 items:
55 - const: arst
56 - const: hrst
57 - const: drst
58 - const: prst
59 - const: irst
60
61 rockchip,grf:
62 $ref: /schemas/types.yaml#/definitions/phandle
63 description: Phandle to general register file used for video input block control.
64
65 power-domains:
66 maxItems: 1
67
68 ports:
69 $ref: /schemas/graph.yaml#/properties/ports
70
71 properties:
72 port@0:
73 $ref: /schemas/graph.yaml#/$defs/port-base
74 unevaluatedProperties: false
75 description: The digital video port (DVP, a parallel video interface).
76
77 properties:
78 endpoint:
79 $ref: video-interfaces.yaml#
80 unevaluatedProperties: false
81
82 properties:
83 bus-type:
84 enum:
85 - 5 # MEDIA_BUS_TYPE_PARALLEL
86 - 6 # MEDIA_BUS_TYPE_BT656
87
88 rockchip,dvp-clk-delay:
89 $ref: /schemas/types.yaml#/definitions/uint32
90 default: 0
91 minimum: 0
92 maximum: 127
93 description:
94 Delay the DVP path clock input to align the sampling phase,
95 only valid in dual edge sampling mode. Delay is zero by
96 default and can be adjusted optionally.
97
98 required:
99 - bus-type
100
101 port@1:
102 $ref: /schemas/graph.yaml#/properties/port
103 description: Port connected to the MIPI CSI-2 receiver output.
104
105 properties:
106 endpoint:
107 $ref: video-interfaces.yaml#
108 unevaluatedProperties: false
109
110required:
111 - compatible
112 - reg
113 - interrupts
114 - clocks
115 - ports
116
117additionalProperties: false
118
119examples:
120 - |
121 #include <dt-bindings/clock/rk3568-cru.h>
122 #include <dt-bindings/interrupt-controller/arm-gic.h>
123 #include <dt-bindings/interrupt-controller/irq.h>
124 #include <dt-bindings/power/rk3568-power.h>
125 #include <dt-bindings/media/video-interfaces.h>
126
127 soc {
128 #address-cells = <2>;
129 #size-cells = <2>;
130
131 vicap: video-capture@fdfe0000 {
132 compatible = "rockchip,rk3568-vicap";
133 reg = <0x0 0xfdfe0000 0x0 0x200>;
134 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
135 assigned-clocks = <&cru DCLK_VICAP>;
136 assigned-clock-rates = <300000000>;
137 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>,
138 <&cru DCLK_VICAP>, <&cru ICLK_VICAP_G>;
139 clock-names = "aclk", "hclk", "dclk", "iclk";
140 iommus = <&vicap_mmu>;
141 power-domains = <&power RK3568_PD_VI>;
142 resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>,
143 <&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>,
144 <&cru SRST_I_VICAP>;
145 reset-names = "arst", "hrst", "drst", "prst", "irst";
146 rockchip,grf = <&grf>;
147
148 ports {
149 #address-cells = <1>;
150 #size-cells = <0>;
151
152 vicap_dvp: port@0 {
153 reg = <0>;
154
155 vicap_dvp_input: endpoint {
156 bus-type = <MEDIA_BUS_TYPE_BT656>;
157 bus-width = <16>;
158 pclk-sample = <MEDIA_PCLK_SAMPLE_DUAL_EDGE>;
159 remote-endpoint = <&it6801_output>;
160 };
161 };
162
163 vicap_mipi: port@1 {
164 reg = <1>;
165
166 vicap_mipi_input: endpoint {
167 remote-endpoint = <&csi_output>;
168 };
169 };
170 };
171 };
172 };