tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7maintainers:
8 - Thierry Reding <thierry.reding@gmail.com>
9 - Jon Hunter <jonathanh@nvidia.com>
10
11title: NVIDIA Tegra I2C controller driver
12
13properties:
14 compatible:
15 oneOf:
16 - description: Tegra20 has 4 generic I2C controller. This can support
17 master and slave mode of I2C communication. The i2c-tegra driver
18 only support master mode of I2C communication. Driver of I2C
19 controller is only compatible with "nvidia,tegra20-i2c".
20 const: nvidia,tegra20-i2c
21 - description: Tegra20 has specific I2C controller called as DVC I2C
22 controller. This only support master mode of I2C communication.
23 Register interface/offset and interrupts handling are different than
24 generic I2C controller. Driver of DVC I2C controller is only
25 compatible with "nvidia,tegra20-i2c-dvc".
26 const: nvidia,tegra20-i2c-dvc
27 - description: |
28 Tegra30 has 5 generic I2C controller. This controller is very much
29 similar to Tegra20 I2C controller with additional feature: Continue
30 Transfer Support. This feature helps to implement M_NO_START as per
31 I2C core API transfer flags. Driver of I2C controller is compatible
32 with "nvidia,tegra30-i2c" to enable the continue transfer support.
33 This is also compatible with "nvidia,tegra20-i2c" without continue
34 transfer support.
35 items:
36 - const: nvidia,tegra30-i2c
37 - const: nvidia,tegra20-i2c
38 - description: |
39 Tegra114 has 5 generic I2C controllers. This controller is very much
40 similar to Tegra30 I2C controller with some hardware modification:
41 - Tegra30/Tegra20 I2C controller has 2 clock source called div-clk
42 and fast-clk. Tegra114 has only one clock source called as
43 div-clk and hence clock mechanism is changed in I2C controller.
44 - Tegra30/Tegra20 I2C controller has enabled per packet transfer
45 by default and there is no way to disable it. Tegra114 has this
46 interrupt disable by default and SW need to enable explicitly.
47 Due to above changes, Tegra114 I2C driver makes incompatible with
48 previous hardware driver. Hence, Tegra114 I2C controller is
49 compatible with "nvidia,tegra114-i2c".
50 const: nvidia,tegra114-i2c
51 - description: |
52 Tegra124 has 6 generic I2C controllers. These controllers are very
53 similar to those found on Tegra114 but also contain several hardware
54 improvements and new registers.
55 const: nvidia,tegra124-i2c
56 - description: |
57 Tegra210 has 6 generic I2C controllers. These controllers are very
58 similar to those found on Tegra124.
59 items:
60 - const: nvidia,tegra210-i2c
61 - const: nvidia,tegra124-i2c
62 - description: |
63 Tegra210 has one I2C controller that is on host1x bus and is part of
64 the VE power domain and typically used for camera use-cases. This VI
65 I2C controller is mostly compatible with the programming model of
66 the regular I2C controllers with a few exceptions. The I2C registers
67 start at an offset of 0xc00 (instead of 0), registers are 16 bytes
68 apart (rather than 4) and the controller does not support slave
69 mode.
70 const: nvidia,tegra210-i2c-vi
71 - description: |
72 Tegra186 has 9 generic I2C controllers, two of which are in the AON
73 (always-on) partition of the SoC. All of these controllers are very
74 similar to those found on Tegra210.
75 const: nvidia,tegra186-i2c
76 - description: |
77 Tegra194 has 8 generic I2C controllers, two of which are in the AON
78 (always-on) partition of the SoC. All of these controllers are very
79 similar to those found on Tegra186. However, these controllers have
80 support for 64 KiB transactions whereas earlier chips supported no
81 more than 4 KiB per transactions.
82 const: nvidia,tegra194-i2c
83 - description: |
84 Tegra256 has 8 generic I2C controllers. The controllers are similar to
85 the previous generations, but have a different parent clock and hence
86 the timing parameters are configured differently.
87 const: nvidia,tegra256-i2c
88 - description:
89 Tegra264 has 17 generic I2C controllers, two of which are in the AON
90 (always-on) partition of the SoC. In addition to the features from
91 Tegra194, a SW mutex register is added to support use of the same I2C
92 instance across multiple firmwares.
93 const: nvidia,tegra264-i2c
94
95 reg:
96 maxItems: 1
97
98 interrupts:
99 maxItems: 1
100
101 clocks:
102 minItems: 1
103 maxItems: 2
104
105 clock-names:
106 minItems: 1
107 maxItems: 2
108
109 resets:
110 items:
111 - description:
112 Module reset. This property is optional for controllers in Tegra194,
113 Tegra234 etc where an internal software reset is available as an
114 alternative.
115
116 reset-names:
117 items:
118 - const: i2c
119
120 power-domains:
121 maxItems: 1
122
123 dmas:
124 items:
125 - description: DMA channel for the reception FIFO
126 - description: DMA channel for the transmission FIFO
127
128 dma-names:
129 items:
130 - const: rx
131 - const: tx
132
133required:
134 - compatible
135 - reg
136 - interrupts
137 - clocks
138 - clock-names
139
140allOf:
141 - $ref: /schemas/i2c/i2c-controller.yaml
142 - if:
143 properties:
144 compatible:
145 contains:
146 enum:
147 - nvidia,tegra20-i2c
148 - nvidia,tegra30-i2c
149 then:
150 properties:
151 clocks:
152 minItems: 2
153 clock-names:
154 items:
155 - const: div-clk
156 - const: fast-clk
157
158 - if:
159 properties:
160 compatible:
161 contains:
162 enum:
163 - nvidia,tegra114-i2c
164 - nvidia,tegra210-i2c
165 then:
166 properties:
167 clocks:
168 maxItems: 1
169 clock-names:
170 items:
171 - const: div-clk
172
173 - if:
174 properties:
175 compatible:
176 contains:
177 const: nvidia,tegra210-i2c-vi
178 then:
179 properties:
180 clocks:
181 minItems: 2
182 clock-names:
183 items:
184 - const: div-clk
185 - const: slow
186 power-domains:
187 items:
188 - description: phandle to the VENC power domain
189 else:
190 properties:
191 power-domains: false
192
193 - if:
194 not:
195 properties:
196 compatible:
197 contains:
198 enum:
199 - nvidia,tegra194-i2c
200 - nvidia,tegra256-i2c
201 - nvidia,tegra264-i2c
202 then:
203 required:
204 - resets
205 - reset-names
206
207unevaluatedProperties: false
208
209examples:
210 - |
211 i2c@7000c000 {
212 compatible = "nvidia,tegra20-i2c";
213 reg = <0x7000c000 0x100>;
214 interrupts = <0 38 0x04>;
215 clocks = <&tegra_car 12>, <&tegra_car 124>;
216 clock-names = "div-clk", "fast-clk";
217 resets = <&tegra_car 12>;
218 reset-names = "i2c";
219 dmas = <&apbdma 16>, <&apbdma 16>;
220 dma-names = "rx", "tx";
221
222 #address-cells = <1>;
223 #size-cells = <0>;
224 };