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1# SPDX-License-Identifier: GPL-2.0-only
2# Copyright 2019-2020, The Linux Foundation, All Rights Reserved
3%YAML 1.2
4---
5
6$id: http://devicetree.org/schemas/display/msm/gmu.yaml#
7$schema: http://devicetree.org/meta-schemas/core.yaml#
8
9title: GMU attached to certain Adreno GPUs
10
11maintainers:
12 - Rob Clark <robdclark@gmail.com>
13
14description: |
15 These bindings describe the Graphics Management Unit (GMU) that is attached
16 to members of the Adreno A6xx GPU family. The GMU provides on-device power
17 management and support to improve power efficiency and reduce the load on
18 the CPU.
19
20properties:
21 compatible:
22 oneOf:
23 - items:
24 - pattern: '^qcom,adreno-gmu-[6-8][0-9][0-9]\.[0-9]$'
25 - const: qcom,adreno-gmu
26 - items:
27 - pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$'
28 - const: qcom,adreno-gmu
29 - const: qcom,adreno-gmu-wrapper
30
31 reg:
32 minItems: 1
33 maxItems: 4
34
35 reg-names:
36 minItems: 1
37 maxItems: 4
38
39 clocks:
40 minItems: 4
41 maxItems: 7
42
43 clock-names:
44 minItems: 4
45 maxItems: 7
46
47 interrupts:
48 items:
49 - description: GMU HFI interrupt
50 - description: GMU interrupt
51
52 interrupt-names:
53 items:
54 - const: hfi
55 - const: gmu
56
57 power-domains:
58 items:
59 - description: CX power domain
60 - description: GX power domain
61
62 power-domain-names:
63 items:
64 - const: cx
65 - const: gx
66
67 iommus:
68 maxItems: 1
69
70 qcom,qmp:
71 $ref: /schemas/types.yaml#/definitions/phandle
72 description: Reference to the AOSS side-channel message RAM
73
74 operating-points-v2: true
75
76 opp-table:
77 type: object
78
79required:
80 - compatible
81 - reg
82 - reg-names
83 - power-domains
84 - power-domain-names
85
86additionalProperties: false
87
88allOf:
89 - if:
90 properties:
91 compatible:
92 contains:
93 enum:
94 - qcom,adreno-gmu-615.0
95 - qcom,adreno-gmu-618.0
96 - qcom,adreno-gmu-630.2
97 then:
98 properties:
99 reg:
100 items:
101 - description: Core GMU registers
102 - description: GMU PDC registers
103 - description: GMU PDC sequence registers
104 reg-names:
105 items:
106 - const: gmu
107 - const: gmu_pdc
108 - const: gmu_pdc_seq
109 clocks:
110 items:
111 - description: GMU clock
112 - description: GPU CX clock
113 - description: GPU AXI clock
114 - description: GPU MEMNOC clock
115 clock-names:
116 items:
117 - const: gmu
118 - const: cxo
119 - const: axi
120 - const: memnoc
121
122 - if:
123 properties:
124 compatible:
125 contains:
126 enum:
127 - qcom,adreno-gmu-623.0
128 then:
129 properties:
130 reg:
131 items:
132 - description: Core GMU registers
133 - description: Resource controller registers
134 - description: GMU PDC registers
135 reg-names:
136 items:
137 - const: gmu
138 - const: rscc
139 - const: gmu_pdc
140 clocks:
141 items:
142 - description: GMU clock
143 - description: GPU CX clock
144 - description: GPU AXI clock
145 - description: GPU MEMNOC clock
146 - description: GPU AHB clock
147 - description: GPU HUB CX clock
148 clock-names:
149 items:
150 - const: gmu
151 - const: cxo
152 - const: axi
153 - const: memnoc
154 - const: ahb
155 - const: hub
156
157 - if:
158 properties:
159 compatible:
160 contains:
161 enum:
162 - qcom,adreno-gmu-635.0
163 - qcom,adreno-gmu-660.1
164 - qcom,adreno-gmu-663.0
165 then:
166 properties:
167 reg:
168 items:
169 - description: Core GMU registers
170 - description: Resource controller registers
171 - description: GMU PDC registers
172 reg-names:
173 items:
174 - const: gmu
175 - const: rscc
176 - const: gmu_pdc
177 clocks:
178 items:
179 - description: GMU clock
180 - description: GPU CX clock
181 - description: GPU AXI clock
182 - description: GPU MEMNOC clock
183 - description: GPU AHB clock
184 - description: GPU HUB CX clock
185 - description: GPU SMMU vote clock
186 clock-names:
187 items:
188 - const: gmu
189 - const: cxo
190 - const: axi
191 - const: memnoc
192 - const: ahb
193 - const: hub
194 - const: smmu_vote
195
196 - if:
197 properties:
198 compatible:
199 contains:
200 enum:
201 - qcom,adreno-gmu-640.1
202 then:
203 properties:
204 reg:
205 items:
206 - description: Core GMU registers
207 - description: GMU PDC registers
208 - description: GMU PDC sequence registers
209 reg-names:
210 items:
211 - const: gmu
212 - const: gmu_pdc
213 - const: gmu_pdc_seq
214
215 - if:
216 properties:
217 compatible:
218 contains:
219 enum:
220 - qcom,adreno-gmu-650.2
221 then:
222 properties:
223 reg:
224 items:
225 - description: Core GMU registers
226 - description: Resource controller registers
227 - description: GMU PDC registers
228 - description: GMU PDC sequence registers
229 reg-names:
230 items:
231 - const: gmu
232 - const: rscc
233 - const: gmu_pdc
234 - const: gmu_pdc_seq
235
236 - if:
237 properties:
238 compatible:
239 contains:
240 enum:
241 - qcom,adreno-gmu-640.1
242 - qcom,adreno-gmu-650.2
243 then:
244 properties:
245 clocks:
246 items:
247 - description: GPU AHB clock
248 - description: GMU clock
249 - description: GPU CX clock
250 - description: GPU AXI clock
251 - description: GPU MEMNOC clock
252 clock-names:
253 items:
254 - const: ahb
255 - const: gmu
256 - const: cxo
257 - const: axi
258 - const: memnoc
259
260 - if:
261 properties:
262 compatible:
263 contains:
264 enum:
265 - qcom,adreno-gmu-730.1
266 - qcom,adreno-gmu-740.1
267 - qcom,adreno-gmu-750.1
268 - qcom,adreno-gmu-x185.1
269 then:
270 properties:
271 reg:
272 items:
273 - description: Core GMU registers
274 - description: Resource controller registers
275 - description: GMU PDC registers
276 reg-names:
277 items:
278 - const: gmu
279 - const: rscc
280 - const: gmu_pdc
281 clocks:
282 items:
283 - description: GPU AHB clock
284 - description: GMU clock
285 - description: GPU CX clock
286 - description: GPU AXI clock
287 - description: GPU MEMNOC clock
288 - description: GMU HUB clock
289 - description: GPUSS DEMET clock
290 clock-names:
291 items:
292 - const: ahb
293 - const: gmu
294 - const: cxo
295 - const: axi
296 - const: memnoc
297 - const: hub
298 - const: demet
299
300 required:
301 - qcom,qmp
302
303 - if:
304 properties:
305 compatible:
306 contains:
307 const: qcom,adreno-gmu-840.1
308 then:
309 properties:
310 reg:
311 items:
312 - description: Core GMU registers
313 reg-names:
314 items:
315 - const: gmu
316 clocks:
317 items:
318 - description: GPU AHB clock
319 - description: GMU clock
320 - description: GPU CX clock
321 - description: GPU MEMNOC clock
322 - description: GMU HUB clock
323 clock-names:
324 items:
325 - const: ahb
326 - const: gmu
327 - const: cxo
328 - const: memnoc
329 - const: hub
330
331 - if:
332 properties:
333 compatible:
334 contains:
335 const: qcom,adreno-gmu-x285.1
336 then:
337 properties:
338 reg:
339 items:
340 - description: Core GMU registers
341 reg-names:
342 items:
343 - const: gmu
344 clocks:
345 items:
346 - description: GPU AHB clock
347 - description: GMU clock
348 - description: GPU CX clock
349 - description: GPU MEMNOC clock
350 - description: GMU HUB clock
351 - description: GMU RSCC HUB clock
352 clock-names:
353 items:
354 - const: ahb
355 - const: gmu
356 - const: cxo
357 - const: memnoc
358 - const: hub
359 - const: rscc
360
361 - if:
362 properties:
363 compatible:
364 contains:
365 const: qcom,adreno-gmu-wrapper
366 then:
367 properties:
368 reg:
369 items:
370 - description: GMU wrapper register space
371 reg-names:
372 items:
373 - const: gmu
374 else:
375 required:
376 - clocks
377 - clock-names
378 - interrupts
379 - interrupt-names
380 - iommus
381 - operating-points-v2
382
383examples:
384 - |
385 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
386 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
387 #include <dt-bindings/interrupt-controller/irq.h>
388 #include <dt-bindings/interrupt-controller/arm-gic.h>
389
390 gmu: gmu@506a000 {
391 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
392
393 reg = <0x506a000 0x30000>,
394 <0xb280000 0x10000>,
395 <0xb480000 0x10000>;
396 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
397
398 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
399 <&gpucc GPU_CC_CXO_CLK>,
400 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
401 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
402 clock-names = "gmu", "cxo", "axi", "memnoc";
403
404 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
406 interrupt-names = "hfi", "gmu";
407
408 power-domains = <&gpucc GPU_CX_GDSC>,
409 <&gpucc GPU_GX_GDSC>;
410 power-domain-names = "cx", "gx";
411
412 iommus = <&adreno_smmu 5>;
413 operating-points-v2 = <&gmu_opp_table>;
414 };
415
416 gmu_wrapper: gmu@596a000 {
417 compatible = "qcom,adreno-gmu-wrapper";
418 reg = <0x0596a000 0x30000>;
419 reg-names = "gmu";
420 power-domains = <&gpucc GPU_CX_GDSC>,
421 <&gpucc GPU_GX_GDSC>;
422 power-domain-names = "cx", "gx";
423 };