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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/silabs,si5341.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Silicon Labs Si5340/1/2/4/5 programmable i2c clock generator
8
9maintainers:
10 - Mike Looijmans <mike.looijmans@topic.nl>
11
12description: >
13 Silicon Labs Si5340, Si5341 Si5342, Si5344 and Si5345 programmable i2c clock
14 generator.
15
16 Reference
17 [1] Si5341 Data Sheet
18 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
19 [2] Si5341 Reference Manual
20 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
21 [3] Si5345 Reference Manual
22 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
23
24 The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
25 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
26 in turn can be directed to any of the 10 (or 4) outputs through a divider.
27 The internal structure of the clock generators can be found in [2].
28 The Si5345 is similar to the Si5341 with the addition of fractional input
29 dividers and automatic input selection, as described in [3].
30 The Si5342 and Si5344 are smaller versions of the Si5345, with 2 or 4 outputs.
31
32 The driver can be used in "as is" mode, reading the current settings from the
33 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
34 configured when the driver probes, it assumes the driver must fully initialize
35 it.
36
37 The device type, speed grade and revision are determined runtime by probing.
38
39properties:
40 compatible:
41 enum:
42 - silabs,si5340
43 - silabs,si5341
44 - silabs,si5342
45 - silabs,si5344
46 - silabs,si5345
47
48 reg:
49 maxItems: 1
50
51 "#clock-cells":
52 const: 2
53 description: >
54 The first value is "0" for outputs, "1" for synthesizers.
55
56 The second value is the output or synthesizer index.
57
58 "#address-cells":
59 const: 1
60
61 "#size-cells":
62 const: 0
63
64 clocks:
65 minItems: 1
66 maxItems: 4
67
68 clock-names:
69 minItems: 1
70 items:
71 - const: xtal
72 - const: in0
73 - const: in1
74 - const: in2
75
76 clock-output-names: true
77
78 interrupts:
79 maxItems: 1
80 description: Interrupt for INTRb pin
81
82 vdd-supply:
83 description: Regulator node for VDD
84
85 vdda-supply:
86 description: Regulator node for VDDA
87
88 vdds-supply:
89 description: Regulator node for VDDS
90
91 silabs,pll-m-num:
92 description:
93 Numerator for PLL feedback divider. Must be such that the PLL output is in
94 the valid range. For example, to create 14GHz from a 48MHz xtal, use
95 m-num=14000 and m-den=48. Only the fraction matters, using 3500 and 12
96 will deliver the exact same result. If these are not specified, and the
97 PLL is not yet programmed when the driver probes, the PLL will be set to
98 14GHz.
99 $ref: /schemas/types.yaml#/definitions/uint32
100
101 silabs,pll-m-den:
102 description: Denominator for PLL feedback divider
103 $ref: /schemas/types.yaml#/definitions/uint32
104
105 silabs,reprogram:
106 description: Always perform soft-reset and reinitialize PLL
107 type: boolean
108
109 silabs,xaxb-ext-clk:
110 description: Use XA/XB pins as external reference clock
111 type: boolean
112
113 silabs,iovdd-33:
114 description: I2C lines use 3.3V thresholds
115 type: boolean
116
117patternProperties:
118 "^vddo[0-9]-supply$": true
119
120 "^out@[0-9]$":
121 description: >
122 Output-specific override nodes
123
124 Each of the clock outputs can be overwritten individually by using a child
125 node. If a child node for a clock output is not set, the configuration
126 remains unchanged.
127 type: object
128 additionalProperties: false
129
130 properties:
131 reg:
132 description: Number of clock output
133 maximum: 9
134
135 always-on:
136 description: Set to keep the clock output always running
137 type: boolean
138
139 silabs,format:
140 description: Output format
141 $ref: /schemas/types.yaml#/definitions/uint32
142 enum: [1, 2, 4]
143
144 silabs,common-mode:
145 description: Override output common mode
146 $ref: /schemas/types.yaml#/definitions/uint32
147
148 silabs,amplitude:
149 description: Override output amplitude
150 $ref: /schemas/types.yaml#/definitions/uint32
151
152 silabs,synth-master:
153 description: Allow dynamic multisynth rate control
154 type: boolean
155
156 silabs,disable-high:
157 description: Drive output HIGH when disabled
158 type: boolean
159
160 required:
161 - reg
162
163required:
164 - compatible
165 - reg
166 - "#clock-cells"
167 - "#address-cells"
168 - "#size-cells"
169 - clocks
170 - clock-names
171
172additionalProperties: false
173
174examples:
175 - |
176 i2c {
177 #address-cells = <1>;
178 #size-cells = <0>;
179
180 clock-generator@74 {
181 reg = <0x74>;
182 compatible = "silabs,si5341";
183 #clock-cells = <2>;
184 #address-cells = <1>;
185 #size-cells = <0>;
186 clocks = <&ref48>;
187 clock-names = "xtal";
188
189 silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */
190 silabs,pll-m-den = <48>;
191 silabs,reprogram; /* Chips are not programmed, always reset */
192
193 out@0 {
194 reg = <0>;
195 silabs,format = <1>; /* LVDS 3v3 */
196 silabs,common-mode = <3>;
197 silabs,amplitude = <3>;
198 silabs,synth-master;
199 };
200
201 /*
202 * Output 6 configuration:
203 * LVDS 1v8
204 */
205 out@6 {
206 reg = <6>;
207 silabs,format = <1>; /* LVDS 1v8 */
208 silabs,common-mode = <13>;
209 silabs,amplitude = <3>;
210 };
211
212 /*
213 * Output 8 configuration:
214 * HCSL 3v3
215 */
216 out@8 {
217 reg = <8>;
218 silabs,format = <2>;
219 silabs,common-mode = <11>;
220 silabs,amplitude = <3>;
221 };
222 };
223 };