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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __AMDGPU_RESET_H__
25#define __AMDGPU_RESET_H__
26
27#include "amdgpu.h"
28
29enum AMDGPU_RESET_FLAGS {
30
31 AMDGPU_NEED_FULL_RESET = 0,
32 AMDGPU_SKIP_HW_RESET = 1,
33};
34
35struct amdgpu_reset_context {
36 enum amd_reset_method method;
37 struct amdgpu_device *reset_req_dev;
38 struct amdgpu_job *job;
39 struct amdgpu_hive_info *hive;
40 struct list_head *reset_device_list;
41 unsigned long flags;
42};
43
44struct amdgpu_reset_handler {
45 enum amd_reset_method reset_method;
46 struct list_head handler_list;
47 int (*prepare_env)(struct amdgpu_reset_control *reset_ctl,
48 struct amdgpu_reset_context *context);
49 int (*prepare_hwcontext)(struct amdgpu_reset_control *reset_ctl,
50 struct amdgpu_reset_context *context);
51 int (*perform_reset)(struct amdgpu_reset_control *reset_ctl,
52 struct amdgpu_reset_context *context);
53 int (*restore_hwcontext)(struct amdgpu_reset_control *reset_ctl,
54 struct amdgpu_reset_context *context);
55 int (*restore_env)(struct amdgpu_reset_control *reset_ctl,
56 struct amdgpu_reset_context *context);
57
58 int (*do_reset)(struct amdgpu_device *adev);
59};
60
61struct amdgpu_reset_control {
62 void *handle;
63 struct work_struct reset_work;
64 struct mutex reset_lock;
65 struct list_head reset_handlers;
66 atomic_t in_reset;
67 enum amd_reset_method active_reset;
68 struct amdgpu_reset_handler *(*get_reset_handler)(
69 struct amdgpu_reset_control *reset_ctl,
70 struct amdgpu_reset_context *context);
71 void (*async_reset)(struct work_struct *work);
72};
73
74
75enum amdgpu_reset_domain_type {
76 SINGLE_DEVICE,
77 XGMI_HIVE
78};
79
80struct amdgpu_reset_domain {
81 struct kref refcount;
82 struct workqueue_struct *wq;
83 enum amdgpu_reset_domain_type type;
84 struct rw_semaphore sem;
85 atomic_t in_gpu_reset;
86 atomic_t reset_res;
87};
88
89
90int amdgpu_reset_init(struct amdgpu_device *adev);
91int amdgpu_reset_fini(struct amdgpu_device *adev);
92
93int amdgpu_reset_prepare_hwcontext(struct amdgpu_device *adev,
94 struct amdgpu_reset_context *reset_context);
95
96int amdgpu_reset_perform_reset(struct amdgpu_device *adev,
97 struct amdgpu_reset_context *reset_context);
98
99int amdgpu_reset_add_handler(struct amdgpu_reset_control *reset_ctl,
100 struct amdgpu_reset_handler *handler);
101
102struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_domain_type type,
103 char *wq_name);
104
105void amdgpu_reset_destroy_reset_domain(struct kref *ref);
106
107static inline bool amdgpu_reset_get_reset_domain(struct amdgpu_reset_domain *domain)
108{
109 return kref_get_unless_zero(&domain->refcount) != 0;
110}
111
112static inline void amdgpu_reset_put_reset_domain(struct amdgpu_reset_domain *domain)
113{
114 kref_put(&domain->refcount, amdgpu_reset_destroy_reset_domain);
115}
116
117static inline bool amdgpu_reset_domain_schedule(struct amdgpu_reset_domain *domain,
118 struct work_struct *work)
119{
120 return queue_work(domain->wq, work);
121}
122
123void amdgpu_device_lock_reset_domain(struct amdgpu_reset_domain *reset_domain);
124
125void amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain *reset_domain);
126
127#endif