tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Pinctrl data for the NVIDIA Tegra194 pinmux
4 *
5 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 */
16
17#include <linux/init.h>
18#include <linux/of.h>
19#include <linux/platform_device.h>
20#include <linux/pinctrl/pinctrl.h>
21#include <linux/pinctrl/pinmux.h>
22
23#include "pinctrl-tegra.h"
24
25/* Define unique ID for each pins */
26enum pin_id {
27 TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
28 TEGRA_PIN_PEX_L5_RST_N_PGG1,
29};
30
31/* Table for pin descriptor */
32static const struct pinctrl_pin_desc tegra194_pins[] = {
33 PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, "PEX_L5_CLKREQ_N_PGG0"),
34 PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1, "PEX_L5_RST_N_PGG1"),
35};
36
37static const unsigned int pex_l5_clkreq_n_pgg0_pins[] = {
38 TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
39};
40
41static const unsigned int pex_l5_rst_n_pgg1_pins[] = {
42 TEGRA_PIN_PEX_L5_RST_N_PGG1,
43};
44
45/* Define unique ID for each function */
46enum tegra_mux_dt {
47 TEGRA_MUX_RSVD0,
48 TEGRA_MUX_RSVD1,
49 TEGRA_MUX_RSVD2,
50 TEGRA_MUX_RSVD3,
51 TEGRA_MUX_PE5,
52};
53
54/* Make list of each function name */
55#define TEGRA_PIN_FUNCTION(lid) \
56 { \
57 .name = #lid, \
58 }
59
60static struct tegra_function tegra194_functions[] = {
61 TEGRA_PIN_FUNCTION(rsvd0),
62 TEGRA_PIN_FUNCTION(rsvd1),
63 TEGRA_PIN_FUNCTION(rsvd2),
64 TEGRA_PIN_FUNCTION(rsvd3),
65 TEGRA_PIN_FUNCTION(pe5),
66};
67
68#define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b, \
69 drvup_w, slwr_b, slwr_w, slwf_b, \
70 slwf_w, bank) \
71 .drv_reg = ((r)), \
72 .drv_bank = bank, \
73 .drvdn_bit = drvdn_b, \
74 .drvdn_width = drvdn_w, \
75 .drvup_bit = drvup_b, \
76 .drvup_width = drvup_w, \
77 .slwr_bit = slwr_b, \
78 .slwr_width = slwr_w, \
79 .slwf_bit = slwf_b, \
80 .slwf_width = slwf_w
81
82#define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_lpbk, e_input, \
83 e_od, schmitt_b, drvtype) \
84 .mux_reg = ((r)), \
85 .lpmd_bit = -1, \
86 .lock_bit = -1, \
87 .hsm_bit = -1, \
88 .mux_bank = bank, \
89 .mux_bit = 0, \
90 .pupd_reg = ((r)), \
91 .pupd_bank = bank, \
92 .pupd_bit = 2, \
93 .tri_reg = ((r)), \
94 .tri_bank = bank, \
95 .tri_bit = 4, \
96 .einput_bit = e_input, \
97 .odrain_bit = e_od, \
98 .sfsel_bit = 10, \
99 .schmitt_bit = schmitt_b, \
100 .drvtype_bit = 13, \
101 .drv_reg = -1, \
102 .parked_bitmask = 0
103
104#define drive_pex_l5_clkreq_n_pgg0 \
105 DRV_PINGROUP_ENTRY_Y(0x14004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
106#define drive_pex_l5_rst_n_pgg1 \
107 DRV_PINGROUP_ENTRY_Y(0x1400c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
108
109#define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_lpbk, \
110 e_input, e_lpdr, e_od, schmitt_b, drvtype, io_rail) \
111 { \
112 .name = #pg_name, \
113 .pins = pg_name##_pins, \
114 .npins = ARRAY_SIZE(pg_name##_pins), \
115 .funcs = { \
116 TEGRA_MUX_##f0, \
117 TEGRA_MUX_##f1, \
118 TEGRA_MUX_##f2, \
119 TEGRA_MUX_##f3, \
120 }, \
121 PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_lpbk, \
122 e_input, e_od, \
123 schmitt_b, drvtype), \
124 drive_##pg_name, \
125 }
126
127static const struct tegra_pingroup tegra194_groups[] = {
128 PINGROUP(pex_l5_clkreq_n_pgg0, PE5, RSVD1, RSVD2, RSVD3, 0x14000, 0,
129 Y, -1, 6, 8, 11, 12, N, "vddio_pex_ctl_2"),
130 PINGROUP(pex_l5_rst_n_pgg1, PE5, RSVD1, RSVD2, RSVD3, 0x14008, 0,
131 Y, -1, 6, 8, 11, 12, N, "vddio_pex_ctl_2"),
132};
133
134static const struct tegra_pinctrl_soc_data tegra194_pinctrl = {
135 .pins = tegra194_pins,
136 .npins = ARRAY_SIZE(tegra194_pins),
137 .functions = tegra194_functions,
138 .nfunctions = ARRAY_SIZE(tegra194_functions),
139 .groups = tegra194_groups,
140 .ngroups = ARRAY_SIZE(tegra194_groups),
141 .hsm_in_mux = true,
142 .schmitt_in_mux = true,
143 .drvtype_in_mux = true,
144 .sfsel_in_mux = true,
145};
146
147static int tegra194_pinctrl_probe(struct platform_device *pdev)
148{
149 return tegra_pinctrl_probe(pdev, &tegra194_pinctrl);
150}
151
152static const struct of_device_id tegra194_pinctrl_of_match[] = {
153 { .compatible = "nvidia,tegra194-pinmux", },
154 { },
155};
156
157static struct platform_driver tegra194_pinctrl_driver = {
158 .driver = {
159 .name = "tegra194-pinctrl",
160 .of_match_table = tegra194_pinctrl_of_match,
161 },
162 .probe = tegra194_pinctrl_probe,
163};
164
165static int __init tegra194_pinctrl_init(void)
166{
167 return platform_driver_register(&tegra194_pinctrl_driver);
168}
169arch_initcall(tegra194_pinctrl_init);