Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * OHCI HCD (Host Controller Driver) for USB.
3 *
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
6 *
7 * [ Initialisation is based on Linus' ]
8 * [ uhci code and gregs ohci fragments ]
9 * [ (C) Copyright 1999 Linus Torvalds ]
10 * [ (C) Copyright 1999 Gregory P. Smith]
11 *
12 * PCI Bus Glue
13 *
14 * This file is licenced under the GPL.
15 */
16
17#ifndef CONFIG_PCI
18#error "This file is PCI bus glue. CONFIG_PCI must be defined."
19#endif
20
21/*-------------------------------------------------------------------------*/
22
23static int broken_suspend(struct usb_hcd *hcd)
24{
25 device_init_wakeup(&hcd->self.root_hub->dev, 0);
26 return 0;
27}
28
29/* AMD 756, for most chips (early revs), corrupts register
30 * values on read ... so enable the vendor workaround.
31 */
32static int ohci_quirk_amd756(struct usb_hcd *hcd)
33{
34 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
35
36 ohci->flags = OHCI_QUIRK_AMD756;
37 ohci_dbg (ohci, "AMD756 erratum 4 workaround\n");
38
39 /* also erratum 10 (suspend/resume issues) */
40 return broken_suspend(hcd);
41}
42
43/* Apple's OHCI driver has a lot of bizarre workarounds
44 * for this chip. Evidently control and bulk lists
45 * can get confused. (B&W G3 models, and ...)
46 */
47static int ohci_quirk_opti(struct usb_hcd *hcd)
48{
49 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
50
51 ohci_dbg (ohci, "WARNING: OPTi workarounds unavailable\n");
52
53 return 0;
54}
55
56/* Check for NSC87560. We have to look at the bridge (fn1) to
57 * identify the USB (fn2). This quirk might apply to more or
58 * even all NSC stuff.
59 */
60static int ohci_quirk_ns(struct usb_hcd *hcd)
61{
62 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
63 struct pci_dev *b;
64
65 b = pci_get_slot (pdev->bus, PCI_DEVFN (PCI_SLOT (pdev->devfn), 1));
66 if (b && b->device == PCI_DEVICE_ID_NS_87560_LIO
67 && b->vendor == PCI_VENDOR_ID_NS) {
68 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
69
70 ohci->flags |= OHCI_QUIRK_SUPERIO;
71 ohci_dbg (ohci, "Using NSC SuperIO setup\n");
72 }
73 pci_dev_put(b);
74
75 return 0;
76}
77
78/* Check for Compaq's ZFMicro chipset, which needs short
79 * delays before control or bulk queues get re-activated
80 * in finish_unlinks()
81 */
82static int ohci_quirk_zfmicro(struct usb_hcd *hcd)
83{
84 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
85
86 ohci->flags |= OHCI_QUIRK_ZFMICRO;
87 ohci_dbg(ohci, "enabled Compaq ZFMicro chipset quirks\n");
88
89 return 0;
90}
91
92/* Check for Toshiba SCC OHCI which has big endian registers
93 * and little endian in memory data structures
94 */
95static int ohci_quirk_toshiba_scc(struct usb_hcd *hcd)
96{
97 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
98
99 /* That chip is only present in the southbridge of some
100 * cell based platforms which are supposed to select
101 * CONFIG_USB_OHCI_BIG_ENDIAN_MMIO. We verify here if
102 * that was the case though.
103 */
104#ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
105 ohci->flags |= OHCI_QUIRK_BE_MMIO;
106 ohci_dbg (ohci, "enabled big endian Toshiba quirk\n");
107 return 0;
108#else
109 ohci_err (ohci, "unsupported big endian Toshiba quirk\n");
110 return -ENXIO;
111#endif
112}
113
114/* Check for NEC chip and apply quirk for allegedly lost interrupts.
115 */
116
117static void ohci_quirk_nec_worker(struct work_struct *work)
118{
119 struct ohci_hcd *ohci = container_of(work, struct ohci_hcd, nec_work);
120 int status;
121
122 status = ohci_init(ohci);
123 if (status != 0) {
124 ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n",
125 "ohci_init", status);
126 return;
127 }
128
129 status = ohci_restart(ohci);
130 if (status != 0)
131 ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n",
132 "ohci_restart", status);
133}
134
135static int ohci_quirk_nec(struct usb_hcd *hcd)
136{
137 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
138
139 ohci->flags |= OHCI_QUIRK_NEC;
140 INIT_WORK(&ohci->nec_work, ohci_quirk_nec_worker);
141 ohci_dbg (ohci, "enabled NEC chipset lost interrupt quirk\n");
142
143 return 0;
144}
145
146/* List of quirks for OHCI */
147static const struct pci_device_id ohci_pci_quirks[] = {
148 {
149 PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x740c),
150 .driver_data = (unsigned long)ohci_quirk_amd756,
151 },
152 {
153 PCI_DEVICE(PCI_VENDOR_ID_OPTI, 0xc861),
154 .driver_data = (unsigned long)ohci_quirk_opti,
155 },
156 {
157 PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_ANY_ID),
158 .driver_data = (unsigned long)ohci_quirk_ns,
159 },
160 {
161 PCI_DEVICE(PCI_VENDOR_ID_COMPAQ, 0xa0f8),
162 .driver_data = (unsigned long)ohci_quirk_zfmicro,
163 },
164 {
165 PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, 0x01b6),
166 .driver_data = (unsigned long)ohci_quirk_toshiba_scc,
167 },
168 {
169 PCI_DEVICE(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB),
170 .driver_data = (unsigned long)ohci_quirk_nec,
171 },
172 {
173 /* Toshiba portege 4000 */
174 .vendor = PCI_VENDOR_ID_AL,
175 .device = 0x5237,
176 .subvendor = PCI_VENDOR_ID_TOSHIBA,
177 .subdevice = 0x0004,
178 .driver_data = (unsigned long) broken_suspend,
179 },
180 {
181 PCI_DEVICE(PCI_VENDOR_ID_ITE, 0x8152),
182 .driver_data = (unsigned long) broken_suspend,
183 },
184 /* FIXME for some of the early AMD 760 southbridges, OHCI
185 * won't work at all. blacklist them.
186 */
187
188 {},
189};
190
191static int ohci_pci_reset (struct usb_hcd *hcd)
192{
193 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
194 int ret = 0;
195
196 if (hcd->self.controller) {
197 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
198 const struct pci_device_id *quirk_id;
199
200 quirk_id = pci_match_id(ohci_pci_quirks, pdev);
201 if (quirk_id != NULL) {
202 int (*quirk)(struct usb_hcd *ohci);
203 quirk = (void *)quirk_id->driver_data;
204 ret = quirk(hcd);
205 }
206 }
207 if (ret == 0) {
208 ohci_hcd_init (ohci);
209 return ohci_init (ohci);
210 }
211 return ret;
212}
213
214
215static int __devinit ohci_pci_start (struct usb_hcd *hcd)
216{
217 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
218 int ret;
219
220#ifdef CONFIG_PM /* avoid warnings about unused pdev */
221 if (hcd->self.controller) {
222 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
223
224 /* RWC may not be set for add-in PCI cards, since boot
225 * firmware probably ignored them. This transfers PCI
226 * PM wakeup capabilities (once the PCI layer is fixed).
227 */
228 if (device_may_wakeup(&pdev->dev))
229 ohci->hc_control |= OHCI_CTRL_RWC;
230 }
231#endif /* CONFIG_PM */
232
233 ret = ohci_run (ohci);
234 if (ret < 0) {
235 ohci_err (ohci, "can't start\n");
236 ohci_stop (hcd);
237 }
238 return ret;
239}
240
241#if defined(CONFIG_USB_PERSIST) && (defined(CONFIG_USB_EHCI_HCD) || \
242 defined(CONFIG_USB_EHCI_HCD_MODULE))
243
244/* Following a power loss, we must prepare to regain control of the ports
245 * we used to own. This means turning on the port power before ehci-hcd
246 * tries to switch ownership.
247 *
248 * This isn't a 100% perfect solution. On most systems the OHCI controllers
249 * lie at lower PCI addresses than the EHCI controller, so they will be
250 * discovered (and hence resumed) first. But there is no guarantee things
251 * will always work this way. If the EHCI controller is resumed first and
252 * the OHCI ports are unpowered, then the handover will fail.
253 */
254static void prepare_for_handover(struct usb_hcd *hcd)
255{
256 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
257 int port;
258
259 /* Here we "know" root ports should always stay powered */
260 ohci_dbg(ohci, "powerup ports\n");
261 for (port = 0; port < ohci->num_ports; port++)
262 ohci_writel(ohci, RH_PS_PPS,
263 &ohci->regs->roothub.portstatus[port]);
264
265 /* Flush those writes */
266 ohci_readl(ohci, &ohci->regs->control);
267 msleep(20);
268}
269
270#else
271
272static inline void prepare_for_handover(struct usb_hcd *hcd)
273{ }
274
275#endif /* CONFIG_USB_PERSIST etc. */
276
277#ifdef CONFIG_PM
278
279static int ohci_pci_suspend (struct usb_hcd *hcd, pm_message_t message)
280{
281 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
282 unsigned long flags;
283 int rc = 0;
284
285 /* Root hub was already suspended. Disable irq emission and
286 * mark HW unaccessible, bail out if RH has been resumed. Use
287 * the spinlock to properly synchronize with possible pending
288 * RH suspend or resume activity.
289 *
290 * This is still racy as hcd->state is manipulated outside of
291 * any locks =P But that will be a different fix.
292 */
293 spin_lock_irqsave (&ohci->lock, flags);
294 if (hcd->state != HC_STATE_SUSPENDED) {
295 rc = -EINVAL;
296 goto bail;
297 }
298 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
299 (void)ohci_readl(ohci, &ohci->regs->intrdisable);
300
301 /* make sure snapshot being resumed re-enumerates everything */
302 if (message.event == PM_EVENT_PRETHAW)
303 ohci_usb_reset(ohci);
304
305 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
306 bail:
307 spin_unlock_irqrestore (&ohci->lock, flags);
308
309 return rc;
310}
311
312
313static int ohci_pci_resume (struct usb_hcd *hcd)
314{
315 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
316
317 /* FIXME: we should try to detect loss of VBUS power here */
318 prepare_for_handover(hcd);
319
320 return 0;
321}
322
323#endif /* CONFIG_PM */
324
325
326/*-------------------------------------------------------------------------*/
327
328static const struct hc_driver ohci_pci_hc_driver = {
329 .description = hcd_name,
330 .product_desc = "OHCI Host Controller",
331 .hcd_priv_size = sizeof(struct ohci_hcd),
332
333 /*
334 * generic hardware linkage
335 */
336 .irq = ohci_irq,
337 .flags = HCD_MEMORY | HCD_USB11,
338
339 /*
340 * basic lifecycle operations
341 */
342 .reset = ohci_pci_reset,
343 .start = ohci_pci_start,
344 .stop = ohci_stop,
345 .shutdown = ohci_shutdown,
346
347#ifdef CONFIG_PM
348 /* these suspend/resume entries are for upstream PCI glue ONLY */
349 .suspend = ohci_pci_suspend,
350 .resume = ohci_pci_resume,
351#endif
352
353 /*
354 * managing i/o requests and associated device resources
355 */
356 .urb_enqueue = ohci_urb_enqueue,
357 .urb_dequeue = ohci_urb_dequeue,
358 .endpoint_disable = ohci_endpoint_disable,
359
360 /*
361 * scheduling support
362 */
363 .get_frame_number = ohci_get_frame,
364
365 /*
366 * root hub support
367 */
368 .hub_status_data = ohci_hub_status_data,
369 .hub_control = ohci_hub_control,
370 .hub_irq_enable = ohci_rhsc_enable,
371#ifdef CONFIG_PM
372 .bus_suspend = ohci_bus_suspend,
373 .bus_resume = ohci_bus_resume,
374#endif
375 .start_port_reset = ohci_start_port_reset,
376};
377
378/*-------------------------------------------------------------------------*/
379
380
381static const struct pci_device_id pci_ids [] = { {
382 /* handle any USB OHCI controller */
383 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_OHCI, ~0),
384 .driver_data = (unsigned long) &ohci_pci_hc_driver,
385 }, { /* end: all zeroes */ }
386};
387MODULE_DEVICE_TABLE (pci, pci_ids);
388
389/* pci driver glue; this is a "new style" PCI driver module */
390static struct pci_driver ohci_pci_driver = {
391 .name = (char *) hcd_name,
392 .id_table = pci_ids,
393
394 .probe = usb_hcd_pci_probe,
395 .remove = usb_hcd_pci_remove,
396
397#ifdef CONFIG_PM
398 .suspend = usb_hcd_pci_suspend,
399 .resume = usb_hcd_pci_resume,
400#endif
401
402 .shutdown = usb_hcd_pci_shutdown,
403};
404