tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31*/
32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
35#include "mlx5_ifc_fpga.h"
36
37enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
63};
64
65enum {
66 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
67 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
68 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
69 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
70};
71
72enum {
73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
74 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
75};
76
77enum {
78 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
79 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
80 MLX5_CMD_OP_INIT_HCA = 0x102,
81 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
82 MLX5_CMD_OP_ENABLE_HCA = 0x104,
83 MLX5_CMD_OP_DISABLE_HCA = 0x105,
84 MLX5_CMD_OP_QUERY_PAGES = 0x107,
85 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
86 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
87 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
88 MLX5_CMD_OP_SET_ISSI = 0x10b,
89 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
90 MLX5_CMD_OP_CREATE_MKEY = 0x200,
91 MLX5_CMD_OP_QUERY_MKEY = 0x201,
92 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
93 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
94 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
95 MLX5_CMD_OP_CREATE_EQ = 0x301,
96 MLX5_CMD_OP_DESTROY_EQ = 0x302,
97 MLX5_CMD_OP_QUERY_EQ = 0x303,
98 MLX5_CMD_OP_GEN_EQE = 0x304,
99 MLX5_CMD_OP_CREATE_CQ = 0x400,
100 MLX5_CMD_OP_DESTROY_CQ = 0x401,
101 MLX5_CMD_OP_QUERY_CQ = 0x402,
102 MLX5_CMD_OP_MODIFY_CQ = 0x403,
103 MLX5_CMD_OP_CREATE_QP = 0x500,
104 MLX5_CMD_OP_DESTROY_QP = 0x501,
105 MLX5_CMD_OP_RST2INIT_QP = 0x502,
106 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
107 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
108 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
109 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
110 MLX5_CMD_OP_2ERR_QP = 0x507,
111 MLX5_CMD_OP_2RST_QP = 0x50a,
112 MLX5_CMD_OP_QUERY_QP = 0x50b,
113 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
114 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
115 MLX5_CMD_OP_CREATE_PSV = 0x600,
116 MLX5_CMD_OP_DESTROY_PSV = 0x601,
117 MLX5_CMD_OP_CREATE_SRQ = 0x700,
118 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
119 MLX5_CMD_OP_QUERY_SRQ = 0x702,
120 MLX5_CMD_OP_ARM_RQ = 0x703,
121 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
122 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
123 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
124 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
125 MLX5_CMD_OP_CREATE_DCT = 0x710,
126 MLX5_CMD_OP_DESTROY_DCT = 0x711,
127 MLX5_CMD_OP_DRAIN_DCT = 0x712,
128 MLX5_CMD_OP_QUERY_DCT = 0x713,
129 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
130 MLX5_CMD_OP_CREATE_XRQ = 0x717,
131 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
132 MLX5_CMD_OP_QUERY_XRQ = 0x719,
133 MLX5_CMD_OP_ARM_XRQ = 0x71a,
134 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
135 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
136 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
137 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
138 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
139 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
140 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
141 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
142 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
143 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
144 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
145 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
146 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
147 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
148 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
149 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
150 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
151 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
152 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
153 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
154 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
155 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
156 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
157 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
158 MLX5_CMD_OP_ALLOC_PD = 0x800,
159 MLX5_CMD_OP_DEALLOC_PD = 0x801,
160 MLX5_CMD_OP_ALLOC_UAR = 0x802,
161 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
162 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
163 MLX5_CMD_OP_ACCESS_REG = 0x805,
164 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
165 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
166 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
167 MLX5_CMD_OP_MAD_IFC = 0x50d,
168 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
169 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
170 MLX5_CMD_OP_NOP = 0x80d,
171 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
172 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
173 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
174 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
175 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
176 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
177 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
178 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
179 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
180 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
181 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
182 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
183 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
184 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
185 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
186 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
187 MLX5_CMD_OP_CREATE_LAG = 0x840,
188 MLX5_CMD_OP_MODIFY_LAG = 0x841,
189 MLX5_CMD_OP_QUERY_LAG = 0x842,
190 MLX5_CMD_OP_DESTROY_LAG = 0x843,
191 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
192 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
193 MLX5_CMD_OP_CREATE_TIR = 0x900,
194 MLX5_CMD_OP_MODIFY_TIR = 0x901,
195 MLX5_CMD_OP_DESTROY_TIR = 0x902,
196 MLX5_CMD_OP_QUERY_TIR = 0x903,
197 MLX5_CMD_OP_CREATE_SQ = 0x904,
198 MLX5_CMD_OP_MODIFY_SQ = 0x905,
199 MLX5_CMD_OP_DESTROY_SQ = 0x906,
200 MLX5_CMD_OP_QUERY_SQ = 0x907,
201 MLX5_CMD_OP_CREATE_RQ = 0x908,
202 MLX5_CMD_OP_MODIFY_RQ = 0x909,
203 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
204 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
205 MLX5_CMD_OP_QUERY_RQ = 0x90b,
206 MLX5_CMD_OP_CREATE_RMP = 0x90c,
207 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
208 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
209 MLX5_CMD_OP_QUERY_RMP = 0x90f,
210 MLX5_CMD_OP_CREATE_TIS = 0x912,
211 MLX5_CMD_OP_MODIFY_TIS = 0x913,
212 MLX5_CMD_OP_DESTROY_TIS = 0x914,
213 MLX5_CMD_OP_QUERY_TIS = 0x915,
214 MLX5_CMD_OP_CREATE_RQT = 0x916,
215 MLX5_CMD_OP_MODIFY_RQT = 0x917,
216 MLX5_CMD_OP_DESTROY_RQT = 0x918,
217 MLX5_CMD_OP_QUERY_RQT = 0x919,
218 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
219 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
220 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
221 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
222 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
223 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
224 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
225 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
226 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
227 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
228 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
229 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
230 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
231 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
232 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
233 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
234 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
235 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
236 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
237 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
238 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
239 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
240 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
241 MLX5_CMD_OP_MAX
242};
243
244struct mlx5_ifc_flow_table_fields_supported_bits {
245 u8 outer_dmac[0x1];
246 u8 outer_smac[0x1];
247 u8 outer_ether_type[0x1];
248 u8 outer_ip_version[0x1];
249 u8 outer_first_prio[0x1];
250 u8 outer_first_cfi[0x1];
251 u8 outer_first_vid[0x1];
252 u8 outer_ipv4_ttl[0x1];
253 u8 outer_second_prio[0x1];
254 u8 outer_second_cfi[0x1];
255 u8 outer_second_vid[0x1];
256 u8 reserved_at_b[0x1];
257 u8 outer_sip[0x1];
258 u8 outer_dip[0x1];
259 u8 outer_frag[0x1];
260 u8 outer_ip_protocol[0x1];
261 u8 outer_ip_ecn[0x1];
262 u8 outer_ip_dscp[0x1];
263 u8 outer_udp_sport[0x1];
264 u8 outer_udp_dport[0x1];
265 u8 outer_tcp_sport[0x1];
266 u8 outer_tcp_dport[0x1];
267 u8 outer_tcp_flags[0x1];
268 u8 outer_gre_protocol[0x1];
269 u8 outer_gre_key[0x1];
270 u8 outer_vxlan_vni[0x1];
271 u8 reserved_at_1a[0x5];
272 u8 source_eswitch_port[0x1];
273
274 u8 inner_dmac[0x1];
275 u8 inner_smac[0x1];
276 u8 inner_ether_type[0x1];
277 u8 inner_ip_version[0x1];
278 u8 inner_first_prio[0x1];
279 u8 inner_first_cfi[0x1];
280 u8 inner_first_vid[0x1];
281 u8 reserved_at_27[0x1];
282 u8 inner_second_prio[0x1];
283 u8 inner_second_cfi[0x1];
284 u8 inner_second_vid[0x1];
285 u8 reserved_at_2b[0x1];
286 u8 inner_sip[0x1];
287 u8 inner_dip[0x1];
288 u8 inner_frag[0x1];
289 u8 inner_ip_protocol[0x1];
290 u8 inner_ip_ecn[0x1];
291 u8 inner_ip_dscp[0x1];
292 u8 inner_udp_sport[0x1];
293 u8 inner_udp_dport[0x1];
294 u8 inner_tcp_sport[0x1];
295 u8 inner_tcp_dport[0x1];
296 u8 inner_tcp_flags[0x1];
297 u8 reserved_at_37[0x9];
298 u8 reserved_at_40[0x1a];
299 u8 bth_dst_qp[0x1];
300
301 u8 reserved_at_5b[0x25];
302};
303
304struct mlx5_ifc_flow_table_prop_layout_bits {
305 u8 ft_support[0x1];
306 u8 reserved_at_1[0x1];
307 u8 flow_counter[0x1];
308 u8 flow_modify_en[0x1];
309 u8 modify_root[0x1];
310 u8 identified_miss_table_mode[0x1];
311 u8 flow_table_modify[0x1];
312 u8 encap[0x1];
313 u8 decap[0x1];
314 u8 reserved_at_9[0x17];
315
316 u8 reserved_at_20[0x2];
317 u8 log_max_ft_size[0x6];
318 u8 log_max_modify_header_context[0x8];
319 u8 max_modify_header_actions[0x8];
320 u8 max_ft_level[0x8];
321
322 u8 reserved_at_40[0x20];
323
324 u8 reserved_at_60[0x18];
325 u8 log_max_ft_num[0x8];
326
327 u8 reserved_at_80[0x18];
328 u8 log_max_destination[0x8];
329
330 u8 reserved_at_a0[0x18];
331 u8 log_max_flow[0x8];
332
333 u8 reserved_at_c0[0x40];
334
335 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
336
337 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
338};
339
340struct mlx5_ifc_odp_per_transport_service_cap_bits {
341 u8 send[0x1];
342 u8 receive[0x1];
343 u8 write[0x1];
344 u8 read[0x1];
345 u8 atomic[0x1];
346 u8 srq_receive[0x1];
347 u8 reserved_at_6[0x1a];
348};
349
350struct mlx5_ifc_ipv4_layout_bits {
351 u8 reserved_at_0[0x60];
352
353 u8 ipv4[0x20];
354};
355
356struct mlx5_ifc_ipv6_layout_bits {
357 u8 ipv6[16][0x8];
358};
359
360union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
361 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
362 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
363 u8 reserved_at_0[0x80];
364};
365
366struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
367 u8 smac_47_16[0x20];
368
369 u8 smac_15_0[0x10];
370 u8 ethertype[0x10];
371
372 u8 dmac_47_16[0x20];
373
374 u8 dmac_15_0[0x10];
375 u8 first_prio[0x3];
376 u8 first_cfi[0x1];
377 u8 first_vid[0xc];
378
379 u8 ip_protocol[0x8];
380 u8 ip_dscp[0x6];
381 u8 ip_ecn[0x2];
382 u8 cvlan_tag[0x1];
383 u8 svlan_tag[0x1];
384 u8 frag[0x1];
385 u8 ip_version[0x4];
386 u8 tcp_flags[0x9];
387
388 u8 tcp_sport[0x10];
389 u8 tcp_dport[0x10];
390
391 u8 reserved_at_c0[0x18];
392 u8 ttl_hoplimit[0x8];
393
394 u8 udp_sport[0x10];
395 u8 udp_dport[0x10];
396
397 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
398
399 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
400};
401
402struct mlx5_ifc_fte_match_set_misc_bits {
403 u8 reserved_at_0[0x8];
404 u8 source_sqn[0x18];
405
406 u8 reserved_at_20[0x10];
407 u8 source_port[0x10];
408
409 u8 outer_second_prio[0x3];
410 u8 outer_second_cfi[0x1];
411 u8 outer_second_vid[0xc];
412 u8 inner_second_prio[0x3];
413 u8 inner_second_cfi[0x1];
414 u8 inner_second_vid[0xc];
415
416 u8 outer_second_cvlan_tag[0x1];
417 u8 inner_second_cvlan_tag[0x1];
418 u8 outer_second_svlan_tag[0x1];
419 u8 inner_second_svlan_tag[0x1];
420 u8 reserved_at_64[0xc];
421 u8 gre_protocol[0x10];
422
423 u8 gre_key_h[0x18];
424 u8 gre_key_l[0x8];
425
426 u8 vxlan_vni[0x18];
427 u8 reserved_at_b8[0x8];
428
429 u8 reserved_at_c0[0x20];
430
431 u8 reserved_at_e0[0xc];
432 u8 outer_ipv6_flow_label[0x14];
433
434 u8 reserved_at_100[0xc];
435 u8 inner_ipv6_flow_label[0x14];
436
437 u8 reserved_at_120[0x28];
438 u8 bth_dst_qp[0x18];
439 u8 reserved_at_160[0xa0];
440};
441
442struct mlx5_ifc_cmd_pas_bits {
443 u8 pa_h[0x20];
444
445 u8 pa_l[0x14];
446 u8 reserved_at_34[0xc];
447};
448
449struct mlx5_ifc_uint64_bits {
450 u8 hi[0x20];
451
452 u8 lo[0x20];
453};
454
455enum {
456 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
457 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
458 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
459 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
460 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
461 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
462 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
463 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
464 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
465 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
466};
467
468struct mlx5_ifc_ads_bits {
469 u8 fl[0x1];
470 u8 free_ar[0x1];
471 u8 reserved_at_2[0xe];
472 u8 pkey_index[0x10];
473
474 u8 reserved_at_20[0x8];
475 u8 grh[0x1];
476 u8 mlid[0x7];
477 u8 rlid[0x10];
478
479 u8 ack_timeout[0x5];
480 u8 reserved_at_45[0x3];
481 u8 src_addr_index[0x8];
482 u8 reserved_at_50[0x4];
483 u8 stat_rate[0x4];
484 u8 hop_limit[0x8];
485
486 u8 reserved_at_60[0x4];
487 u8 tclass[0x8];
488 u8 flow_label[0x14];
489
490 u8 rgid_rip[16][0x8];
491
492 u8 reserved_at_100[0x4];
493 u8 f_dscp[0x1];
494 u8 f_ecn[0x1];
495 u8 reserved_at_106[0x1];
496 u8 f_eth_prio[0x1];
497 u8 ecn[0x2];
498 u8 dscp[0x6];
499 u8 udp_sport[0x10];
500
501 u8 dei_cfi[0x1];
502 u8 eth_prio[0x3];
503 u8 sl[0x4];
504 u8 port[0x8];
505 u8 rmac_47_32[0x10];
506
507 u8 rmac_31_0[0x20];
508};
509
510struct mlx5_ifc_flow_table_nic_cap_bits {
511 u8 nic_rx_multi_path_tirs[0x1];
512 u8 nic_rx_multi_path_tirs_fts[0x1];
513 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
514 u8 reserved_at_3[0x1fd];
515
516 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
517
518 u8 reserved_at_400[0x200];
519
520 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
521
522 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
523
524 u8 reserved_at_a00[0x200];
525
526 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
527
528 u8 reserved_at_e00[0x7200];
529};
530
531struct mlx5_ifc_flow_table_eswitch_cap_bits {
532 u8 reserved_at_0[0x200];
533
534 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
535
536 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
537
538 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
539
540 u8 reserved_at_800[0x7800];
541};
542
543struct mlx5_ifc_e_switch_cap_bits {
544 u8 vport_svlan_strip[0x1];
545 u8 vport_cvlan_strip[0x1];
546 u8 vport_svlan_insert[0x1];
547 u8 vport_cvlan_insert_if_not_exist[0x1];
548 u8 vport_cvlan_insert_overwrite[0x1];
549 u8 reserved_at_5[0x19];
550 u8 nic_vport_node_guid_modify[0x1];
551 u8 nic_vport_port_guid_modify[0x1];
552
553 u8 vxlan_encap_decap[0x1];
554 u8 nvgre_encap_decap[0x1];
555 u8 reserved_at_22[0x9];
556 u8 log_max_encap_headers[0x5];
557 u8 reserved_2b[0x6];
558 u8 max_encap_header_size[0xa];
559
560 u8 reserved_40[0x7c0];
561
562};
563
564struct mlx5_ifc_qos_cap_bits {
565 u8 packet_pacing[0x1];
566 u8 esw_scheduling[0x1];
567 u8 esw_bw_share[0x1];
568 u8 esw_rate_limit[0x1];
569 u8 reserved_at_4[0x1c];
570
571 u8 reserved_at_20[0x20];
572
573 u8 packet_pacing_max_rate[0x20];
574
575 u8 packet_pacing_min_rate[0x20];
576
577 u8 reserved_at_80[0x10];
578 u8 packet_pacing_rate_table_size[0x10];
579
580 u8 esw_element_type[0x10];
581 u8 esw_tsar_type[0x10];
582
583 u8 reserved_at_c0[0x10];
584 u8 max_qos_para_vport[0x10];
585
586 u8 max_tsar_bw_share[0x20];
587
588 u8 reserved_at_100[0x700];
589};
590
591struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
592 u8 csum_cap[0x1];
593 u8 vlan_cap[0x1];
594 u8 lro_cap[0x1];
595 u8 lro_psh_flag[0x1];
596 u8 lro_time_stamp[0x1];
597 u8 reserved_at_5[0x2];
598 u8 wqe_vlan_insert[0x1];
599 u8 self_lb_en_modifiable[0x1];
600 u8 reserved_at_9[0x2];
601 u8 max_lso_cap[0x5];
602 u8 multi_pkt_send_wqe[0x2];
603 u8 wqe_inline_mode[0x2];
604 u8 rss_ind_tbl_cap[0x4];
605 u8 reg_umr_sq[0x1];
606 u8 scatter_fcs[0x1];
607 u8 enhanced_multi_pkt_send_wqe[0x1];
608 u8 tunnel_lso_const_out_ip_id[0x1];
609 u8 reserved_at_1c[0x2];
610 u8 tunnel_stateless_gre[0x1];
611 u8 tunnel_stateless_vxlan[0x1];
612
613 u8 swp[0x1];
614 u8 swp_csum[0x1];
615 u8 swp_lso[0x1];
616 u8 reserved_at_23[0x1d];
617
618 u8 reserved_at_40[0x10];
619 u8 lro_min_mss_size[0x10];
620
621 u8 reserved_at_60[0x120];
622
623 u8 lro_timer_supported_periods[4][0x20];
624
625 u8 reserved_at_200[0x600];
626};
627
628struct mlx5_ifc_roce_cap_bits {
629 u8 roce_apm[0x1];
630 u8 reserved_at_1[0x1f];
631
632 u8 reserved_at_20[0x60];
633
634 u8 reserved_at_80[0xc];
635 u8 l3_type[0x4];
636 u8 reserved_at_90[0x8];
637 u8 roce_version[0x8];
638
639 u8 reserved_at_a0[0x10];
640 u8 r_roce_dest_udp_port[0x10];
641
642 u8 r_roce_max_src_udp_port[0x10];
643 u8 r_roce_min_src_udp_port[0x10];
644
645 u8 reserved_at_e0[0x10];
646 u8 roce_address_table_size[0x10];
647
648 u8 reserved_at_100[0x700];
649};
650
651enum {
652 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
653 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
654 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
655 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
656 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
657 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
658 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
659 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
660 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
661};
662
663enum {
664 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
665 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
666 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
667 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
668 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
669 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
670 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
671 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
672 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
673};
674
675struct mlx5_ifc_atomic_caps_bits {
676 u8 reserved_at_0[0x40];
677
678 u8 atomic_req_8B_endianness_mode[0x2];
679 u8 reserved_at_42[0x4];
680 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
681
682 u8 reserved_at_47[0x19];
683
684 u8 reserved_at_60[0x20];
685
686 u8 reserved_at_80[0x10];
687 u8 atomic_operations[0x10];
688
689 u8 reserved_at_a0[0x10];
690 u8 atomic_size_qp[0x10];
691
692 u8 reserved_at_c0[0x10];
693 u8 atomic_size_dc[0x10];
694
695 u8 reserved_at_e0[0x720];
696};
697
698struct mlx5_ifc_odp_cap_bits {
699 u8 reserved_at_0[0x40];
700
701 u8 sig[0x1];
702 u8 reserved_at_41[0x1f];
703
704 u8 reserved_at_60[0x20];
705
706 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
707
708 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
709
710 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
711
712 u8 reserved_at_e0[0x720];
713};
714
715struct mlx5_ifc_calc_op {
716 u8 reserved_at_0[0x10];
717 u8 reserved_at_10[0x9];
718 u8 op_swap_endianness[0x1];
719 u8 op_min[0x1];
720 u8 op_xor[0x1];
721 u8 op_or[0x1];
722 u8 op_and[0x1];
723 u8 op_max[0x1];
724 u8 op_add[0x1];
725};
726
727struct mlx5_ifc_vector_calc_cap_bits {
728 u8 calc_matrix[0x1];
729 u8 reserved_at_1[0x1f];
730 u8 reserved_at_20[0x8];
731 u8 max_vec_count[0x8];
732 u8 reserved_at_30[0xd];
733 u8 max_chunk_size[0x3];
734 struct mlx5_ifc_calc_op calc0;
735 struct mlx5_ifc_calc_op calc1;
736 struct mlx5_ifc_calc_op calc2;
737 struct mlx5_ifc_calc_op calc3;
738
739 u8 reserved_at_e0[0x720];
740};
741
742enum {
743 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
744 MLX5_WQ_TYPE_CYCLIC = 0x1,
745 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
746};
747
748enum {
749 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
750 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
751};
752
753enum {
754 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
755 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
756 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
757 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
758 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
759};
760
761enum {
762 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
763 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
764 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
765 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
766 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
767 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
768};
769
770enum {
771 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
772 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
773};
774
775enum {
776 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
777 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
778 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
779};
780
781enum {
782 MLX5_CAP_PORT_TYPE_IB = 0x0,
783 MLX5_CAP_PORT_TYPE_ETH = 0x1,
784};
785
786enum {
787 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
788 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
789 MLX5_CAP_UMR_FENCE_NONE = 0x2,
790};
791
792struct mlx5_ifc_cmd_hca_cap_bits {
793 u8 reserved_at_0[0x80];
794
795 u8 log_max_srq_sz[0x8];
796 u8 log_max_qp_sz[0x8];
797 u8 reserved_at_90[0xb];
798 u8 log_max_qp[0x5];
799
800 u8 reserved_at_a0[0xb];
801 u8 log_max_srq[0x5];
802 u8 reserved_at_b0[0x10];
803
804 u8 reserved_at_c0[0x8];
805 u8 log_max_cq_sz[0x8];
806 u8 reserved_at_d0[0xb];
807 u8 log_max_cq[0x5];
808
809 u8 log_max_eq_sz[0x8];
810 u8 reserved_at_e8[0x2];
811 u8 log_max_mkey[0x6];
812 u8 reserved_at_f0[0xc];
813 u8 log_max_eq[0x4];
814
815 u8 max_indirection[0x8];
816 u8 fixed_buffer_size[0x1];
817 u8 log_max_mrw_sz[0x7];
818 u8 force_teardown[0x1];
819 u8 reserved_at_111[0x1];
820 u8 log_max_bsf_list_size[0x6];
821 u8 umr_extended_translation_offset[0x1];
822 u8 null_mkey[0x1];
823 u8 log_max_klm_list_size[0x6];
824
825 u8 reserved_at_120[0xa];
826 u8 log_max_ra_req_dc[0x6];
827 u8 reserved_at_130[0xa];
828 u8 log_max_ra_res_dc[0x6];
829
830 u8 reserved_at_140[0xa];
831 u8 log_max_ra_req_qp[0x6];
832 u8 reserved_at_150[0xa];
833 u8 log_max_ra_res_qp[0x6];
834
835 u8 end_pad[0x1];
836 u8 cc_query_allowed[0x1];
837 u8 cc_modify_allowed[0x1];
838 u8 start_pad[0x1];
839 u8 cache_line_128byte[0x1];
840 u8 reserved_at_165[0xb];
841 u8 gid_table_size[0x10];
842
843 u8 out_of_seq_cnt[0x1];
844 u8 vport_counters[0x1];
845 u8 retransmission_q_counters[0x1];
846 u8 reserved_at_183[0x1];
847 u8 modify_rq_counter_set_id[0x1];
848 u8 rq_delay_drop[0x1];
849 u8 max_qp_cnt[0xa];
850 u8 pkey_table_size[0x10];
851
852 u8 vport_group_manager[0x1];
853 u8 vhca_group_manager[0x1];
854 u8 ib_virt[0x1];
855 u8 eth_virt[0x1];
856 u8 reserved_at_1a4[0x1];
857 u8 ets[0x1];
858 u8 nic_flow_table[0x1];
859 u8 eswitch_flow_table[0x1];
860 u8 early_vf_enable[0x1];
861 u8 mcam_reg[0x1];
862 u8 pcam_reg[0x1];
863 u8 local_ca_ack_delay[0x5];
864 u8 port_module_event[0x1];
865 u8 enhanced_error_q_counters[0x1];
866 u8 ports_check[0x1];
867 u8 reserved_at_1b3[0x1];
868 u8 disable_link_up[0x1];
869 u8 beacon_led[0x1];
870 u8 port_type[0x2];
871 u8 num_ports[0x8];
872
873 u8 reserved_at_1c0[0x1];
874 u8 pps[0x1];
875 u8 pps_modify[0x1];
876 u8 log_max_msg[0x5];
877 u8 reserved_at_1c8[0x4];
878 u8 max_tc[0x4];
879 u8 reserved_at_1d0[0x1];
880 u8 dcbx[0x1];
881 u8 general_notification_event[0x1];
882 u8 reserved_at_1d3[0x2];
883 u8 fpga[0x1];
884 u8 rol_s[0x1];
885 u8 rol_g[0x1];
886 u8 reserved_at_1d8[0x1];
887 u8 wol_s[0x1];
888 u8 wol_g[0x1];
889 u8 wol_a[0x1];
890 u8 wol_b[0x1];
891 u8 wol_m[0x1];
892 u8 wol_u[0x1];
893 u8 wol_p[0x1];
894
895 u8 stat_rate_support[0x10];
896 u8 reserved_at_1f0[0xc];
897 u8 cqe_version[0x4];
898
899 u8 compact_address_vector[0x1];
900 u8 striding_rq[0x1];
901 u8 reserved_at_202[0x1];
902 u8 ipoib_enhanced_offloads[0x1];
903 u8 ipoib_basic_offloads[0x1];
904 u8 reserved_at_205[0x5];
905 u8 umr_fence[0x2];
906 u8 reserved_at_20c[0x3];
907 u8 drain_sigerr[0x1];
908 u8 cmdif_checksum[0x2];
909 u8 sigerr_cqe[0x1];
910 u8 reserved_at_213[0x1];
911 u8 wq_signature[0x1];
912 u8 sctr_data_cqe[0x1];
913 u8 reserved_at_216[0x1];
914 u8 sho[0x1];
915 u8 tph[0x1];
916 u8 rf[0x1];
917 u8 dct[0x1];
918 u8 qos[0x1];
919 u8 eth_net_offloads[0x1];
920 u8 roce[0x1];
921 u8 atomic[0x1];
922 u8 reserved_at_21f[0x1];
923
924 u8 cq_oi[0x1];
925 u8 cq_resize[0x1];
926 u8 cq_moderation[0x1];
927 u8 reserved_at_223[0x3];
928 u8 cq_eq_remap[0x1];
929 u8 pg[0x1];
930 u8 block_lb_mc[0x1];
931 u8 reserved_at_229[0x1];
932 u8 scqe_break_moderation[0x1];
933 u8 cq_period_start_from_cqe[0x1];
934 u8 cd[0x1];
935 u8 reserved_at_22d[0x1];
936 u8 apm[0x1];
937 u8 vector_calc[0x1];
938 u8 umr_ptr_rlky[0x1];
939 u8 imaicl[0x1];
940 u8 reserved_at_232[0x4];
941 u8 qkv[0x1];
942 u8 pkv[0x1];
943 u8 set_deth_sqpn[0x1];
944 u8 reserved_at_239[0x3];
945 u8 xrc[0x1];
946 u8 ud[0x1];
947 u8 uc[0x1];
948 u8 rc[0x1];
949
950 u8 uar_4k[0x1];
951 u8 reserved_at_241[0x9];
952 u8 uar_sz[0x6];
953 u8 reserved_at_250[0x8];
954 u8 log_pg_sz[0x8];
955
956 u8 bf[0x1];
957 u8 driver_version[0x1];
958 u8 pad_tx_eth_packet[0x1];
959 u8 reserved_at_263[0x8];
960 u8 log_bf_reg_size[0x5];
961
962 u8 reserved_at_270[0xb];
963 u8 lag_master[0x1];
964 u8 num_lag_ports[0x4];
965
966 u8 reserved_at_280[0x10];
967 u8 max_wqe_sz_sq[0x10];
968
969 u8 reserved_at_2a0[0x10];
970 u8 max_wqe_sz_rq[0x10];
971
972 u8 max_flow_counter_31_16[0x10];
973 u8 max_wqe_sz_sq_dc[0x10];
974
975 u8 reserved_at_2e0[0x7];
976 u8 max_qp_mcg[0x19];
977
978 u8 reserved_at_300[0x18];
979 u8 log_max_mcg[0x8];
980
981 u8 reserved_at_320[0x3];
982 u8 log_max_transport_domain[0x5];
983 u8 reserved_at_328[0x3];
984 u8 log_max_pd[0x5];
985 u8 reserved_at_330[0xb];
986 u8 log_max_xrcd[0x5];
987
988 u8 reserved_at_340[0x8];
989 u8 log_max_flow_counter_bulk[0x8];
990 u8 max_flow_counter_15_0[0x10];
991
992
993 u8 reserved_at_360[0x3];
994 u8 log_max_rq[0x5];
995 u8 reserved_at_368[0x3];
996 u8 log_max_sq[0x5];
997 u8 reserved_at_370[0x3];
998 u8 log_max_tir[0x5];
999 u8 reserved_at_378[0x3];
1000 u8 log_max_tis[0x5];
1001
1002 u8 basic_cyclic_rcv_wqe[0x1];
1003 u8 reserved_at_381[0x2];
1004 u8 log_max_rmp[0x5];
1005 u8 reserved_at_388[0x3];
1006 u8 log_max_rqt[0x5];
1007 u8 reserved_at_390[0x3];
1008 u8 log_max_rqt_size[0x5];
1009 u8 reserved_at_398[0x3];
1010 u8 log_max_tis_per_sq[0x5];
1011
1012 u8 reserved_at_3a0[0x3];
1013 u8 log_max_stride_sz_rq[0x5];
1014 u8 reserved_at_3a8[0x3];
1015 u8 log_min_stride_sz_rq[0x5];
1016 u8 reserved_at_3b0[0x3];
1017 u8 log_max_stride_sz_sq[0x5];
1018 u8 reserved_at_3b8[0x3];
1019 u8 log_min_stride_sz_sq[0x5];
1020
1021 u8 reserved_at_3c0[0x1b];
1022 u8 log_max_wq_sz[0x5];
1023
1024 u8 nic_vport_change_event[0x1];
1025 u8 disable_local_lb[0x1];
1026 u8 reserved_at_3e2[0x9];
1027 u8 log_max_vlan_list[0x5];
1028 u8 reserved_at_3f0[0x3];
1029 u8 log_max_current_mc_list[0x5];
1030 u8 reserved_at_3f8[0x3];
1031 u8 log_max_current_uc_list[0x5];
1032
1033 u8 reserved_at_400[0x80];
1034
1035 u8 reserved_at_480[0x3];
1036 u8 log_max_l2_table[0x5];
1037 u8 reserved_at_488[0x8];
1038 u8 log_uar_page_sz[0x10];
1039
1040 u8 reserved_at_4a0[0x20];
1041 u8 device_frequency_mhz[0x20];
1042 u8 device_frequency_khz[0x20];
1043
1044 u8 reserved_at_500[0x20];
1045 u8 num_of_uars_per_page[0x20];
1046 u8 reserved_at_540[0x40];
1047
1048 u8 reserved_at_580[0x3f];
1049 u8 cqe_compression[0x1];
1050
1051 u8 cqe_compression_timeout[0x10];
1052 u8 cqe_compression_max_num[0x10];
1053
1054 u8 reserved_at_5e0[0x10];
1055 u8 tag_matching[0x1];
1056 u8 rndv_offload_rc[0x1];
1057 u8 rndv_offload_dc[0x1];
1058 u8 log_tag_matching_list_sz[0x5];
1059 u8 reserved_at_5f8[0x3];
1060 u8 log_max_xrq[0x5];
1061
1062 u8 reserved_at_600[0x200];
1063};
1064
1065enum mlx5_flow_destination_type {
1066 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1067 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1068 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1069
1070 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1071};
1072
1073struct mlx5_ifc_dest_format_struct_bits {
1074 u8 destination_type[0x8];
1075 u8 destination_id[0x18];
1076
1077 u8 reserved_at_20[0x20];
1078};
1079
1080struct mlx5_ifc_flow_counter_list_bits {
1081 u8 flow_counter_id[0x20];
1082
1083 u8 reserved_at_20[0x20];
1084};
1085
1086union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1087 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1088 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1089 u8 reserved_at_0[0x40];
1090};
1091
1092struct mlx5_ifc_fte_match_param_bits {
1093 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1094
1095 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1096
1097 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1098
1099 u8 reserved_at_600[0xa00];
1100};
1101
1102enum {
1103 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1104 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1105 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1106 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1107 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1108};
1109
1110struct mlx5_ifc_rx_hash_field_select_bits {
1111 u8 l3_prot_type[0x1];
1112 u8 l4_prot_type[0x1];
1113 u8 selected_fields[0x1e];
1114};
1115
1116enum {
1117 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1118 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1119};
1120
1121enum {
1122 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1123 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1124};
1125
1126struct mlx5_ifc_wq_bits {
1127 u8 wq_type[0x4];
1128 u8 wq_signature[0x1];
1129 u8 end_padding_mode[0x2];
1130 u8 cd_slave[0x1];
1131 u8 reserved_at_8[0x18];
1132
1133 u8 hds_skip_first_sge[0x1];
1134 u8 log2_hds_buf_size[0x3];
1135 u8 reserved_at_24[0x7];
1136 u8 page_offset[0x5];
1137 u8 lwm[0x10];
1138
1139 u8 reserved_at_40[0x8];
1140 u8 pd[0x18];
1141
1142 u8 reserved_at_60[0x8];
1143 u8 uar_page[0x18];
1144
1145 u8 dbr_addr[0x40];
1146
1147 u8 hw_counter[0x20];
1148
1149 u8 sw_counter[0x20];
1150
1151 u8 reserved_at_100[0xc];
1152 u8 log_wq_stride[0x4];
1153 u8 reserved_at_110[0x3];
1154 u8 log_wq_pg_sz[0x5];
1155 u8 reserved_at_118[0x3];
1156 u8 log_wq_sz[0x5];
1157
1158 u8 reserved_at_120[0x15];
1159 u8 log_wqe_num_of_strides[0x3];
1160 u8 two_byte_shift_en[0x1];
1161 u8 reserved_at_139[0x4];
1162 u8 log_wqe_stride_size[0x3];
1163
1164 u8 reserved_at_140[0x4c0];
1165
1166 struct mlx5_ifc_cmd_pas_bits pas[0];
1167};
1168
1169struct mlx5_ifc_rq_num_bits {
1170 u8 reserved_at_0[0x8];
1171 u8 rq_num[0x18];
1172};
1173
1174struct mlx5_ifc_mac_address_layout_bits {
1175 u8 reserved_at_0[0x10];
1176 u8 mac_addr_47_32[0x10];
1177
1178 u8 mac_addr_31_0[0x20];
1179};
1180
1181struct mlx5_ifc_vlan_layout_bits {
1182 u8 reserved_at_0[0x14];
1183 u8 vlan[0x0c];
1184
1185 u8 reserved_at_20[0x20];
1186};
1187
1188struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1189 u8 reserved_at_0[0xa0];
1190
1191 u8 min_time_between_cnps[0x20];
1192
1193 u8 reserved_at_c0[0x12];
1194 u8 cnp_dscp[0x6];
1195 u8 reserved_at_d8[0x4];
1196 u8 cnp_prio_mode[0x1];
1197 u8 cnp_802p_prio[0x3];
1198
1199 u8 reserved_at_e0[0x720];
1200};
1201
1202struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1203 u8 reserved_at_0[0x60];
1204
1205 u8 reserved_at_60[0x4];
1206 u8 clamp_tgt_rate[0x1];
1207 u8 reserved_at_65[0x3];
1208 u8 clamp_tgt_rate_after_time_inc[0x1];
1209 u8 reserved_at_69[0x17];
1210
1211 u8 reserved_at_80[0x20];
1212
1213 u8 rpg_time_reset[0x20];
1214
1215 u8 rpg_byte_reset[0x20];
1216
1217 u8 rpg_threshold[0x20];
1218
1219 u8 rpg_max_rate[0x20];
1220
1221 u8 rpg_ai_rate[0x20];
1222
1223 u8 rpg_hai_rate[0x20];
1224
1225 u8 rpg_gd[0x20];
1226
1227 u8 rpg_min_dec_fac[0x20];
1228
1229 u8 rpg_min_rate[0x20];
1230
1231 u8 reserved_at_1c0[0xe0];
1232
1233 u8 rate_to_set_on_first_cnp[0x20];
1234
1235 u8 dce_tcp_g[0x20];
1236
1237 u8 dce_tcp_rtt[0x20];
1238
1239 u8 rate_reduce_monitor_period[0x20];
1240
1241 u8 reserved_at_320[0x20];
1242
1243 u8 initial_alpha_value[0x20];
1244
1245 u8 reserved_at_360[0x4a0];
1246};
1247
1248struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1249 u8 reserved_at_0[0x80];
1250
1251 u8 rppp_max_rps[0x20];
1252
1253 u8 rpg_time_reset[0x20];
1254
1255 u8 rpg_byte_reset[0x20];
1256
1257 u8 rpg_threshold[0x20];
1258
1259 u8 rpg_max_rate[0x20];
1260
1261 u8 rpg_ai_rate[0x20];
1262
1263 u8 rpg_hai_rate[0x20];
1264
1265 u8 rpg_gd[0x20];
1266
1267 u8 rpg_min_dec_fac[0x20];
1268
1269 u8 rpg_min_rate[0x20];
1270
1271 u8 reserved_at_1c0[0x640];
1272};
1273
1274enum {
1275 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1276 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1277 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1278};
1279
1280struct mlx5_ifc_resize_field_select_bits {
1281 u8 resize_field_select[0x20];
1282};
1283
1284enum {
1285 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1286 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1287 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1288 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1289};
1290
1291struct mlx5_ifc_modify_field_select_bits {
1292 u8 modify_field_select[0x20];
1293};
1294
1295struct mlx5_ifc_field_select_r_roce_np_bits {
1296 u8 field_select_r_roce_np[0x20];
1297};
1298
1299struct mlx5_ifc_field_select_r_roce_rp_bits {
1300 u8 field_select_r_roce_rp[0x20];
1301};
1302
1303enum {
1304 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1305 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1306 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1307 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1308 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1309 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1310 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1311 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1312 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1313 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1314};
1315
1316struct mlx5_ifc_field_select_802_1qau_rp_bits {
1317 u8 field_select_8021qaurp[0x20];
1318};
1319
1320struct mlx5_ifc_phys_layer_cntrs_bits {
1321 u8 time_since_last_clear_high[0x20];
1322
1323 u8 time_since_last_clear_low[0x20];
1324
1325 u8 symbol_errors_high[0x20];
1326
1327 u8 symbol_errors_low[0x20];
1328
1329 u8 sync_headers_errors_high[0x20];
1330
1331 u8 sync_headers_errors_low[0x20];
1332
1333 u8 edpl_bip_errors_lane0_high[0x20];
1334
1335 u8 edpl_bip_errors_lane0_low[0x20];
1336
1337 u8 edpl_bip_errors_lane1_high[0x20];
1338
1339 u8 edpl_bip_errors_lane1_low[0x20];
1340
1341 u8 edpl_bip_errors_lane2_high[0x20];
1342
1343 u8 edpl_bip_errors_lane2_low[0x20];
1344
1345 u8 edpl_bip_errors_lane3_high[0x20];
1346
1347 u8 edpl_bip_errors_lane3_low[0x20];
1348
1349 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1350
1351 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1352
1353 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1354
1355 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1356
1357 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1358
1359 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1360
1361 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1362
1363 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1364
1365 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1366
1367 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1368
1369 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1370
1371 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1372
1373 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1374
1375 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1376
1377 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1378
1379 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1380
1381 u8 rs_fec_corrected_blocks_high[0x20];
1382
1383 u8 rs_fec_corrected_blocks_low[0x20];
1384
1385 u8 rs_fec_uncorrectable_blocks_high[0x20];
1386
1387 u8 rs_fec_uncorrectable_blocks_low[0x20];
1388
1389 u8 rs_fec_no_errors_blocks_high[0x20];
1390
1391 u8 rs_fec_no_errors_blocks_low[0x20];
1392
1393 u8 rs_fec_single_error_blocks_high[0x20];
1394
1395 u8 rs_fec_single_error_blocks_low[0x20];
1396
1397 u8 rs_fec_corrected_symbols_total_high[0x20];
1398
1399 u8 rs_fec_corrected_symbols_total_low[0x20];
1400
1401 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1402
1403 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1404
1405 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1406
1407 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1408
1409 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1410
1411 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1412
1413 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1414
1415 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1416
1417 u8 link_down_events[0x20];
1418
1419 u8 successful_recovery_events[0x20];
1420
1421 u8 reserved_at_640[0x180];
1422};
1423
1424struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1425 u8 time_since_last_clear_high[0x20];
1426
1427 u8 time_since_last_clear_low[0x20];
1428
1429 u8 phy_received_bits_high[0x20];
1430
1431 u8 phy_received_bits_low[0x20];
1432
1433 u8 phy_symbol_errors_high[0x20];
1434
1435 u8 phy_symbol_errors_low[0x20];
1436
1437 u8 phy_corrected_bits_high[0x20];
1438
1439 u8 phy_corrected_bits_low[0x20];
1440
1441 u8 phy_corrected_bits_lane0_high[0x20];
1442
1443 u8 phy_corrected_bits_lane0_low[0x20];
1444
1445 u8 phy_corrected_bits_lane1_high[0x20];
1446
1447 u8 phy_corrected_bits_lane1_low[0x20];
1448
1449 u8 phy_corrected_bits_lane2_high[0x20];
1450
1451 u8 phy_corrected_bits_lane2_low[0x20];
1452
1453 u8 phy_corrected_bits_lane3_high[0x20];
1454
1455 u8 phy_corrected_bits_lane3_low[0x20];
1456
1457 u8 reserved_at_200[0x5c0];
1458};
1459
1460struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1461 u8 symbol_error_counter[0x10];
1462
1463 u8 link_error_recovery_counter[0x8];
1464
1465 u8 link_downed_counter[0x8];
1466
1467 u8 port_rcv_errors[0x10];
1468
1469 u8 port_rcv_remote_physical_errors[0x10];
1470
1471 u8 port_rcv_switch_relay_errors[0x10];
1472
1473 u8 port_xmit_discards[0x10];
1474
1475 u8 port_xmit_constraint_errors[0x8];
1476
1477 u8 port_rcv_constraint_errors[0x8];
1478
1479 u8 reserved_at_70[0x8];
1480
1481 u8 link_overrun_errors[0x8];
1482
1483 u8 reserved_at_80[0x10];
1484
1485 u8 vl_15_dropped[0x10];
1486
1487 u8 reserved_at_a0[0x80];
1488
1489 u8 port_xmit_wait[0x20];
1490};
1491
1492struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1493 u8 transmit_queue_high[0x20];
1494
1495 u8 transmit_queue_low[0x20];
1496
1497 u8 reserved_at_40[0x780];
1498};
1499
1500struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1501 u8 rx_octets_high[0x20];
1502
1503 u8 rx_octets_low[0x20];
1504
1505 u8 reserved_at_40[0xc0];
1506
1507 u8 rx_frames_high[0x20];
1508
1509 u8 rx_frames_low[0x20];
1510
1511 u8 tx_octets_high[0x20];
1512
1513 u8 tx_octets_low[0x20];
1514
1515 u8 reserved_at_180[0xc0];
1516
1517 u8 tx_frames_high[0x20];
1518
1519 u8 tx_frames_low[0x20];
1520
1521 u8 rx_pause_high[0x20];
1522
1523 u8 rx_pause_low[0x20];
1524
1525 u8 rx_pause_duration_high[0x20];
1526
1527 u8 rx_pause_duration_low[0x20];
1528
1529 u8 tx_pause_high[0x20];
1530
1531 u8 tx_pause_low[0x20];
1532
1533 u8 tx_pause_duration_high[0x20];
1534
1535 u8 tx_pause_duration_low[0x20];
1536
1537 u8 rx_pause_transition_high[0x20];
1538
1539 u8 rx_pause_transition_low[0x20];
1540
1541 u8 reserved_at_3c0[0x400];
1542};
1543
1544struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1545 u8 port_transmit_wait_high[0x20];
1546
1547 u8 port_transmit_wait_low[0x20];
1548
1549 u8 reserved_at_40[0x100];
1550
1551 u8 rx_buffer_almost_full_high[0x20];
1552
1553 u8 rx_buffer_almost_full_low[0x20];
1554
1555 u8 rx_buffer_full_high[0x20];
1556
1557 u8 rx_buffer_full_low[0x20];
1558
1559 u8 reserved_at_1c0[0x600];
1560};
1561
1562struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1563 u8 dot3stats_alignment_errors_high[0x20];
1564
1565 u8 dot3stats_alignment_errors_low[0x20];
1566
1567 u8 dot3stats_fcs_errors_high[0x20];
1568
1569 u8 dot3stats_fcs_errors_low[0x20];
1570
1571 u8 dot3stats_single_collision_frames_high[0x20];
1572
1573 u8 dot3stats_single_collision_frames_low[0x20];
1574
1575 u8 dot3stats_multiple_collision_frames_high[0x20];
1576
1577 u8 dot3stats_multiple_collision_frames_low[0x20];
1578
1579 u8 dot3stats_sqe_test_errors_high[0x20];
1580
1581 u8 dot3stats_sqe_test_errors_low[0x20];
1582
1583 u8 dot3stats_deferred_transmissions_high[0x20];
1584
1585 u8 dot3stats_deferred_transmissions_low[0x20];
1586
1587 u8 dot3stats_late_collisions_high[0x20];
1588
1589 u8 dot3stats_late_collisions_low[0x20];
1590
1591 u8 dot3stats_excessive_collisions_high[0x20];
1592
1593 u8 dot3stats_excessive_collisions_low[0x20];
1594
1595 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1596
1597 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1598
1599 u8 dot3stats_carrier_sense_errors_high[0x20];
1600
1601 u8 dot3stats_carrier_sense_errors_low[0x20];
1602
1603 u8 dot3stats_frame_too_longs_high[0x20];
1604
1605 u8 dot3stats_frame_too_longs_low[0x20];
1606
1607 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1608
1609 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1610
1611 u8 dot3stats_symbol_errors_high[0x20];
1612
1613 u8 dot3stats_symbol_errors_low[0x20];
1614
1615 u8 dot3control_in_unknown_opcodes_high[0x20];
1616
1617 u8 dot3control_in_unknown_opcodes_low[0x20];
1618
1619 u8 dot3in_pause_frames_high[0x20];
1620
1621 u8 dot3in_pause_frames_low[0x20];
1622
1623 u8 dot3out_pause_frames_high[0x20];
1624
1625 u8 dot3out_pause_frames_low[0x20];
1626
1627 u8 reserved_at_400[0x3c0];
1628};
1629
1630struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1631 u8 ether_stats_drop_events_high[0x20];
1632
1633 u8 ether_stats_drop_events_low[0x20];
1634
1635 u8 ether_stats_octets_high[0x20];
1636
1637 u8 ether_stats_octets_low[0x20];
1638
1639 u8 ether_stats_pkts_high[0x20];
1640
1641 u8 ether_stats_pkts_low[0x20];
1642
1643 u8 ether_stats_broadcast_pkts_high[0x20];
1644
1645 u8 ether_stats_broadcast_pkts_low[0x20];
1646
1647 u8 ether_stats_multicast_pkts_high[0x20];
1648
1649 u8 ether_stats_multicast_pkts_low[0x20];
1650
1651 u8 ether_stats_crc_align_errors_high[0x20];
1652
1653 u8 ether_stats_crc_align_errors_low[0x20];
1654
1655 u8 ether_stats_undersize_pkts_high[0x20];
1656
1657 u8 ether_stats_undersize_pkts_low[0x20];
1658
1659 u8 ether_stats_oversize_pkts_high[0x20];
1660
1661 u8 ether_stats_oversize_pkts_low[0x20];
1662
1663 u8 ether_stats_fragments_high[0x20];
1664
1665 u8 ether_stats_fragments_low[0x20];
1666
1667 u8 ether_stats_jabbers_high[0x20];
1668
1669 u8 ether_stats_jabbers_low[0x20];
1670
1671 u8 ether_stats_collisions_high[0x20];
1672
1673 u8 ether_stats_collisions_low[0x20];
1674
1675 u8 ether_stats_pkts64octets_high[0x20];
1676
1677 u8 ether_stats_pkts64octets_low[0x20];
1678
1679 u8 ether_stats_pkts65to127octets_high[0x20];
1680
1681 u8 ether_stats_pkts65to127octets_low[0x20];
1682
1683 u8 ether_stats_pkts128to255octets_high[0x20];
1684
1685 u8 ether_stats_pkts128to255octets_low[0x20];
1686
1687 u8 ether_stats_pkts256to511octets_high[0x20];
1688
1689 u8 ether_stats_pkts256to511octets_low[0x20];
1690
1691 u8 ether_stats_pkts512to1023octets_high[0x20];
1692
1693 u8 ether_stats_pkts512to1023octets_low[0x20];
1694
1695 u8 ether_stats_pkts1024to1518octets_high[0x20];
1696
1697 u8 ether_stats_pkts1024to1518octets_low[0x20];
1698
1699 u8 ether_stats_pkts1519to2047octets_high[0x20];
1700
1701 u8 ether_stats_pkts1519to2047octets_low[0x20];
1702
1703 u8 ether_stats_pkts2048to4095octets_high[0x20];
1704
1705 u8 ether_stats_pkts2048to4095octets_low[0x20];
1706
1707 u8 ether_stats_pkts4096to8191octets_high[0x20];
1708
1709 u8 ether_stats_pkts4096to8191octets_low[0x20];
1710
1711 u8 ether_stats_pkts8192to10239octets_high[0x20];
1712
1713 u8 ether_stats_pkts8192to10239octets_low[0x20];
1714
1715 u8 reserved_at_540[0x280];
1716};
1717
1718struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1719 u8 if_in_octets_high[0x20];
1720
1721 u8 if_in_octets_low[0x20];
1722
1723 u8 if_in_ucast_pkts_high[0x20];
1724
1725 u8 if_in_ucast_pkts_low[0x20];
1726
1727 u8 if_in_discards_high[0x20];
1728
1729 u8 if_in_discards_low[0x20];
1730
1731 u8 if_in_errors_high[0x20];
1732
1733 u8 if_in_errors_low[0x20];
1734
1735 u8 if_in_unknown_protos_high[0x20];
1736
1737 u8 if_in_unknown_protos_low[0x20];
1738
1739 u8 if_out_octets_high[0x20];
1740
1741 u8 if_out_octets_low[0x20];
1742
1743 u8 if_out_ucast_pkts_high[0x20];
1744
1745 u8 if_out_ucast_pkts_low[0x20];
1746
1747 u8 if_out_discards_high[0x20];
1748
1749 u8 if_out_discards_low[0x20];
1750
1751 u8 if_out_errors_high[0x20];
1752
1753 u8 if_out_errors_low[0x20];
1754
1755 u8 if_in_multicast_pkts_high[0x20];
1756
1757 u8 if_in_multicast_pkts_low[0x20];
1758
1759 u8 if_in_broadcast_pkts_high[0x20];
1760
1761 u8 if_in_broadcast_pkts_low[0x20];
1762
1763 u8 if_out_multicast_pkts_high[0x20];
1764
1765 u8 if_out_multicast_pkts_low[0x20];
1766
1767 u8 if_out_broadcast_pkts_high[0x20];
1768
1769 u8 if_out_broadcast_pkts_low[0x20];
1770
1771 u8 reserved_at_340[0x480];
1772};
1773
1774struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1775 u8 a_frames_transmitted_ok_high[0x20];
1776
1777 u8 a_frames_transmitted_ok_low[0x20];
1778
1779 u8 a_frames_received_ok_high[0x20];
1780
1781 u8 a_frames_received_ok_low[0x20];
1782
1783 u8 a_frame_check_sequence_errors_high[0x20];
1784
1785 u8 a_frame_check_sequence_errors_low[0x20];
1786
1787 u8 a_alignment_errors_high[0x20];
1788
1789 u8 a_alignment_errors_low[0x20];
1790
1791 u8 a_octets_transmitted_ok_high[0x20];
1792
1793 u8 a_octets_transmitted_ok_low[0x20];
1794
1795 u8 a_octets_received_ok_high[0x20];
1796
1797 u8 a_octets_received_ok_low[0x20];
1798
1799 u8 a_multicast_frames_xmitted_ok_high[0x20];
1800
1801 u8 a_multicast_frames_xmitted_ok_low[0x20];
1802
1803 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1804
1805 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1806
1807 u8 a_multicast_frames_received_ok_high[0x20];
1808
1809 u8 a_multicast_frames_received_ok_low[0x20];
1810
1811 u8 a_broadcast_frames_received_ok_high[0x20];
1812
1813 u8 a_broadcast_frames_received_ok_low[0x20];
1814
1815 u8 a_in_range_length_errors_high[0x20];
1816
1817 u8 a_in_range_length_errors_low[0x20];
1818
1819 u8 a_out_of_range_length_field_high[0x20];
1820
1821 u8 a_out_of_range_length_field_low[0x20];
1822
1823 u8 a_frame_too_long_errors_high[0x20];
1824
1825 u8 a_frame_too_long_errors_low[0x20];
1826
1827 u8 a_symbol_error_during_carrier_high[0x20];
1828
1829 u8 a_symbol_error_during_carrier_low[0x20];
1830
1831 u8 a_mac_control_frames_transmitted_high[0x20];
1832
1833 u8 a_mac_control_frames_transmitted_low[0x20];
1834
1835 u8 a_mac_control_frames_received_high[0x20];
1836
1837 u8 a_mac_control_frames_received_low[0x20];
1838
1839 u8 a_unsupported_opcodes_received_high[0x20];
1840
1841 u8 a_unsupported_opcodes_received_low[0x20];
1842
1843 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1844
1845 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1846
1847 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1848
1849 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1850
1851 u8 reserved_at_4c0[0x300];
1852};
1853
1854struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1855 u8 life_time_counter_high[0x20];
1856
1857 u8 life_time_counter_low[0x20];
1858
1859 u8 rx_errors[0x20];
1860
1861 u8 tx_errors[0x20];
1862
1863 u8 l0_to_recovery_eieos[0x20];
1864
1865 u8 l0_to_recovery_ts[0x20];
1866
1867 u8 l0_to_recovery_framing[0x20];
1868
1869 u8 l0_to_recovery_retrain[0x20];
1870
1871 u8 crc_error_dllp[0x20];
1872
1873 u8 crc_error_tlp[0x20];
1874
1875 u8 tx_overflow_buffer_pkt_high[0x20];
1876
1877 u8 tx_overflow_buffer_pkt_low[0x20];
1878
1879 u8 outbound_stalled_reads[0x20];
1880
1881 u8 outbound_stalled_writes[0x20];
1882
1883 u8 outbound_stalled_reads_events[0x20];
1884
1885 u8 outbound_stalled_writes_events[0x20];
1886
1887 u8 reserved_at_200[0x5c0];
1888};
1889
1890struct mlx5_ifc_cmd_inter_comp_event_bits {
1891 u8 command_completion_vector[0x20];
1892
1893 u8 reserved_at_20[0xc0];
1894};
1895
1896struct mlx5_ifc_stall_vl_event_bits {
1897 u8 reserved_at_0[0x18];
1898 u8 port_num[0x1];
1899 u8 reserved_at_19[0x3];
1900 u8 vl[0x4];
1901
1902 u8 reserved_at_20[0xa0];
1903};
1904
1905struct mlx5_ifc_db_bf_congestion_event_bits {
1906 u8 event_subtype[0x8];
1907 u8 reserved_at_8[0x8];
1908 u8 congestion_level[0x8];
1909 u8 reserved_at_18[0x8];
1910
1911 u8 reserved_at_20[0xa0];
1912};
1913
1914struct mlx5_ifc_gpio_event_bits {
1915 u8 reserved_at_0[0x60];
1916
1917 u8 gpio_event_hi[0x20];
1918
1919 u8 gpio_event_lo[0x20];
1920
1921 u8 reserved_at_a0[0x40];
1922};
1923
1924struct mlx5_ifc_port_state_change_event_bits {
1925 u8 reserved_at_0[0x40];
1926
1927 u8 port_num[0x4];
1928 u8 reserved_at_44[0x1c];
1929
1930 u8 reserved_at_60[0x80];
1931};
1932
1933struct mlx5_ifc_dropped_packet_logged_bits {
1934 u8 reserved_at_0[0xe0];
1935};
1936
1937enum {
1938 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1939 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1940};
1941
1942struct mlx5_ifc_cq_error_bits {
1943 u8 reserved_at_0[0x8];
1944 u8 cqn[0x18];
1945
1946 u8 reserved_at_20[0x20];
1947
1948 u8 reserved_at_40[0x18];
1949 u8 syndrome[0x8];
1950
1951 u8 reserved_at_60[0x80];
1952};
1953
1954struct mlx5_ifc_rdma_page_fault_event_bits {
1955 u8 bytes_committed[0x20];
1956
1957 u8 r_key[0x20];
1958
1959 u8 reserved_at_40[0x10];
1960 u8 packet_len[0x10];
1961
1962 u8 rdma_op_len[0x20];
1963
1964 u8 rdma_va[0x40];
1965
1966 u8 reserved_at_c0[0x5];
1967 u8 rdma[0x1];
1968 u8 write[0x1];
1969 u8 requestor[0x1];
1970 u8 qp_number[0x18];
1971};
1972
1973struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1974 u8 bytes_committed[0x20];
1975
1976 u8 reserved_at_20[0x10];
1977 u8 wqe_index[0x10];
1978
1979 u8 reserved_at_40[0x10];
1980 u8 len[0x10];
1981
1982 u8 reserved_at_60[0x60];
1983
1984 u8 reserved_at_c0[0x5];
1985 u8 rdma[0x1];
1986 u8 write_read[0x1];
1987 u8 requestor[0x1];
1988 u8 qpn[0x18];
1989};
1990
1991struct mlx5_ifc_qp_events_bits {
1992 u8 reserved_at_0[0xa0];
1993
1994 u8 type[0x8];
1995 u8 reserved_at_a8[0x18];
1996
1997 u8 reserved_at_c0[0x8];
1998 u8 qpn_rqn_sqn[0x18];
1999};
2000
2001struct mlx5_ifc_dct_events_bits {
2002 u8 reserved_at_0[0xc0];
2003
2004 u8 reserved_at_c0[0x8];
2005 u8 dct_number[0x18];
2006};
2007
2008struct mlx5_ifc_comp_event_bits {
2009 u8 reserved_at_0[0xc0];
2010
2011 u8 reserved_at_c0[0x8];
2012 u8 cq_number[0x18];
2013};
2014
2015enum {
2016 MLX5_QPC_STATE_RST = 0x0,
2017 MLX5_QPC_STATE_INIT = 0x1,
2018 MLX5_QPC_STATE_RTR = 0x2,
2019 MLX5_QPC_STATE_RTS = 0x3,
2020 MLX5_QPC_STATE_SQER = 0x4,
2021 MLX5_QPC_STATE_ERR = 0x6,
2022 MLX5_QPC_STATE_SQD = 0x7,
2023 MLX5_QPC_STATE_SUSPENDED = 0x9,
2024};
2025
2026enum {
2027 MLX5_QPC_ST_RC = 0x0,
2028 MLX5_QPC_ST_UC = 0x1,
2029 MLX5_QPC_ST_UD = 0x2,
2030 MLX5_QPC_ST_XRC = 0x3,
2031 MLX5_QPC_ST_DCI = 0x5,
2032 MLX5_QPC_ST_QP0 = 0x7,
2033 MLX5_QPC_ST_QP1 = 0x8,
2034 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2035 MLX5_QPC_ST_REG_UMR = 0xc,
2036};
2037
2038enum {
2039 MLX5_QPC_PM_STATE_ARMED = 0x0,
2040 MLX5_QPC_PM_STATE_REARM = 0x1,
2041 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2042 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2043};
2044
2045enum {
2046 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2047};
2048
2049enum {
2050 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2051 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2052};
2053
2054enum {
2055 MLX5_QPC_MTU_256_BYTES = 0x1,
2056 MLX5_QPC_MTU_512_BYTES = 0x2,
2057 MLX5_QPC_MTU_1K_BYTES = 0x3,
2058 MLX5_QPC_MTU_2K_BYTES = 0x4,
2059 MLX5_QPC_MTU_4K_BYTES = 0x5,
2060 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2061};
2062
2063enum {
2064 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2065 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2066 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2067 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2068 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2069 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2070 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2071 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2072};
2073
2074enum {
2075 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2076 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2077 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2078};
2079
2080enum {
2081 MLX5_QPC_CS_RES_DISABLE = 0x0,
2082 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2083 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2084};
2085
2086struct mlx5_ifc_qpc_bits {
2087 u8 state[0x4];
2088 u8 lag_tx_port_affinity[0x4];
2089 u8 st[0x8];
2090 u8 reserved_at_10[0x3];
2091 u8 pm_state[0x2];
2092 u8 reserved_at_15[0x3];
2093 u8 offload_type[0x4];
2094 u8 end_padding_mode[0x2];
2095 u8 reserved_at_1e[0x2];
2096
2097 u8 wq_signature[0x1];
2098 u8 block_lb_mc[0x1];
2099 u8 atomic_like_write_en[0x1];
2100 u8 latency_sensitive[0x1];
2101 u8 reserved_at_24[0x1];
2102 u8 drain_sigerr[0x1];
2103 u8 reserved_at_26[0x2];
2104 u8 pd[0x18];
2105
2106 u8 mtu[0x3];
2107 u8 log_msg_max[0x5];
2108 u8 reserved_at_48[0x1];
2109 u8 log_rq_size[0x4];
2110 u8 log_rq_stride[0x3];
2111 u8 no_sq[0x1];
2112 u8 log_sq_size[0x4];
2113 u8 reserved_at_55[0x6];
2114 u8 rlky[0x1];
2115 u8 ulp_stateless_offload_mode[0x4];
2116
2117 u8 counter_set_id[0x8];
2118 u8 uar_page[0x18];
2119
2120 u8 reserved_at_80[0x8];
2121 u8 user_index[0x18];
2122
2123 u8 reserved_at_a0[0x3];
2124 u8 log_page_size[0x5];
2125 u8 remote_qpn[0x18];
2126
2127 struct mlx5_ifc_ads_bits primary_address_path;
2128
2129 struct mlx5_ifc_ads_bits secondary_address_path;
2130
2131 u8 log_ack_req_freq[0x4];
2132 u8 reserved_at_384[0x4];
2133 u8 log_sra_max[0x3];
2134 u8 reserved_at_38b[0x2];
2135 u8 retry_count[0x3];
2136 u8 rnr_retry[0x3];
2137 u8 reserved_at_393[0x1];
2138 u8 fre[0x1];
2139 u8 cur_rnr_retry[0x3];
2140 u8 cur_retry_count[0x3];
2141 u8 reserved_at_39b[0x5];
2142
2143 u8 reserved_at_3a0[0x20];
2144
2145 u8 reserved_at_3c0[0x8];
2146 u8 next_send_psn[0x18];
2147
2148 u8 reserved_at_3e0[0x8];
2149 u8 cqn_snd[0x18];
2150
2151 u8 reserved_at_400[0x8];
2152 u8 deth_sqpn[0x18];
2153
2154 u8 reserved_at_420[0x20];
2155
2156 u8 reserved_at_440[0x8];
2157 u8 last_acked_psn[0x18];
2158
2159 u8 reserved_at_460[0x8];
2160 u8 ssn[0x18];
2161
2162 u8 reserved_at_480[0x8];
2163 u8 log_rra_max[0x3];
2164 u8 reserved_at_48b[0x1];
2165 u8 atomic_mode[0x4];
2166 u8 rre[0x1];
2167 u8 rwe[0x1];
2168 u8 rae[0x1];
2169 u8 reserved_at_493[0x1];
2170 u8 page_offset[0x6];
2171 u8 reserved_at_49a[0x3];
2172 u8 cd_slave_receive[0x1];
2173 u8 cd_slave_send[0x1];
2174 u8 cd_master[0x1];
2175
2176 u8 reserved_at_4a0[0x3];
2177 u8 min_rnr_nak[0x5];
2178 u8 next_rcv_psn[0x18];
2179
2180 u8 reserved_at_4c0[0x8];
2181 u8 xrcd[0x18];
2182
2183 u8 reserved_at_4e0[0x8];
2184 u8 cqn_rcv[0x18];
2185
2186 u8 dbr_addr[0x40];
2187
2188 u8 q_key[0x20];
2189
2190 u8 reserved_at_560[0x5];
2191 u8 rq_type[0x3];
2192 u8 srqn_rmpn_xrqn[0x18];
2193
2194 u8 reserved_at_580[0x8];
2195 u8 rmsn[0x18];
2196
2197 u8 hw_sq_wqebb_counter[0x10];
2198 u8 sw_sq_wqebb_counter[0x10];
2199
2200 u8 hw_rq_counter[0x20];
2201
2202 u8 sw_rq_counter[0x20];
2203
2204 u8 reserved_at_600[0x20];
2205
2206 u8 reserved_at_620[0xf];
2207 u8 cgs[0x1];
2208 u8 cs_req[0x8];
2209 u8 cs_res[0x8];
2210
2211 u8 dc_access_key[0x40];
2212
2213 u8 reserved_at_680[0xc0];
2214};
2215
2216struct mlx5_ifc_roce_addr_layout_bits {
2217 u8 source_l3_address[16][0x8];
2218
2219 u8 reserved_at_80[0x3];
2220 u8 vlan_valid[0x1];
2221 u8 vlan_id[0xc];
2222 u8 source_mac_47_32[0x10];
2223
2224 u8 source_mac_31_0[0x20];
2225
2226 u8 reserved_at_c0[0x14];
2227 u8 roce_l3_type[0x4];
2228 u8 roce_version[0x8];
2229
2230 u8 reserved_at_e0[0x20];
2231};
2232
2233union mlx5_ifc_hca_cap_union_bits {
2234 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2235 struct mlx5_ifc_odp_cap_bits odp_cap;
2236 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2237 struct mlx5_ifc_roce_cap_bits roce_cap;
2238 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2239 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2240 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2241 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2242 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2243 struct mlx5_ifc_qos_cap_bits qos_cap;
2244 struct mlx5_ifc_fpga_cap_bits fpga_cap;
2245 u8 reserved_at_0[0x8000];
2246};
2247
2248enum {
2249 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2250 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2251 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2252 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2253 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2254 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2255 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
2256};
2257
2258struct mlx5_ifc_flow_context_bits {
2259 u8 reserved_at_0[0x20];
2260
2261 u8 group_id[0x20];
2262
2263 u8 reserved_at_40[0x8];
2264 u8 flow_tag[0x18];
2265
2266 u8 reserved_at_60[0x10];
2267 u8 action[0x10];
2268
2269 u8 reserved_at_80[0x8];
2270 u8 destination_list_size[0x18];
2271
2272 u8 reserved_at_a0[0x8];
2273 u8 flow_counter_list_size[0x18];
2274
2275 u8 encap_id[0x20];
2276
2277 u8 modify_header_id[0x20];
2278
2279 u8 reserved_at_100[0x100];
2280
2281 struct mlx5_ifc_fte_match_param_bits match_value;
2282
2283 u8 reserved_at_1200[0x600];
2284
2285 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2286};
2287
2288enum {
2289 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2290 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2291};
2292
2293struct mlx5_ifc_xrc_srqc_bits {
2294 u8 state[0x4];
2295 u8 log_xrc_srq_size[0x4];
2296 u8 reserved_at_8[0x18];
2297
2298 u8 wq_signature[0x1];
2299 u8 cont_srq[0x1];
2300 u8 reserved_at_22[0x1];
2301 u8 rlky[0x1];
2302 u8 basic_cyclic_rcv_wqe[0x1];
2303 u8 log_rq_stride[0x3];
2304 u8 xrcd[0x18];
2305
2306 u8 page_offset[0x6];
2307 u8 reserved_at_46[0x2];
2308 u8 cqn[0x18];
2309
2310 u8 reserved_at_60[0x20];
2311
2312 u8 user_index_equal_xrc_srqn[0x1];
2313 u8 reserved_at_81[0x1];
2314 u8 log_page_size[0x6];
2315 u8 user_index[0x18];
2316
2317 u8 reserved_at_a0[0x20];
2318
2319 u8 reserved_at_c0[0x8];
2320 u8 pd[0x18];
2321
2322 u8 lwm[0x10];
2323 u8 wqe_cnt[0x10];
2324
2325 u8 reserved_at_100[0x40];
2326
2327 u8 db_record_addr_h[0x20];
2328
2329 u8 db_record_addr_l[0x1e];
2330 u8 reserved_at_17e[0x2];
2331
2332 u8 reserved_at_180[0x80];
2333};
2334
2335struct mlx5_ifc_traffic_counter_bits {
2336 u8 packets[0x40];
2337
2338 u8 octets[0x40];
2339};
2340
2341struct mlx5_ifc_tisc_bits {
2342 u8 strict_lag_tx_port_affinity[0x1];
2343 u8 reserved_at_1[0x3];
2344 u8 lag_tx_port_affinity[0x04];
2345
2346 u8 reserved_at_8[0x4];
2347 u8 prio[0x4];
2348 u8 reserved_at_10[0x10];
2349
2350 u8 reserved_at_20[0x100];
2351
2352 u8 reserved_at_120[0x8];
2353 u8 transport_domain[0x18];
2354
2355 u8 reserved_at_140[0x8];
2356 u8 underlay_qpn[0x18];
2357 u8 reserved_at_160[0x3a0];
2358};
2359
2360enum {
2361 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2362 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2363};
2364
2365enum {
2366 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2367 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2368};
2369
2370enum {
2371 MLX5_RX_HASH_FN_NONE = 0x0,
2372 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2373 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2374};
2375
2376enum {
2377 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2378 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2379};
2380
2381struct mlx5_ifc_tirc_bits {
2382 u8 reserved_at_0[0x20];
2383
2384 u8 disp_type[0x4];
2385 u8 reserved_at_24[0x1c];
2386
2387 u8 reserved_at_40[0x40];
2388
2389 u8 reserved_at_80[0x4];
2390 u8 lro_timeout_period_usecs[0x10];
2391 u8 lro_enable_mask[0x4];
2392 u8 lro_max_ip_payload_size[0x8];
2393
2394 u8 reserved_at_a0[0x40];
2395
2396 u8 reserved_at_e0[0x8];
2397 u8 inline_rqn[0x18];
2398
2399 u8 rx_hash_symmetric[0x1];
2400 u8 reserved_at_101[0x1];
2401 u8 tunneled_offload_en[0x1];
2402 u8 reserved_at_103[0x5];
2403 u8 indirect_table[0x18];
2404
2405 u8 rx_hash_fn[0x4];
2406 u8 reserved_at_124[0x2];
2407 u8 self_lb_block[0x2];
2408 u8 transport_domain[0x18];
2409
2410 u8 rx_hash_toeplitz_key[10][0x20];
2411
2412 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2413
2414 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2415
2416 u8 reserved_at_2c0[0x4c0];
2417};
2418
2419enum {
2420 MLX5_SRQC_STATE_GOOD = 0x0,
2421 MLX5_SRQC_STATE_ERROR = 0x1,
2422};
2423
2424struct mlx5_ifc_srqc_bits {
2425 u8 state[0x4];
2426 u8 log_srq_size[0x4];
2427 u8 reserved_at_8[0x18];
2428
2429 u8 wq_signature[0x1];
2430 u8 cont_srq[0x1];
2431 u8 reserved_at_22[0x1];
2432 u8 rlky[0x1];
2433 u8 reserved_at_24[0x1];
2434 u8 log_rq_stride[0x3];
2435 u8 xrcd[0x18];
2436
2437 u8 page_offset[0x6];
2438 u8 reserved_at_46[0x2];
2439 u8 cqn[0x18];
2440
2441 u8 reserved_at_60[0x20];
2442
2443 u8 reserved_at_80[0x2];
2444 u8 log_page_size[0x6];
2445 u8 reserved_at_88[0x18];
2446
2447 u8 reserved_at_a0[0x20];
2448
2449 u8 reserved_at_c0[0x8];
2450 u8 pd[0x18];
2451
2452 u8 lwm[0x10];
2453 u8 wqe_cnt[0x10];
2454
2455 u8 reserved_at_100[0x40];
2456
2457 u8 dbr_addr[0x40];
2458
2459 u8 reserved_at_180[0x80];
2460};
2461
2462enum {
2463 MLX5_SQC_STATE_RST = 0x0,
2464 MLX5_SQC_STATE_RDY = 0x1,
2465 MLX5_SQC_STATE_ERR = 0x3,
2466};
2467
2468struct mlx5_ifc_sqc_bits {
2469 u8 rlky[0x1];
2470 u8 cd_master[0x1];
2471 u8 fre[0x1];
2472 u8 flush_in_error_en[0x1];
2473 u8 allow_multi_pkt_send_wqe[0x1];
2474 u8 min_wqe_inline_mode[0x3];
2475 u8 state[0x4];
2476 u8 reg_umr[0x1];
2477 u8 allow_swp[0x1];
2478 u8 reserved_at_e[0x12];
2479
2480 u8 reserved_at_20[0x8];
2481 u8 user_index[0x18];
2482
2483 u8 reserved_at_40[0x8];
2484 u8 cqn[0x18];
2485
2486 u8 reserved_at_60[0x90];
2487
2488 u8 packet_pacing_rate_limit_index[0x10];
2489 u8 tis_lst_sz[0x10];
2490 u8 reserved_at_110[0x10];
2491
2492 u8 reserved_at_120[0x40];
2493
2494 u8 reserved_at_160[0x8];
2495 u8 tis_num_0[0x18];
2496
2497 struct mlx5_ifc_wq_bits wq;
2498};
2499
2500enum {
2501 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2502 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2503 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2504 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2505};
2506
2507struct mlx5_ifc_scheduling_context_bits {
2508 u8 element_type[0x8];
2509 u8 reserved_at_8[0x18];
2510
2511 u8 element_attributes[0x20];
2512
2513 u8 parent_element_id[0x20];
2514
2515 u8 reserved_at_60[0x40];
2516
2517 u8 bw_share[0x20];
2518
2519 u8 max_average_bw[0x20];
2520
2521 u8 reserved_at_e0[0x120];
2522};
2523
2524struct mlx5_ifc_rqtc_bits {
2525 u8 reserved_at_0[0xa0];
2526
2527 u8 reserved_at_a0[0x10];
2528 u8 rqt_max_size[0x10];
2529
2530 u8 reserved_at_c0[0x10];
2531 u8 rqt_actual_size[0x10];
2532
2533 u8 reserved_at_e0[0x6a0];
2534
2535 struct mlx5_ifc_rq_num_bits rq_num[0];
2536};
2537
2538enum {
2539 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2540 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2541};
2542
2543enum {
2544 MLX5_RQC_STATE_RST = 0x0,
2545 MLX5_RQC_STATE_RDY = 0x1,
2546 MLX5_RQC_STATE_ERR = 0x3,
2547};
2548
2549struct mlx5_ifc_rqc_bits {
2550 u8 rlky[0x1];
2551 u8 delay_drop_en[0x1];
2552 u8 scatter_fcs[0x1];
2553 u8 vsd[0x1];
2554 u8 mem_rq_type[0x4];
2555 u8 state[0x4];
2556 u8 reserved_at_c[0x1];
2557 u8 flush_in_error_en[0x1];
2558 u8 reserved_at_e[0x12];
2559
2560 u8 reserved_at_20[0x8];
2561 u8 user_index[0x18];
2562
2563 u8 reserved_at_40[0x8];
2564 u8 cqn[0x18];
2565
2566 u8 counter_set_id[0x8];
2567 u8 reserved_at_68[0x18];
2568
2569 u8 reserved_at_80[0x8];
2570 u8 rmpn[0x18];
2571
2572 u8 reserved_at_a0[0xe0];
2573
2574 struct mlx5_ifc_wq_bits wq;
2575};
2576
2577enum {
2578 MLX5_RMPC_STATE_RDY = 0x1,
2579 MLX5_RMPC_STATE_ERR = 0x3,
2580};
2581
2582struct mlx5_ifc_rmpc_bits {
2583 u8 reserved_at_0[0x8];
2584 u8 state[0x4];
2585 u8 reserved_at_c[0x14];
2586
2587 u8 basic_cyclic_rcv_wqe[0x1];
2588 u8 reserved_at_21[0x1f];
2589
2590 u8 reserved_at_40[0x140];
2591
2592 struct mlx5_ifc_wq_bits wq;
2593};
2594
2595struct mlx5_ifc_nic_vport_context_bits {
2596 u8 reserved_at_0[0x5];
2597 u8 min_wqe_inline_mode[0x3];
2598 u8 reserved_at_8[0x15];
2599 u8 disable_mc_local_lb[0x1];
2600 u8 disable_uc_local_lb[0x1];
2601 u8 roce_en[0x1];
2602
2603 u8 arm_change_event[0x1];
2604 u8 reserved_at_21[0x1a];
2605 u8 event_on_mtu[0x1];
2606 u8 event_on_promisc_change[0x1];
2607 u8 event_on_vlan_change[0x1];
2608 u8 event_on_mc_address_change[0x1];
2609 u8 event_on_uc_address_change[0x1];
2610
2611 u8 reserved_at_40[0xf0];
2612
2613 u8 mtu[0x10];
2614
2615 u8 system_image_guid[0x40];
2616 u8 port_guid[0x40];
2617 u8 node_guid[0x40];
2618
2619 u8 reserved_at_200[0x140];
2620 u8 qkey_violation_counter[0x10];
2621 u8 reserved_at_350[0x430];
2622
2623 u8 promisc_uc[0x1];
2624 u8 promisc_mc[0x1];
2625 u8 promisc_all[0x1];
2626 u8 reserved_at_783[0x2];
2627 u8 allowed_list_type[0x3];
2628 u8 reserved_at_788[0xc];
2629 u8 allowed_list_size[0xc];
2630
2631 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2632
2633 u8 reserved_at_7e0[0x20];
2634
2635 u8 current_uc_mac_address[0][0x40];
2636};
2637
2638enum {
2639 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2640 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2641 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2642 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
2643};
2644
2645struct mlx5_ifc_mkc_bits {
2646 u8 reserved_at_0[0x1];
2647 u8 free[0x1];
2648 u8 reserved_at_2[0xd];
2649 u8 small_fence_on_rdma_read_response[0x1];
2650 u8 umr_en[0x1];
2651 u8 a[0x1];
2652 u8 rw[0x1];
2653 u8 rr[0x1];
2654 u8 lw[0x1];
2655 u8 lr[0x1];
2656 u8 access_mode[0x2];
2657 u8 reserved_at_18[0x8];
2658
2659 u8 qpn[0x18];
2660 u8 mkey_7_0[0x8];
2661
2662 u8 reserved_at_40[0x20];
2663
2664 u8 length64[0x1];
2665 u8 bsf_en[0x1];
2666 u8 sync_umr[0x1];
2667 u8 reserved_at_63[0x2];
2668 u8 expected_sigerr_count[0x1];
2669 u8 reserved_at_66[0x1];
2670 u8 en_rinval[0x1];
2671 u8 pd[0x18];
2672
2673 u8 start_addr[0x40];
2674
2675 u8 len[0x40];
2676
2677 u8 bsf_octword_size[0x20];
2678
2679 u8 reserved_at_120[0x80];
2680
2681 u8 translations_octword_size[0x20];
2682
2683 u8 reserved_at_1c0[0x1b];
2684 u8 log_page_size[0x5];
2685
2686 u8 reserved_at_1e0[0x20];
2687};
2688
2689struct mlx5_ifc_pkey_bits {
2690 u8 reserved_at_0[0x10];
2691 u8 pkey[0x10];
2692};
2693
2694struct mlx5_ifc_array128_auto_bits {
2695 u8 array128_auto[16][0x8];
2696};
2697
2698struct mlx5_ifc_hca_vport_context_bits {
2699 u8 field_select[0x20];
2700
2701 u8 reserved_at_20[0xe0];
2702
2703 u8 sm_virt_aware[0x1];
2704 u8 has_smi[0x1];
2705 u8 has_raw[0x1];
2706 u8 grh_required[0x1];
2707 u8 reserved_at_104[0xc];
2708 u8 port_physical_state[0x4];
2709 u8 vport_state_policy[0x4];
2710 u8 port_state[0x4];
2711 u8 vport_state[0x4];
2712
2713 u8 reserved_at_120[0x20];
2714
2715 u8 system_image_guid[0x40];
2716
2717 u8 port_guid[0x40];
2718
2719 u8 node_guid[0x40];
2720
2721 u8 cap_mask1[0x20];
2722
2723 u8 cap_mask1_field_select[0x20];
2724
2725 u8 cap_mask2[0x20];
2726
2727 u8 cap_mask2_field_select[0x20];
2728
2729 u8 reserved_at_280[0x80];
2730
2731 u8 lid[0x10];
2732 u8 reserved_at_310[0x4];
2733 u8 init_type_reply[0x4];
2734 u8 lmc[0x3];
2735 u8 subnet_timeout[0x5];
2736
2737 u8 sm_lid[0x10];
2738 u8 sm_sl[0x4];
2739 u8 reserved_at_334[0xc];
2740
2741 u8 qkey_violation_counter[0x10];
2742 u8 pkey_violation_counter[0x10];
2743
2744 u8 reserved_at_360[0xca0];
2745};
2746
2747struct mlx5_ifc_esw_vport_context_bits {
2748 u8 reserved_at_0[0x3];
2749 u8 vport_svlan_strip[0x1];
2750 u8 vport_cvlan_strip[0x1];
2751 u8 vport_svlan_insert[0x1];
2752 u8 vport_cvlan_insert[0x2];
2753 u8 reserved_at_8[0x18];
2754
2755 u8 reserved_at_20[0x20];
2756
2757 u8 svlan_cfi[0x1];
2758 u8 svlan_pcp[0x3];
2759 u8 svlan_id[0xc];
2760 u8 cvlan_cfi[0x1];
2761 u8 cvlan_pcp[0x3];
2762 u8 cvlan_id[0xc];
2763
2764 u8 reserved_at_60[0x7a0];
2765};
2766
2767enum {
2768 MLX5_EQC_STATUS_OK = 0x0,
2769 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2770};
2771
2772enum {
2773 MLX5_EQC_ST_ARMED = 0x9,
2774 MLX5_EQC_ST_FIRED = 0xa,
2775};
2776
2777struct mlx5_ifc_eqc_bits {
2778 u8 status[0x4];
2779 u8 reserved_at_4[0x9];
2780 u8 ec[0x1];
2781 u8 oi[0x1];
2782 u8 reserved_at_f[0x5];
2783 u8 st[0x4];
2784 u8 reserved_at_18[0x8];
2785
2786 u8 reserved_at_20[0x20];
2787
2788 u8 reserved_at_40[0x14];
2789 u8 page_offset[0x6];
2790 u8 reserved_at_5a[0x6];
2791
2792 u8 reserved_at_60[0x3];
2793 u8 log_eq_size[0x5];
2794 u8 uar_page[0x18];
2795
2796 u8 reserved_at_80[0x20];
2797
2798 u8 reserved_at_a0[0x18];
2799 u8 intr[0x8];
2800
2801 u8 reserved_at_c0[0x3];
2802 u8 log_page_size[0x5];
2803 u8 reserved_at_c8[0x18];
2804
2805 u8 reserved_at_e0[0x60];
2806
2807 u8 reserved_at_140[0x8];
2808 u8 consumer_counter[0x18];
2809
2810 u8 reserved_at_160[0x8];
2811 u8 producer_counter[0x18];
2812
2813 u8 reserved_at_180[0x80];
2814};
2815
2816enum {
2817 MLX5_DCTC_STATE_ACTIVE = 0x0,
2818 MLX5_DCTC_STATE_DRAINING = 0x1,
2819 MLX5_DCTC_STATE_DRAINED = 0x2,
2820};
2821
2822enum {
2823 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2824 MLX5_DCTC_CS_RES_NA = 0x1,
2825 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2826};
2827
2828enum {
2829 MLX5_DCTC_MTU_256_BYTES = 0x1,
2830 MLX5_DCTC_MTU_512_BYTES = 0x2,
2831 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2832 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2833 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2834};
2835
2836struct mlx5_ifc_dctc_bits {
2837 u8 reserved_at_0[0x4];
2838 u8 state[0x4];
2839 u8 reserved_at_8[0x18];
2840
2841 u8 reserved_at_20[0x8];
2842 u8 user_index[0x18];
2843
2844 u8 reserved_at_40[0x8];
2845 u8 cqn[0x18];
2846
2847 u8 counter_set_id[0x8];
2848 u8 atomic_mode[0x4];
2849 u8 rre[0x1];
2850 u8 rwe[0x1];
2851 u8 rae[0x1];
2852 u8 atomic_like_write_en[0x1];
2853 u8 latency_sensitive[0x1];
2854 u8 rlky[0x1];
2855 u8 free_ar[0x1];
2856 u8 reserved_at_73[0xd];
2857
2858 u8 reserved_at_80[0x8];
2859 u8 cs_res[0x8];
2860 u8 reserved_at_90[0x3];
2861 u8 min_rnr_nak[0x5];
2862 u8 reserved_at_98[0x8];
2863
2864 u8 reserved_at_a0[0x8];
2865 u8 srqn_xrqn[0x18];
2866
2867 u8 reserved_at_c0[0x8];
2868 u8 pd[0x18];
2869
2870 u8 tclass[0x8];
2871 u8 reserved_at_e8[0x4];
2872 u8 flow_label[0x14];
2873
2874 u8 dc_access_key[0x40];
2875
2876 u8 reserved_at_140[0x5];
2877 u8 mtu[0x3];
2878 u8 port[0x8];
2879 u8 pkey_index[0x10];
2880
2881 u8 reserved_at_160[0x8];
2882 u8 my_addr_index[0x8];
2883 u8 reserved_at_170[0x8];
2884 u8 hop_limit[0x8];
2885
2886 u8 dc_access_key_violation_count[0x20];
2887
2888 u8 reserved_at_1a0[0x14];
2889 u8 dei_cfi[0x1];
2890 u8 eth_prio[0x3];
2891 u8 ecn[0x2];
2892 u8 dscp[0x6];
2893
2894 u8 reserved_at_1c0[0x40];
2895};
2896
2897enum {
2898 MLX5_CQC_STATUS_OK = 0x0,
2899 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2900 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2901};
2902
2903enum {
2904 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2905 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2906};
2907
2908enum {
2909 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2910 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2911 MLX5_CQC_ST_FIRED = 0xa,
2912};
2913
2914enum {
2915 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2916 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2917 MLX5_CQ_PERIOD_NUM_MODES
2918};
2919
2920struct mlx5_ifc_cqc_bits {
2921 u8 status[0x4];
2922 u8 reserved_at_4[0x4];
2923 u8 cqe_sz[0x3];
2924 u8 cc[0x1];
2925 u8 reserved_at_c[0x1];
2926 u8 scqe_break_moderation_en[0x1];
2927 u8 oi[0x1];
2928 u8 cq_period_mode[0x2];
2929 u8 cqe_comp_en[0x1];
2930 u8 mini_cqe_res_format[0x2];
2931 u8 st[0x4];
2932 u8 reserved_at_18[0x8];
2933
2934 u8 reserved_at_20[0x20];
2935
2936 u8 reserved_at_40[0x14];
2937 u8 page_offset[0x6];
2938 u8 reserved_at_5a[0x6];
2939
2940 u8 reserved_at_60[0x3];
2941 u8 log_cq_size[0x5];
2942 u8 uar_page[0x18];
2943
2944 u8 reserved_at_80[0x4];
2945 u8 cq_period[0xc];
2946 u8 cq_max_count[0x10];
2947
2948 u8 reserved_at_a0[0x18];
2949 u8 c_eqn[0x8];
2950
2951 u8 reserved_at_c0[0x3];
2952 u8 log_page_size[0x5];
2953 u8 reserved_at_c8[0x18];
2954
2955 u8 reserved_at_e0[0x20];
2956
2957 u8 reserved_at_100[0x8];
2958 u8 last_notified_index[0x18];
2959
2960 u8 reserved_at_120[0x8];
2961 u8 last_solicit_index[0x18];
2962
2963 u8 reserved_at_140[0x8];
2964 u8 consumer_counter[0x18];
2965
2966 u8 reserved_at_160[0x8];
2967 u8 producer_counter[0x18];
2968
2969 u8 reserved_at_180[0x40];
2970
2971 u8 dbr_addr[0x40];
2972};
2973
2974union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2975 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2976 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2977 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2978 u8 reserved_at_0[0x800];
2979};
2980
2981struct mlx5_ifc_query_adapter_param_block_bits {
2982 u8 reserved_at_0[0xc0];
2983
2984 u8 reserved_at_c0[0x8];
2985 u8 ieee_vendor_id[0x18];
2986
2987 u8 reserved_at_e0[0x10];
2988 u8 vsd_vendor_id[0x10];
2989
2990 u8 vsd[208][0x8];
2991
2992 u8 vsd_contd_psid[16][0x8];
2993};
2994
2995enum {
2996 MLX5_XRQC_STATE_GOOD = 0x0,
2997 MLX5_XRQC_STATE_ERROR = 0x1,
2998};
2999
3000enum {
3001 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3002 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3003};
3004
3005enum {
3006 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3007};
3008
3009struct mlx5_ifc_tag_matching_topology_context_bits {
3010 u8 log_matching_list_sz[0x4];
3011 u8 reserved_at_4[0xc];
3012 u8 append_next_index[0x10];
3013
3014 u8 sw_phase_cnt[0x10];
3015 u8 hw_phase_cnt[0x10];
3016
3017 u8 reserved_at_40[0x40];
3018};
3019
3020struct mlx5_ifc_xrqc_bits {
3021 u8 state[0x4];
3022 u8 rlkey[0x1];
3023 u8 reserved_at_5[0xf];
3024 u8 topology[0x4];
3025 u8 reserved_at_18[0x4];
3026 u8 offload[0x4];
3027
3028 u8 reserved_at_20[0x8];
3029 u8 user_index[0x18];
3030
3031 u8 reserved_at_40[0x8];
3032 u8 cqn[0x18];
3033
3034 u8 reserved_at_60[0xa0];
3035
3036 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3037
3038 u8 reserved_at_180[0x280];
3039
3040 struct mlx5_ifc_wq_bits wq;
3041};
3042
3043union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3044 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3045 struct mlx5_ifc_resize_field_select_bits resize_field_select;
3046 u8 reserved_at_0[0x20];
3047};
3048
3049union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3050 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3051 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3052 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3053 u8 reserved_at_0[0x20];
3054};
3055
3056union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3057 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3058 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3059 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3060 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3061 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3062 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3063 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3064 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3065 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3066 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3067 u8 reserved_at_0[0x7c0];
3068};
3069
3070union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3071 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3072 u8 reserved_at_0[0x7c0];
3073};
3074
3075union mlx5_ifc_event_auto_bits {
3076 struct mlx5_ifc_comp_event_bits comp_event;
3077 struct mlx5_ifc_dct_events_bits dct_events;
3078 struct mlx5_ifc_qp_events_bits qp_events;
3079 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3080 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3081 struct mlx5_ifc_cq_error_bits cq_error;
3082 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3083 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3084 struct mlx5_ifc_gpio_event_bits gpio_event;
3085 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3086 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3087 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3088 u8 reserved_at_0[0xe0];
3089};
3090
3091struct mlx5_ifc_health_buffer_bits {
3092 u8 reserved_at_0[0x100];
3093
3094 u8 assert_existptr[0x20];
3095
3096 u8 assert_callra[0x20];
3097
3098 u8 reserved_at_140[0x40];
3099
3100 u8 fw_version[0x20];
3101
3102 u8 hw_id[0x20];
3103
3104 u8 reserved_at_1c0[0x20];
3105
3106 u8 irisc_index[0x8];
3107 u8 synd[0x8];
3108 u8 ext_synd[0x10];
3109};
3110
3111struct mlx5_ifc_register_loopback_control_bits {
3112 u8 no_lb[0x1];
3113 u8 reserved_at_1[0x7];
3114 u8 port[0x8];
3115 u8 reserved_at_10[0x10];
3116
3117 u8 reserved_at_20[0x60];
3118};
3119
3120struct mlx5_ifc_vport_tc_element_bits {
3121 u8 traffic_class[0x4];
3122 u8 reserved_at_4[0xc];
3123 u8 vport_number[0x10];
3124};
3125
3126struct mlx5_ifc_vport_element_bits {
3127 u8 reserved_at_0[0x10];
3128 u8 vport_number[0x10];
3129};
3130
3131enum {
3132 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3133 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3134 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3135};
3136
3137struct mlx5_ifc_tsar_element_bits {
3138 u8 reserved_at_0[0x8];
3139 u8 tsar_type[0x8];
3140 u8 reserved_at_10[0x10];
3141};
3142
3143enum {
3144 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3145 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3146};
3147
3148struct mlx5_ifc_teardown_hca_out_bits {
3149 u8 status[0x8];
3150 u8 reserved_at_8[0x18];
3151
3152 u8 syndrome[0x20];
3153
3154 u8 reserved_at_40[0x3f];
3155
3156 u8 force_state[0x1];
3157};
3158
3159enum {
3160 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3161 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
3162};
3163
3164struct mlx5_ifc_teardown_hca_in_bits {
3165 u8 opcode[0x10];
3166 u8 reserved_at_10[0x10];
3167
3168 u8 reserved_at_20[0x10];
3169 u8 op_mod[0x10];
3170
3171 u8 reserved_at_40[0x10];
3172 u8 profile[0x10];
3173
3174 u8 reserved_at_60[0x20];
3175};
3176
3177struct mlx5_ifc_sqerr2rts_qp_out_bits {
3178 u8 status[0x8];
3179 u8 reserved_at_8[0x18];
3180
3181 u8 syndrome[0x20];
3182
3183 u8 reserved_at_40[0x40];
3184};
3185
3186struct mlx5_ifc_sqerr2rts_qp_in_bits {
3187 u8 opcode[0x10];
3188 u8 reserved_at_10[0x10];
3189
3190 u8 reserved_at_20[0x10];
3191 u8 op_mod[0x10];
3192
3193 u8 reserved_at_40[0x8];
3194 u8 qpn[0x18];
3195
3196 u8 reserved_at_60[0x20];
3197
3198 u8 opt_param_mask[0x20];
3199
3200 u8 reserved_at_a0[0x20];
3201
3202 struct mlx5_ifc_qpc_bits qpc;
3203
3204 u8 reserved_at_800[0x80];
3205};
3206
3207struct mlx5_ifc_sqd2rts_qp_out_bits {
3208 u8 status[0x8];
3209 u8 reserved_at_8[0x18];
3210
3211 u8 syndrome[0x20];
3212
3213 u8 reserved_at_40[0x40];
3214};
3215
3216struct mlx5_ifc_sqd2rts_qp_in_bits {
3217 u8 opcode[0x10];
3218 u8 reserved_at_10[0x10];
3219
3220 u8 reserved_at_20[0x10];
3221 u8 op_mod[0x10];
3222
3223 u8 reserved_at_40[0x8];
3224 u8 qpn[0x18];
3225
3226 u8 reserved_at_60[0x20];
3227
3228 u8 opt_param_mask[0x20];
3229
3230 u8 reserved_at_a0[0x20];
3231
3232 struct mlx5_ifc_qpc_bits qpc;
3233
3234 u8 reserved_at_800[0x80];
3235};
3236
3237struct mlx5_ifc_set_roce_address_out_bits {
3238 u8 status[0x8];
3239 u8 reserved_at_8[0x18];
3240
3241 u8 syndrome[0x20];
3242
3243 u8 reserved_at_40[0x40];
3244};
3245
3246struct mlx5_ifc_set_roce_address_in_bits {
3247 u8 opcode[0x10];
3248 u8 reserved_at_10[0x10];
3249
3250 u8 reserved_at_20[0x10];
3251 u8 op_mod[0x10];
3252
3253 u8 roce_address_index[0x10];
3254 u8 reserved_at_50[0x10];
3255
3256 u8 reserved_at_60[0x20];
3257
3258 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3259};
3260
3261struct mlx5_ifc_set_mad_demux_out_bits {
3262 u8 status[0x8];
3263 u8 reserved_at_8[0x18];
3264
3265 u8 syndrome[0x20];
3266
3267 u8 reserved_at_40[0x40];
3268};
3269
3270enum {
3271 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3272 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3273};
3274
3275struct mlx5_ifc_set_mad_demux_in_bits {
3276 u8 opcode[0x10];
3277 u8 reserved_at_10[0x10];
3278
3279 u8 reserved_at_20[0x10];
3280 u8 op_mod[0x10];
3281
3282 u8 reserved_at_40[0x20];
3283
3284 u8 reserved_at_60[0x6];
3285 u8 demux_mode[0x2];
3286 u8 reserved_at_68[0x18];
3287};
3288
3289struct mlx5_ifc_set_l2_table_entry_out_bits {
3290 u8 status[0x8];
3291 u8 reserved_at_8[0x18];
3292
3293 u8 syndrome[0x20];
3294
3295 u8 reserved_at_40[0x40];
3296};
3297
3298struct mlx5_ifc_set_l2_table_entry_in_bits {
3299 u8 opcode[0x10];
3300 u8 reserved_at_10[0x10];
3301
3302 u8 reserved_at_20[0x10];
3303 u8 op_mod[0x10];
3304
3305 u8 reserved_at_40[0x60];
3306
3307 u8 reserved_at_a0[0x8];
3308 u8 table_index[0x18];
3309
3310 u8 reserved_at_c0[0x20];
3311
3312 u8 reserved_at_e0[0x13];
3313 u8 vlan_valid[0x1];
3314 u8 vlan[0xc];
3315
3316 struct mlx5_ifc_mac_address_layout_bits mac_address;
3317
3318 u8 reserved_at_140[0xc0];
3319};
3320
3321struct mlx5_ifc_set_issi_out_bits {
3322 u8 status[0x8];
3323 u8 reserved_at_8[0x18];
3324
3325 u8 syndrome[0x20];
3326
3327 u8 reserved_at_40[0x40];
3328};
3329
3330struct mlx5_ifc_set_issi_in_bits {
3331 u8 opcode[0x10];
3332 u8 reserved_at_10[0x10];
3333
3334 u8 reserved_at_20[0x10];
3335 u8 op_mod[0x10];
3336
3337 u8 reserved_at_40[0x10];
3338 u8 current_issi[0x10];
3339
3340 u8 reserved_at_60[0x20];
3341};
3342
3343struct mlx5_ifc_set_hca_cap_out_bits {
3344 u8 status[0x8];
3345 u8 reserved_at_8[0x18];
3346
3347 u8 syndrome[0x20];
3348
3349 u8 reserved_at_40[0x40];
3350};
3351
3352struct mlx5_ifc_set_hca_cap_in_bits {
3353 u8 opcode[0x10];
3354 u8 reserved_at_10[0x10];
3355
3356 u8 reserved_at_20[0x10];
3357 u8 op_mod[0x10];
3358
3359 u8 reserved_at_40[0x40];
3360
3361 union mlx5_ifc_hca_cap_union_bits capability;
3362};
3363
3364enum {
3365 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3366 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3367 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3368 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3369};
3370
3371struct mlx5_ifc_set_fte_out_bits {
3372 u8 status[0x8];
3373 u8 reserved_at_8[0x18];
3374
3375 u8 syndrome[0x20];
3376
3377 u8 reserved_at_40[0x40];
3378};
3379
3380struct mlx5_ifc_set_fte_in_bits {
3381 u8 opcode[0x10];
3382 u8 reserved_at_10[0x10];
3383
3384 u8 reserved_at_20[0x10];
3385 u8 op_mod[0x10];
3386
3387 u8 other_vport[0x1];
3388 u8 reserved_at_41[0xf];
3389 u8 vport_number[0x10];
3390
3391 u8 reserved_at_60[0x20];
3392
3393 u8 table_type[0x8];
3394 u8 reserved_at_88[0x18];
3395
3396 u8 reserved_at_a0[0x8];
3397 u8 table_id[0x18];
3398
3399 u8 reserved_at_c0[0x18];
3400 u8 modify_enable_mask[0x8];
3401
3402 u8 reserved_at_e0[0x20];
3403
3404 u8 flow_index[0x20];
3405
3406 u8 reserved_at_120[0xe0];
3407
3408 struct mlx5_ifc_flow_context_bits flow_context;
3409};
3410
3411struct mlx5_ifc_rts2rts_qp_out_bits {
3412 u8 status[0x8];
3413 u8 reserved_at_8[0x18];
3414
3415 u8 syndrome[0x20];
3416
3417 u8 reserved_at_40[0x40];
3418};
3419
3420struct mlx5_ifc_rts2rts_qp_in_bits {
3421 u8 opcode[0x10];
3422 u8 reserved_at_10[0x10];
3423
3424 u8 reserved_at_20[0x10];
3425 u8 op_mod[0x10];
3426
3427 u8 reserved_at_40[0x8];
3428 u8 qpn[0x18];
3429
3430 u8 reserved_at_60[0x20];
3431
3432 u8 opt_param_mask[0x20];
3433
3434 u8 reserved_at_a0[0x20];
3435
3436 struct mlx5_ifc_qpc_bits qpc;
3437
3438 u8 reserved_at_800[0x80];
3439};
3440
3441struct mlx5_ifc_rtr2rts_qp_out_bits {
3442 u8 status[0x8];
3443 u8 reserved_at_8[0x18];
3444
3445 u8 syndrome[0x20];
3446
3447 u8 reserved_at_40[0x40];
3448};
3449
3450struct mlx5_ifc_rtr2rts_qp_in_bits {
3451 u8 opcode[0x10];
3452 u8 reserved_at_10[0x10];
3453
3454 u8 reserved_at_20[0x10];
3455 u8 op_mod[0x10];
3456
3457 u8 reserved_at_40[0x8];
3458 u8 qpn[0x18];
3459
3460 u8 reserved_at_60[0x20];
3461
3462 u8 opt_param_mask[0x20];
3463
3464 u8 reserved_at_a0[0x20];
3465
3466 struct mlx5_ifc_qpc_bits qpc;
3467
3468 u8 reserved_at_800[0x80];
3469};
3470
3471struct mlx5_ifc_rst2init_qp_out_bits {
3472 u8 status[0x8];
3473 u8 reserved_at_8[0x18];
3474
3475 u8 syndrome[0x20];
3476
3477 u8 reserved_at_40[0x40];
3478};
3479
3480struct mlx5_ifc_rst2init_qp_in_bits {
3481 u8 opcode[0x10];
3482 u8 reserved_at_10[0x10];
3483
3484 u8 reserved_at_20[0x10];
3485 u8 op_mod[0x10];
3486
3487 u8 reserved_at_40[0x8];
3488 u8 qpn[0x18];
3489
3490 u8 reserved_at_60[0x20];
3491
3492 u8 opt_param_mask[0x20];
3493
3494 u8 reserved_at_a0[0x20];
3495
3496 struct mlx5_ifc_qpc_bits qpc;
3497
3498 u8 reserved_at_800[0x80];
3499};
3500
3501struct mlx5_ifc_query_xrq_out_bits {
3502 u8 status[0x8];
3503 u8 reserved_at_8[0x18];
3504
3505 u8 syndrome[0x20];
3506
3507 u8 reserved_at_40[0x40];
3508
3509 struct mlx5_ifc_xrqc_bits xrq_context;
3510};
3511
3512struct mlx5_ifc_query_xrq_in_bits {
3513 u8 opcode[0x10];
3514 u8 reserved_at_10[0x10];
3515
3516 u8 reserved_at_20[0x10];
3517 u8 op_mod[0x10];
3518
3519 u8 reserved_at_40[0x8];
3520 u8 xrqn[0x18];
3521
3522 u8 reserved_at_60[0x20];
3523};
3524
3525struct mlx5_ifc_query_xrc_srq_out_bits {
3526 u8 status[0x8];
3527 u8 reserved_at_8[0x18];
3528
3529 u8 syndrome[0x20];
3530
3531 u8 reserved_at_40[0x40];
3532
3533 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3534
3535 u8 reserved_at_280[0x600];
3536
3537 u8 pas[0][0x40];
3538};
3539
3540struct mlx5_ifc_query_xrc_srq_in_bits {
3541 u8 opcode[0x10];
3542 u8 reserved_at_10[0x10];
3543
3544 u8 reserved_at_20[0x10];
3545 u8 op_mod[0x10];
3546
3547 u8 reserved_at_40[0x8];
3548 u8 xrc_srqn[0x18];
3549
3550 u8 reserved_at_60[0x20];
3551};
3552
3553enum {
3554 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3555 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3556};
3557
3558struct mlx5_ifc_query_vport_state_out_bits {
3559 u8 status[0x8];
3560 u8 reserved_at_8[0x18];
3561
3562 u8 syndrome[0x20];
3563
3564 u8 reserved_at_40[0x20];
3565
3566 u8 reserved_at_60[0x18];
3567 u8 admin_state[0x4];
3568 u8 state[0x4];
3569};
3570
3571enum {
3572 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
3573 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
3574};
3575
3576struct mlx5_ifc_query_vport_state_in_bits {
3577 u8 opcode[0x10];
3578 u8 reserved_at_10[0x10];
3579
3580 u8 reserved_at_20[0x10];
3581 u8 op_mod[0x10];
3582
3583 u8 other_vport[0x1];
3584 u8 reserved_at_41[0xf];
3585 u8 vport_number[0x10];
3586
3587 u8 reserved_at_60[0x20];
3588};
3589
3590struct mlx5_ifc_query_vport_counter_out_bits {
3591 u8 status[0x8];
3592 u8 reserved_at_8[0x18];
3593
3594 u8 syndrome[0x20];
3595
3596 u8 reserved_at_40[0x40];
3597
3598 struct mlx5_ifc_traffic_counter_bits received_errors;
3599
3600 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3601
3602 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3603
3604 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3605
3606 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3607
3608 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3609
3610 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3611
3612 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3613
3614 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3615
3616 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3617
3618 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3619
3620 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3621
3622 u8 reserved_at_680[0xa00];
3623};
3624
3625enum {
3626 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3627};
3628
3629struct mlx5_ifc_query_vport_counter_in_bits {
3630 u8 opcode[0x10];
3631 u8 reserved_at_10[0x10];
3632
3633 u8 reserved_at_20[0x10];
3634 u8 op_mod[0x10];
3635
3636 u8 other_vport[0x1];
3637 u8 reserved_at_41[0xb];
3638 u8 port_num[0x4];
3639 u8 vport_number[0x10];
3640
3641 u8 reserved_at_60[0x60];
3642
3643 u8 clear[0x1];
3644 u8 reserved_at_c1[0x1f];
3645
3646 u8 reserved_at_e0[0x20];
3647};
3648
3649struct mlx5_ifc_query_tis_out_bits {
3650 u8 status[0x8];
3651 u8 reserved_at_8[0x18];
3652
3653 u8 syndrome[0x20];
3654
3655 u8 reserved_at_40[0x40];
3656
3657 struct mlx5_ifc_tisc_bits tis_context;
3658};
3659
3660struct mlx5_ifc_query_tis_in_bits {
3661 u8 opcode[0x10];
3662 u8 reserved_at_10[0x10];
3663
3664 u8 reserved_at_20[0x10];
3665 u8 op_mod[0x10];
3666
3667 u8 reserved_at_40[0x8];
3668 u8 tisn[0x18];
3669
3670 u8 reserved_at_60[0x20];
3671};
3672
3673struct mlx5_ifc_query_tir_out_bits {
3674 u8 status[0x8];
3675 u8 reserved_at_8[0x18];
3676
3677 u8 syndrome[0x20];
3678
3679 u8 reserved_at_40[0xc0];
3680
3681 struct mlx5_ifc_tirc_bits tir_context;
3682};
3683
3684struct mlx5_ifc_query_tir_in_bits {
3685 u8 opcode[0x10];
3686 u8 reserved_at_10[0x10];
3687
3688 u8 reserved_at_20[0x10];
3689 u8 op_mod[0x10];
3690
3691 u8 reserved_at_40[0x8];
3692 u8 tirn[0x18];
3693
3694 u8 reserved_at_60[0x20];
3695};
3696
3697struct mlx5_ifc_query_srq_out_bits {
3698 u8 status[0x8];
3699 u8 reserved_at_8[0x18];
3700
3701 u8 syndrome[0x20];
3702
3703 u8 reserved_at_40[0x40];
3704
3705 struct mlx5_ifc_srqc_bits srq_context_entry;
3706
3707 u8 reserved_at_280[0x600];
3708
3709 u8 pas[0][0x40];
3710};
3711
3712struct mlx5_ifc_query_srq_in_bits {
3713 u8 opcode[0x10];
3714 u8 reserved_at_10[0x10];
3715
3716 u8 reserved_at_20[0x10];
3717 u8 op_mod[0x10];
3718
3719 u8 reserved_at_40[0x8];
3720 u8 srqn[0x18];
3721
3722 u8 reserved_at_60[0x20];
3723};
3724
3725struct mlx5_ifc_query_sq_out_bits {
3726 u8 status[0x8];
3727 u8 reserved_at_8[0x18];
3728
3729 u8 syndrome[0x20];
3730
3731 u8 reserved_at_40[0xc0];
3732
3733 struct mlx5_ifc_sqc_bits sq_context;
3734};
3735
3736struct mlx5_ifc_query_sq_in_bits {
3737 u8 opcode[0x10];
3738 u8 reserved_at_10[0x10];
3739
3740 u8 reserved_at_20[0x10];
3741 u8 op_mod[0x10];
3742
3743 u8 reserved_at_40[0x8];
3744 u8 sqn[0x18];
3745
3746 u8 reserved_at_60[0x20];
3747};
3748
3749struct mlx5_ifc_query_special_contexts_out_bits {
3750 u8 status[0x8];
3751 u8 reserved_at_8[0x18];
3752
3753 u8 syndrome[0x20];
3754
3755 u8 dump_fill_mkey[0x20];
3756
3757 u8 resd_lkey[0x20];
3758
3759 u8 null_mkey[0x20];
3760
3761 u8 reserved_at_a0[0x60];
3762};
3763
3764struct mlx5_ifc_query_special_contexts_in_bits {
3765 u8 opcode[0x10];
3766 u8 reserved_at_10[0x10];
3767
3768 u8 reserved_at_20[0x10];
3769 u8 op_mod[0x10];
3770
3771 u8 reserved_at_40[0x40];
3772};
3773
3774struct mlx5_ifc_query_scheduling_element_out_bits {
3775 u8 opcode[0x10];
3776 u8 reserved_at_10[0x10];
3777
3778 u8 reserved_at_20[0x10];
3779 u8 op_mod[0x10];
3780
3781 u8 reserved_at_40[0xc0];
3782
3783 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3784
3785 u8 reserved_at_300[0x100];
3786};
3787
3788enum {
3789 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3790};
3791
3792struct mlx5_ifc_query_scheduling_element_in_bits {
3793 u8 opcode[0x10];
3794 u8 reserved_at_10[0x10];
3795
3796 u8 reserved_at_20[0x10];
3797 u8 op_mod[0x10];
3798
3799 u8 scheduling_hierarchy[0x8];
3800 u8 reserved_at_48[0x18];
3801
3802 u8 scheduling_element_id[0x20];
3803
3804 u8 reserved_at_80[0x180];
3805};
3806
3807struct mlx5_ifc_query_rqt_out_bits {
3808 u8 status[0x8];
3809 u8 reserved_at_8[0x18];
3810
3811 u8 syndrome[0x20];
3812
3813 u8 reserved_at_40[0xc0];
3814
3815 struct mlx5_ifc_rqtc_bits rqt_context;
3816};
3817
3818struct mlx5_ifc_query_rqt_in_bits {
3819 u8 opcode[0x10];
3820 u8 reserved_at_10[0x10];
3821
3822 u8 reserved_at_20[0x10];
3823 u8 op_mod[0x10];
3824
3825 u8 reserved_at_40[0x8];
3826 u8 rqtn[0x18];
3827
3828 u8 reserved_at_60[0x20];
3829};
3830
3831struct mlx5_ifc_query_rq_out_bits {
3832 u8 status[0x8];
3833 u8 reserved_at_8[0x18];
3834
3835 u8 syndrome[0x20];
3836
3837 u8 reserved_at_40[0xc0];
3838
3839 struct mlx5_ifc_rqc_bits rq_context;
3840};
3841
3842struct mlx5_ifc_query_rq_in_bits {
3843 u8 opcode[0x10];
3844 u8 reserved_at_10[0x10];
3845
3846 u8 reserved_at_20[0x10];
3847 u8 op_mod[0x10];
3848
3849 u8 reserved_at_40[0x8];
3850 u8 rqn[0x18];
3851
3852 u8 reserved_at_60[0x20];
3853};
3854
3855struct mlx5_ifc_query_roce_address_out_bits {
3856 u8 status[0x8];
3857 u8 reserved_at_8[0x18];
3858
3859 u8 syndrome[0x20];
3860
3861 u8 reserved_at_40[0x40];
3862
3863 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3864};
3865
3866struct mlx5_ifc_query_roce_address_in_bits {
3867 u8 opcode[0x10];
3868 u8 reserved_at_10[0x10];
3869
3870 u8 reserved_at_20[0x10];
3871 u8 op_mod[0x10];
3872
3873 u8 roce_address_index[0x10];
3874 u8 reserved_at_50[0x10];
3875
3876 u8 reserved_at_60[0x20];
3877};
3878
3879struct mlx5_ifc_query_rmp_out_bits {
3880 u8 status[0x8];
3881 u8 reserved_at_8[0x18];
3882
3883 u8 syndrome[0x20];
3884
3885 u8 reserved_at_40[0xc0];
3886
3887 struct mlx5_ifc_rmpc_bits rmp_context;
3888};
3889
3890struct mlx5_ifc_query_rmp_in_bits {
3891 u8 opcode[0x10];
3892 u8 reserved_at_10[0x10];
3893
3894 u8 reserved_at_20[0x10];
3895 u8 op_mod[0x10];
3896
3897 u8 reserved_at_40[0x8];
3898 u8 rmpn[0x18];
3899
3900 u8 reserved_at_60[0x20];
3901};
3902
3903struct mlx5_ifc_query_qp_out_bits {
3904 u8 status[0x8];
3905 u8 reserved_at_8[0x18];
3906
3907 u8 syndrome[0x20];
3908
3909 u8 reserved_at_40[0x40];
3910
3911 u8 opt_param_mask[0x20];
3912
3913 u8 reserved_at_a0[0x20];
3914
3915 struct mlx5_ifc_qpc_bits qpc;
3916
3917 u8 reserved_at_800[0x80];
3918
3919 u8 pas[0][0x40];
3920};
3921
3922struct mlx5_ifc_query_qp_in_bits {
3923 u8 opcode[0x10];
3924 u8 reserved_at_10[0x10];
3925
3926 u8 reserved_at_20[0x10];
3927 u8 op_mod[0x10];
3928
3929 u8 reserved_at_40[0x8];
3930 u8 qpn[0x18];
3931
3932 u8 reserved_at_60[0x20];
3933};
3934
3935struct mlx5_ifc_query_q_counter_out_bits {
3936 u8 status[0x8];
3937 u8 reserved_at_8[0x18];
3938
3939 u8 syndrome[0x20];
3940
3941 u8 reserved_at_40[0x40];
3942
3943 u8 rx_write_requests[0x20];
3944
3945 u8 reserved_at_a0[0x20];
3946
3947 u8 rx_read_requests[0x20];
3948
3949 u8 reserved_at_e0[0x20];
3950
3951 u8 rx_atomic_requests[0x20];
3952
3953 u8 reserved_at_120[0x20];
3954
3955 u8 rx_dct_connect[0x20];
3956
3957 u8 reserved_at_160[0x20];
3958
3959 u8 out_of_buffer[0x20];
3960
3961 u8 reserved_at_1a0[0x20];
3962
3963 u8 out_of_sequence[0x20];
3964
3965 u8 reserved_at_1e0[0x20];
3966
3967 u8 duplicate_request[0x20];
3968
3969 u8 reserved_at_220[0x20];
3970
3971 u8 rnr_nak_retry_err[0x20];
3972
3973 u8 reserved_at_260[0x20];
3974
3975 u8 packet_seq_err[0x20];
3976
3977 u8 reserved_at_2a0[0x20];
3978
3979 u8 implied_nak_seq_err[0x20];
3980
3981 u8 reserved_at_2e0[0x20];
3982
3983 u8 local_ack_timeout_err[0x20];
3984
3985 u8 reserved_at_320[0xa0];
3986
3987 u8 resp_local_length_error[0x20];
3988
3989 u8 req_local_length_error[0x20];
3990
3991 u8 resp_local_qp_error[0x20];
3992
3993 u8 local_operation_error[0x20];
3994
3995 u8 resp_local_protection[0x20];
3996
3997 u8 req_local_protection[0x20];
3998
3999 u8 resp_cqe_error[0x20];
4000
4001 u8 req_cqe_error[0x20];
4002
4003 u8 req_mw_binding[0x20];
4004
4005 u8 req_bad_response[0x20];
4006
4007 u8 req_remote_invalid_request[0x20];
4008
4009 u8 resp_remote_invalid_request[0x20];
4010
4011 u8 req_remote_access_errors[0x20];
4012
4013 u8 resp_remote_access_errors[0x20];
4014
4015 u8 req_remote_operation_errors[0x20];
4016
4017 u8 req_transport_retries_exceeded[0x20];
4018
4019 u8 cq_overflow[0x20];
4020
4021 u8 resp_cqe_flush_error[0x20];
4022
4023 u8 req_cqe_flush_error[0x20];
4024
4025 u8 reserved_at_620[0x1e0];
4026};
4027
4028struct mlx5_ifc_query_q_counter_in_bits {
4029 u8 opcode[0x10];
4030 u8 reserved_at_10[0x10];
4031
4032 u8 reserved_at_20[0x10];
4033 u8 op_mod[0x10];
4034
4035 u8 reserved_at_40[0x80];
4036
4037 u8 clear[0x1];
4038 u8 reserved_at_c1[0x1f];
4039
4040 u8 reserved_at_e0[0x18];
4041 u8 counter_set_id[0x8];
4042};
4043
4044struct mlx5_ifc_query_pages_out_bits {
4045 u8 status[0x8];
4046 u8 reserved_at_8[0x18];
4047
4048 u8 syndrome[0x20];
4049
4050 u8 reserved_at_40[0x10];
4051 u8 function_id[0x10];
4052
4053 u8 num_pages[0x20];
4054};
4055
4056enum {
4057 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4058 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4059 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4060};
4061
4062struct mlx5_ifc_query_pages_in_bits {
4063 u8 opcode[0x10];
4064 u8 reserved_at_10[0x10];
4065
4066 u8 reserved_at_20[0x10];
4067 u8 op_mod[0x10];
4068
4069 u8 reserved_at_40[0x10];
4070 u8 function_id[0x10];
4071
4072 u8 reserved_at_60[0x20];
4073};
4074
4075struct mlx5_ifc_query_nic_vport_context_out_bits {
4076 u8 status[0x8];
4077 u8 reserved_at_8[0x18];
4078
4079 u8 syndrome[0x20];
4080
4081 u8 reserved_at_40[0x40];
4082
4083 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4084};
4085
4086struct mlx5_ifc_query_nic_vport_context_in_bits {
4087 u8 opcode[0x10];
4088 u8 reserved_at_10[0x10];
4089
4090 u8 reserved_at_20[0x10];
4091 u8 op_mod[0x10];
4092
4093 u8 other_vport[0x1];
4094 u8 reserved_at_41[0xf];
4095 u8 vport_number[0x10];
4096
4097 u8 reserved_at_60[0x5];
4098 u8 allowed_list_type[0x3];
4099 u8 reserved_at_68[0x18];
4100};
4101
4102struct mlx5_ifc_query_mkey_out_bits {
4103 u8 status[0x8];
4104 u8 reserved_at_8[0x18];
4105
4106 u8 syndrome[0x20];
4107
4108 u8 reserved_at_40[0x40];
4109
4110 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4111
4112 u8 reserved_at_280[0x600];
4113
4114 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4115
4116 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4117};
4118
4119struct mlx5_ifc_query_mkey_in_bits {
4120 u8 opcode[0x10];
4121 u8 reserved_at_10[0x10];
4122
4123 u8 reserved_at_20[0x10];
4124 u8 op_mod[0x10];
4125
4126 u8 reserved_at_40[0x8];
4127 u8 mkey_index[0x18];
4128
4129 u8 pg_access[0x1];
4130 u8 reserved_at_61[0x1f];
4131};
4132
4133struct mlx5_ifc_query_mad_demux_out_bits {
4134 u8 status[0x8];
4135 u8 reserved_at_8[0x18];
4136
4137 u8 syndrome[0x20];
4138
4139 u8 reserved_at_40[0x40];
4140
4141 u8 mad_dumux_parameters_block[0x20];
4142};
4143
4144struct mlx5_ifc_query_mad_demux_in_bits {
4145 u8 opcode[0x10];
4146 u8 reserved_at_10[0x10];
4147
4148 u8 reserved_at_20[0x10];
4149 u8 op_mod[0x10];
4150
4151 u8 reserved_at_40[0x40];
4152};
4153
4154struct mlx5_ifc_query_l2_table_entry_out_bits {
4155 u8 status[0x8];
4156 u8 reserved_at_8[0x18];
4157
4158 u8 syndrome[0x20];
4159
4160 u8 reserved_at_40[0xa0];
4161
4162 u8 reserved_at_e0[0x13];
4163 u8 vlan_valid[0x1];
4164 u8 vlan[0xc];
4165
4166 struct mlx5_ifc_mac_address_layout_bits mac_address;
4167
4168 u8 reserved_at_140[0xc0];
4169};
4170
4171struct mlx5_ifc_query_l2_table_entry_in_bits {
4172 u8 opcode[0x10];
4173 u8 reserved_at_10[0x10];
4174
4175 u8 reserved_at_20[0x10];
4176 u8 op_mod[0x10];
4177
4178 u8 reserved_at_40[0x60];
4179
4180 u8 reserved_at_a0[0x8];
4181 u8 table_index[0x18];
4182
4183 u8 reserved_at_c0[0x140];
4184};
4185
4186struct mlx5_ifc_query_issi_out_bits {
4187 u8 status[0x8];
4188 u8 reserved_at_8[0x18];
4189
4190 u8 syndrome[0x20];
4191
4192 u8 reserved_at_40[0x10];
4193 u8 current_issi[0x10];
4194
4195 u8 reserved_at_60[0xa0];
4196
4197 u8 reserved_at_100[76][0x8];
4198 u8 supported_issi_dw0[0x20];
4199};
4200
4201struct mlx5_ifc_query_issi_in_bits {
4202 u8 opcode[0x10];
4203 u8 reserved_at_10[0x10];
4204
4205 u8 reserved_at_20[0x10];
4206 u8 op_mod[0x10];
4207
4208 u8 reserved_at_40[0x40];
4209};
4210
4211struct mlx5_ifc_set_driver_version_out_bits {
4212 u8 status[0x8];
4213 u8 reserved_0[0x18];
4214
4215 u8 syndrome[0x20];
4216 u8 reserved_1[0x40];
4217};
4218
4219struct mlx5_ifc_set_driver_version_in_bits {
4220 u8 opcode[0x10];
4221 u8 reserved_0[0x10];
4222
4223 u8 reserved_1[0x10];
4224 u8 op_mod[0x10];
4225
4226 u8 reserved_2[0x40];
4227 u8 driver_version[64][0x8];
4228};
4229
4230struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4231 u8 status[0x8];
4232 u8 reserved_at_8[0x18];
4233
4234 u8 syndrome[0x20];
4235
4236 u8 reserved_at_40[0x40];
4237
4238 struct mlx5_ifc_pkey_bits pkey[0];
4239};
4240
4241struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4242 u8 opcode[0x10];
4243 u8 reserved_at_10[0x10];
4244
4245 u8 reserved_at_20[0x10];
4246 u8 op_mod[0x10];
4247
4248 u8 other_vport[0x1];
4249 u8 reserved_at_41[0xb];
4250 u8 port_num[0x4];
4251 u8 vport_number[0x10];
4252
4253 u8 reserved_at_60[0x10];
4254 u8 pkey_index[0x10];
4255};
4256
4257enum {
4258 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4259 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4260 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4261};
4262
4263struct mlx5_ifc_query_hca_vport_gid_out_bits {
4264 u8 status[0x8];
4265 u8 reserved_at_8[0x18];
4266
4267 u8 syndrome[0x20];
4268
4269 u8 reserved_at_40[0x20];
4270
4271 u8 gids_num[0x10];
4272 u8 reserved_at_70[0x10];
4273
4274 struct mlx5_ifc_array128_auto_bits gid[0];
4275};
4276
4277struct mlx5_ifc_query_hca_vport_gid_in_bits {
4278 u8 opcode[0x10];
4279 u8 reserved_at_10[0x10];
4280
4281 u8 reserved_at_20[0x10];
4282 u8 op_mod[0x10];
4283
4284 u8 other_vport[0x1];
4285 u8 reserved_at_41[0xb];
4286 u8 port_num[0x4];
4287 u8 vport_number[0x10];
4288
4289 u8 reserved_at_60[0x10];
4290 u8 gid_index[0x10];
4291};
4292
4293struct mlx5_ifc_query_hca_vport_context_out_bits {
4294 u8 status[0x8];
4295 u8 reserved_at_8[0x18];
4296
4297 u8 syndrome[0x20];
4298
4299 u8 reserved_at_40[0x40];
4300
4301 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4302};
4303
4304struct mlx5_ifc_query_hca_vport_context_in_bits {
4305 u8 opcode[0x10];
4306 u8 reserved_at_10[0x10];
4307
4308 u8 reserved_at_20[0x10];
4309 u8 op_mod[0x10];
4310
4311 u8 other_vport[0x1];
4312 u8 reserved_at_41[0xb];
4313 u8 port_num[0x4];
4314 u8 vport_number[0x10];
4315
4316 u8 reserved_at_60[0x20];
4317};
4318
4319struct mlx5_ifc_query_hca_cap_out_bits {
4320 u8 status[0x8];
4321 u8 reserved_at_8[0x18];
4322
4323 u8 syndrome[0x20];
4324
4325 u8 reserved_at_40[0x40];
4326
4327 union mlx5_ifc_hca_cap_union_bits capability;
4328};
4329
4330struct mlx5_ifc_query_hca_cap_in_bits {
4331 u8 opcode[0x10];
4332 u8 reserved_at_10[0x10];
4333
4334 u8 reserved_at_20[0x10];
4335 u8 op_mod[0x10];
4336
4337 u8 reserved_at_40[0x40];
4338};
4339
4340struct mlx5_ifc_query_flow_table_out_bits {
4341 u8 status[0x8];
4342 u8 reserved_at_8[0x18];
4343
4344 u8 syndrome[0x20];
4345
4346 u8 reserved_at_40[0x80];
4347
4348 u8 reserved_at_c0[0x8];
4349 u8 level[0x8];
4350 u8 reserved_at_d0[0x8];
4351 u8 log_size[0x8];
4352
4353 u8 reserved_at_e0[0x120];
4354};
4355
4356struct mlx5_ifc_query_flow_table_in_bits {
4357 u8 opcode[0x10];
4358 u8 reserved_at_10[0x10];
4359
4360 u8 reserved_at_20[0x10];
4361 u8 op_mod[0x10];
4362
4363 u8 reserved_at_40[0x40];
4364
4365 u8 table_type[0x8];
4366 u8 reserved_at_88[0x18];
4367
4368 u8 reserved_at_a0[0x8];
4369 u8 table_id[0x18];
4370
4371 u8 reserved_at_c0[0x140];
4372};
4373
4374struct mlx5_ifc_query_fte_out_bits {
4375 u8 status[0x8];
4376 u8 reserved_at_8[0x18];
4377
4378 u8 syndrome[0x20];
4379
4380 u8 reserved_at_40[0x1c0];
4381
4382 struct mlx5_ifc_flow_context_bits flow_context;
4383};
4384
4385struct mlx5_ifc_query_fte_in_bits {
4386 u8 opcode[0x10];
4387 u8 reserved_at_10[0x10];
4388
4389 u8 reserved_at_20[0x10];
4390 u8 op_mod[0x10];
4391
4392 u8 reserved_at_40[0x40];
4393
4394 u8 table_type[0x8];
4395 u8 reserved_at_88[0x18];
4396
4397 u8 reserved_at_a0[0x8];
4398 u8 table_id[0x18];
4399
4400 u8 reserved_at_c0[0x40];
4401
4402 u8 flow_index[0x20];
4403
4404 u8 reserved_at_120[0xe0];
4405};
4406
4407enum {
4408 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4409 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4410 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4411};
4412
4413struct mlx5_ifc_query_flow_group_out_bits {
4414 u8 status[0x8];
4415 u8 reserved_at_8[0x18];
4416
4417 u8 syndrome[0x20];
4418
4419 u8 reserved_at_40[0xa0];
4420
4421 u8 start_flow_index[0x20];
4422
4423 u8 reserved_at_100[0x20];
4424
4425 u8 end_flow_index[0x20];
4426
4427 u8 reserved_at_140[0xa0];
4428
4429 u8 reserved_at_1e0[0x18];
4430 u8 match_criteria_enable[0x8];
4431
4432 struct mlx5_ifc_fte_match_param_bits match_criteria;
4433
4434 u8 reserved_at_1200[0xe00];
4435};
4436
4437struct mlx5_ifc_query_flow_group_in_bits {
4438 u8 opcode[0x10];
4439 u8 reserved_at_10[0x10];
4440
4441 u8 reserved_at_20[0x10];
4442 u8 op_mod[0x10];
4443
4444 u8 reserved_at_40[0x40];
4445
4446 u8 table_type[0x8];
4447 u8 reserved_at_88[0x18];
4448
4449 u8 reserved_at_a0[0x8];
4450 u8 table_id[0x18];
4451
4452 u8 group_id[0x20];
4453
4454 u8 reserved_at_e0[0x120];
4455};
4456
4457struct mlx5_ifc_query_flow_counter_out_bits {
4458 u8 status[0x8];
4459 u8 reserved_at_8[0x18];
4460
4461 u8 syndrome[0x20];
4462
4463 u8 reserved_at_40[0x40];
4464
4465 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4466};
4467
4468struct mlx5_ifc_query_flow_counter_in_bits {
4469 u8 opcode[0x10];
4470 u8 reserved_at_10[0x10];
4471
4472 u8 reserved_at_20[0x10];
4473 u8 op_mod[0x10];
4474
4475 u8 reserved_at_40[0x80];
4476
4477 u8 clear[0x1];
4478 u8 reserved_at_c1[0xf];
4479 u8 num_of_counters[0x10];
4480
4481 u8 flow_counter_id[0x20];
4482};
4483
4484struct mlx5_ifc_query_esw_vport_context_out_bits {
4485 u8 status[0x8];
4486 u8 reserved_at_8[0x18];
4487
4488 u8 syndrome[0x20];
4489
4490 u8 reserved_at_40[0x40];
4491
4492 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4493};
4494
4495struct mlx5_ifc_query_esw_vport_context_in_bits {
4496 u8 opcode[0x10];
4497 u8 reserved_at_10[0x10];
4498
4499 u8 reserved_at_20[0x10];
4500 u8 op_mod[0x10];
4501
4502 u8 other_vport[0x1];
4503 u8 reserved_at_41[0xf];
4504 u8 vport_number[0x10];
4505
4506 u8 reserved_at_60[0x20];
4507};
4508
4509struct mlx5_ifc_modify_esw_vport_context_out_bits {
4510 u8 status[0x8];
4511 u8 reserved_at_8[0x18];
4512
4513 u8 syndrome[0x20];
4514
4515 u8 reserved_at_40[0x40];
4516};
4517
4518struct mlx5_ifc_esw_vport_context_fields_select_bits {
4519 u8 reserved_at_0[0x1c];
4520 u8 vport_cvlan_insert[0x1];
4521 u8 vport_svlan_insert[0x1];
4522 u8 vport_cvlan_strip[0x1];
4523 u8 vport_svlan_strip[0x1];
4524};
4525
4526struct mlx5_ifc_modify_esw_vport_context_in_bits {
4527 u8 opcode[0x10];
4528 u8 reserved_at_10[0x10];
4529
4530 u8 reserved_at_20[0x10];
4531 u8 op_mod[0x10];
4532
4533 u8 other_vport[0x1];
4534 u8 reserved_at_41[0xf];
4535 u8 vport_number[0x10];
4536
4537 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4538
4539 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4540};
4541
4542struct mlx5_ifc_query_eq_out_bits {
4543 u8 status[0x8];
4544 u8 reserved_at_8[0x18];
4545
4546 u8 syndrome[0x20];
4547
4548 u8 reserved_at_40[0x40];
4549
4550 struct mlx5_ifc_eqc_bits eq_context_entry;
4551
4552 u8 reserved_at_280[0x40];
4553
4554 u8 event_bitmask[0x40];
4555
4556 u8 reserved_at_300[0x580];
4557
4558 u8 pas[0][0x40];
4559};
4560
4561struct mlx5_ifc_query_eq_in_bits {
4562 u8 opcode[0x10];
4563 u8 reserved_at_10[0x10];
4564
4565 u8 reserved_at_20[0x10];
4566 u8 op_mod[0x10];
4567
4568 u8 reserved_at_40[0x18];
4569 u8 eq_number[0x8];
4570
4571 u8 reserved_at_60[0x20];
4572};
4573
4574struct mlx5_ifc_encap_header_in_bits {
4575 u8 reserved_at_0[0x5];
4576 u8 header_type[0x3];
4577 u8 reserved_at_8[0xe];
4578 u8 encap_header_size[0xa];
4579
4580 u8 reserved_at_20[0x10];
4581 u8 encap_header[2][0x8];
4582
4583 u8 more_encap_header[0][0x8];
4584};
4585
4586struct mlx5_ifc_query_encap_header_out_bits {
4587 u8 status[0x8];
4588 u8 reserved_at_8[0x18];
4589
4590 u8 syndrome[0x20];
4591
4592 u8 reserved_at_40[0xa0];
4593
4594 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4595};
4596
4597struct mlx5_ifc_query_encap_header_in_bits {
4598 u8 opcode[0x10];
4599 u8 reserved_at_10[0x10];
4600
4601 u8 reserved_at_20[0x10];
4602 u8 op_mod[0x10];
4603
4604 u8 encap_id[0x20];
4605
4606 u8 reserved_at_60[0xa0];
4607};
4608
4609struct mlx5_ifc_alloc_encap_header_out_bits {
4610 u8 status[0x8];
4611 u8 reserved_at_8[0x18];
4612
4613 u8 syndrome[0x20];
4614
4615 u8 encap_id[0x20];
4616
4617 u8 reserved_at_60[0x20];
4618};
4619
4620struct mlx5_ifc_alloc_encap_header_in_bits {
4621 u8 opcode[0x10];
4622 u8 reserved_at_10[0x10];
4623
4624 u8 reserved_at_20[0x10];
4625 u8 op_mod[0x10];
4626
4627 u8 reserved_at_40[0xa0];
4628
4629 struct mlx5_ifc_encap_header_in_bits encap_header;
4630};
4631
4632struct mlx5_ifc_dealloc_encap_header_out_bits {
4633 u8 status[0x8];
4634 u8 reserved_at_8[0x18];
4635
4636 u8 syndrome[0x20];
4637
4638 u8 reserved_at_40[0x40];
4639};
4640
4641struct mlx5_ifc_dealloc_encap_header_in_bits {
4642 u8 opcode[0x10];
4643 u8 reserved_at_10[0x10];
4644
4645 u8 reserved_20[0x10];
4646 u8 op_mod[0x10];
4647
4648 u8 encap_id[0x20];
4649
4650 u8 reserved_60[0x20];
4651};
4652
4653struct mlx5_ifc_set_action_in_bits {
4654 u8 action_type[0x4];
4655 u8 field[0xc];
4656 u8 reserved_at_10[0x3];
4657 u8 offset[0x5];
4658 u8 reserved_at_18[0x3];
4659 u8 length[0x5];
4660
4661 u8 data[0x20];
4662};
4663
4664struct mlx5_ifc_add_action_in_bits {
4665 u8 action_type[0x4];
4666 u8 field[0xc];
4667 u8 reserved_at_10[0x10];
4668
4669 u8 data[0x20];
4670};
4671
4672union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4673 struct mlx5_ifc_set_action_in_bits set_action_in;
4674 struct mlx5_ifc_add_action_in_bits add_action_in;
4675 u8 reserved_at_0[0x40];
4676};
4677
4678enum {
4679 MLX5_ACTION_TYPE_SET = 0x1,
4680 MLX5_ACTION_TYPE_ADD = 0x2,
4681};
4682
4683enum {
4684 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
4685 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
4686 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
4687 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
4688 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
4689 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
4690 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
4691 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
4692 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
4693 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
4694 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
4695 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
4696 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
4697 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
4698 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
4699 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
4700 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
4701 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
4702 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
4703 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4704 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4705 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
4706 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4707};
4708
4709struct mlx5_ifc_alloc_modify_header_context_out_bits {
4710 u8 status[0x8];
4711 u8 reserved_at_8[0x18];
4712
4713 u8 syndrome[0x20];
4714
4715 u8 modify_header_id[0x20];
4716
4717 u8 reserved_at_60[0x20];
4718};
4719
4720struct mlx5_ifc_alloc_modify_header_context_in_bits {
4721 u8 opcode[0x10];
4722 u8 reserved_at_10[0x10];
4723
4724 u8 reserved_at_20[0x10];
4725 u8 op_mod[0x10];
4726
4727 u8 reserved_at_40[0x20];
4728
4729 u8 table_type[0x8];
4730 u8 reserved_at_68[0x10];
4731 u8 num_of_actions[0x8];
4732
4733 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4734};
4735
4736struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4737 u8 status[0x8];
4738 u8 reserved_at_8[0x18];
4739
4740 u8 syndrome[0x20];
4741
4742 u8 reserved_at_40[0x40];
4743};
4744
4745struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4746 u8 opcode[0x10];
4747 u8 reserved_at_10[0x10];
4748
4749 u8 reserved_at_20[0x10];
4750 u8 op_mod[0x10];
4751
4752 u8 modify_header_id[0x20];
4753
4754 u8 reserved_at_60[0x20];
4755};
4756
4757struct mlx5_ifc_query_dct_out_bits {
4758 u8 status[0x8];
4759 u8 reserved_at_8[0x18];
4760
4761 u8 syndrome[0x20];
4762
4763 u8 reserved_at_40[0x40];
4764
4765 struct mlx5_ifc_dctc_bits dct_context_entry;
4766
4767 u8 reserved_at_280[0x180];
4768};
4769
4770struct mlx5_ifc_query_dct_in_bits {
4771 u8 opcode[0x10];
4772 u8 reserved_at_10[0x10];
4773
4774 u8 reserved_at_20[0x10];
4775 u8 op_mod[0x10];
4776
4777 u8 reserved_at_40[0x8];
4778 u8 dctn[0x18];
4779
4780 u8 reserved_at_60[0x20];
4781};
4782
4783struct mlx5_ifc_query_cq_out_bits {
4784 u8 status[0x8];
4785 u8 reserved_at_8[0x18];
4786
4787 u8 syndrome[0x20];
4788
4789 u8 reserved_at_40[0x40];
4790
4791 struct mlx5_ifc_cqc_bits cq_context;
4792
4793 u8 reserved_at_280[0x600];
4794
4795 u8 pas[0][0x40];
4796};
4797
4798struct mlx5_ifc_query_cq_in_bits {
4799 u8 opcode[0x10];
4800 u8 reserved_at_10[0x10];
4801
4802 u8 reserved_at_20[0x10];
4803 u8 op_mod[0x10];
4804
4805 u8 reserved_at_40[0x8];
4806 u8 cqn[0x18];
4807
4808 u8 reserved_at_60[0x20];
4809};
4810
4811struct mlx5_ifc_query_cong_status_out_bits {
4812 u8 status[0x8];
4813 u8 reserved_at_8[0x18];
4814
4815 u8 syndrome[0x20];
4816
4817 u8 reserved_at_40[0x20];
4818
4819 u8 enable[0x1];
4820 u8 tag_enable[0x1];
4821 u8 reserved_at_62[0x1e];
4822};
4823
4824struct mlx5_ifc_query_cong_status_in_bits {
4825 u8 opcode[0x10];
4826 u8 reserved_at_10[0x10];
4827
4828 u8 reserved_at_20[0x10];
4829 u8 op_mod[0x10];
4830
4831 u8 reserved_at_40[0x18];
4832 u8 priority[0x4];
4833 u8 cong_protocol[0x4];
4834
4835 u8 reserved_at_60[0x20];
4836};
4837
4838struct mlx5_ifc_query_cong_statistics_out_bits {
4839 u8 status[0x8];
4840 u8 reserved_at_8[0x18];
4841
4842 u8 syndrome[0x20];
4843
4844 u8 reserved_at_40[0x40];
4845
4846 u8 rp_cur_flows[0x20];
4847
4848 u8 sum_flows[0x20];
4849
4850 u8 rp_cnp_ignored_high[0x20];
4851
4852 u8 rp_cnp_ignored_low[0x20];
4853
4854 u8 rp_cnp_handled_high[0x20];
4855
4856 u8 rp_cnp_handled_low[0x20];
4857
4858 u8 reserved_at_140[0x100];
4859
4860 u8 time_stamp_high[0x20];
4861
4862 u8 time_stamp_low[0x20];
4863
4864 u8 accumulators_period[0x20];
4865
4866 u8 np_ecn_marked_roce_packets_high[0x20];
4867
4868 u8 np_ecn_marked_roce_packets_low[0x20];
4869
4870 u8 np_cnp_sent_high[0x20];
4871
4872 u8 np_cnp_sent_low[0x20];
4873
4874 u8 reserved_at_320[0x560];
4875};
4876
4877struct mlx5_ifc_query_cong_statistics_in_bits {
4878 u8 opcode[0x10];
4879 u8 reserved_at_10[0x10];
4880
4881 u8 reserved_at_20[0x10];
4882 u8 op_mod[0x10];
4883
4884 u8 clear[0x1];
4885 u8 reserved_at_41[0x1f];
4886
4887 u8 reserved_at_60[0x20];
4888};
4889
4890struct mlx5_ifc_query_cong_params_out_bits {
4891 u8 status[0x8];
4892 u8 reserved_at_8[0x18];
4893
4894 u8 syndrome[0x20];
4895
4896 u8 reserved_at_40[0x40];
4897
4898 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4899};
4900
4901struct mlx5_ifc_query_cong_params_in_bits {
4902 u8 opcode[0x10];
4903 u8 reserved_at_10[0x10];
4904
4905 u8 reserved_at_20[0x10];
4906 u8 op_mod[0x10];
4907
4908 u8 reserved_at_40[0x1c];
4909 u8 cong_protocol[0x4];
4910
4911 u8 reserved_at_60[0x20];
4912};
4913
4914struct mlx5_ifc_query_adapter_out_bits {
4915 u8 status[0x8];
4916 u8 reserved_at_8[0x18];
4917
4918 u8 syndrome[0x20];
4919
4920 u8 reserved_at_40[0x40];
4921
4922 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4923};
4924
4925struct mlx5_ifc_query_adapter_in_bits {
4926 u8 opcode[0x10];
4927 u8 reserved_at_10[0x10];
4928
4929 u8 reserved_at_20[0x10];
4930 u8 op_mod[0x10];
4931
4932 u8 reserved_at_40[0x40];
4933};
4934
4935struct mlx5_ifc_qp_2rst_out_bits {
4936 u8 status[0x8];
4937 u8 reserved_at_8[0x18];
4938
4939 u8 syndrome[0x20];
4940
4941 u8 reserved_at_40[0x40];
4942};
4943
4944struct mlx5_ifc_qp_2rst_in_bits {
4945 u8 opcode[0x10];
4946 u8 reserved_at_10[0x10];
4947
4948 u8 reserved_at_20[0x10];
4949 u8 op_mod[0x10];
4950
4951 u8 reserved_at_40[0x8];
4952 u8 qpn[0x18];
4953
4954 u8 reserved_at_60[0x20];
4955};
4956
4957struct mlx5_ifc_qp_2err_out_bits {
4958 u8 status[0x8];
4959 u8 reserved_at_8[0x18];
4960
4961 u8 syndrome[0x20];
4962
4963 u8 reserved_at_40[0x40];
4964};
4965
4966struct mlx5_ifc_qp_2err_in_bits {
4967 u8 opcode[0x10];
4968 u8 reserved_at_10[0x10];
4969
4970 u8 reserved_at_20[0x10];
4971 u8 op_mod[0x10];
4972
4973 u8 reserved_at_40[0x8];
4974 u8 qpn[0x18];
4975
4976 u8 reserved_at_60[0x20];
4977};
4978
4979struct mlx5_ifc_page_fault_resume_out_bits {
4980 u8 status[0x8];
4981 u8 reserved_at_8[0x18];
4982
4983 u8 syndrome[0x20];
4984
4985 u8 reserved_at_40[0x40];
4986};
4987
4988struct mlx5_ifc_page_fault_resume_in_bits {
4989 u8 opcode[0x10];
4990 u8 reserved_at_10[0x10];
4991
4992 u8 reserved_at_20[0x10];
4993 u8 op_mod[0x10];
4994
4995 u8 error[0x1];
4996 u8 reserved_at_41[0x4];
4997 u8 page_fault_type[0x3];
4998 u8 wq_number[0x18];
4999
5000 u8 reserved_at_60[0x8];
5001 u8 token[0x18];
5002};
5003
5004struct mlx5_ifc_nop_out_bits {
5005 u8 status[0x8];
5006 u8 reserved_at_8[0x18];
5007
5008 u8 syndrome[0x20];
5009
5010 u8 reserved_at_40[0x40];
5011};
5012
5013struct mlx5_ifc_nop_in_bits {
5014 u8 opcode[0x10];
5015 u8 reserved_at_10[0x10];
5016
5017 u8 reserved_at_20[0x10];
5018 u8 op_mod[0x10];
5019
5020 u8 reserved_at_40[0x40];
5021};
5022
5023struct mlx5_ifc_modify_vport_state_out_bits {
5024 u8 status[0x8];
5025 u8 reserved_at_8[0x18];
5026
5027 u8 syndrome[0x20];
5028
5029 u8 reserved_at_40[0x40];
5030};
5031
5032struct mlx5_ifc_modify_vport_state_in_bits {
5033 u8 opcode[0x10];
5034 u8 reserved_at_10[0x10];
5035
5036 u8 reserved_at_20[0x10];
5037 u8 op_mod[0x10];
5038
5039 u8 other_vport[0x1];
5040 u8 reserved_at_41[0xf];
5041 u8 vport_number[0x10];
5042
5043 u8 reserved_at_60[0x18];
5044 u8 admin_state[0x4];
5045 u8 reserved_at_7c[0x4];
5046};
5047
5048struct mlx5_ifc_modify_tis_out_bits {
5049 u8 status[0x8];
5050 u8 reserved_at_8[0x18];
5051
5052 u8 syndrome[0x20];
5053
5054 u8 reserved_at_40[0x40];
5055};
5056
5057struct mlx5_ifc_modify_tis_bitmask_bits {
5058 u8 reserved_at_0[0x20];
5059
5060 u8 reserved_at_20[0x1d];
5061 u8 lag_tx_port_affinity[0x1];
5062 u8 strict_lag_tx_port_affinity[0x1];
5063 u8 prio[0x1];
5064};
5065
5066struct mlx5_ifc_modify_tis_in_bits {
5067 u8 opcode[0x10];
5068 u8 reserved_at_10[0x10];
5069
5070 u8 reserved_at_20[0x10];
5071 u8 op_mod[0x10];
5072
5073 u8 reserved_at_40[0x8];
5074 u8 tisn[0x18];
5075
5076 u8 reserved_at_60[0x20];
5077
5078 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5079
5080 u8 reserved_at_c0[0x40];
5081
5082 struct mlx5_ifc_tisc_bits ctx;
5083};
5084
5085struct mlx5_ifc_modify_tir_bitmask_bits {
5086 u8 reserved_at_0[0x20];
5087
5088 u8 reserved_at_20[0x1b];
5089 u8 self_lb_en[0x1];
5090 u8 reserved_at_3c[0x1];
5091 u8 hash[0x1];
5092 u8 reserved_at_3e[0x1];
5093 u8 lro[0x1];
5094};
5095
5096struct mlx5_ifc_modify_tir_out_bits {
5097 u8 status[0x8];
5098 u8 reserved_at_8[0x18];
5099
5100 u8 syndrome[0x20];
5101
5102 u8 reserved_at_40[0x40];
5103};
5104
5105struct mlx5_ifc_modify_tir_in_bits {
5106 u8 opcode[0x10];
5107 u8 reserved_at_10[0x10];
5108
5109 u8 reserved_at_20[0x10];
5110 u8 op_mod[0x10];
5111
5112 u8 reserved_at_40[0x8];
5113 u8 tirn[0x18];
5114
5115 u8 reserved_at_60[0x20];
5116
5117 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5118
5119 u8 reserved_at_c0[0x40];
5120
5121 struct mlx5_ifc_tirc_bits ctx;
5122};
5123
5124struct mlx5_ifc_modify_sq_out_bits {
5125 u8 status[0x8];
5126 u8 reserved_at_8[0x18];
5127
5128 u8 syndrome[0x20];
5129
5130 u8 reserved_at_40[0x40];
5131};
5132
5133struct mlx5_ifc_modify_sq_in_bits {
5134 u8 opcode[0x10];
5135 u8 reserved_at_10[0x10];
5136
5137 u8 reserved_at_20[0x10];
5138 u8 op_mod[0x10];
5139
5140 u8 sq_state[0x4];
5141 u8 reserved_at_44[0x4];
5142 u8 sqn[0x18];
5143
5144 u8 reserved_at_60[0x20];
5145
5146 u8 modify_bitmask[0x40];
5147
5148 u8 reserved_at_c0[0x40];
5149
5150 struct mlx5_ifc_sqc_bits ctx;
5151};
5152
5153struct mlx5_ifc_modify_scheduling_element_out_bits {
5154 u8 status[0x8];
5155 u8 reserved_at_8[0x18];
5156
5157 u8 syndrome[0x20];
5158
5159 u8 reserved_at_40[0x1c0];
5160};
5161
5162enum {
5163 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5164 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5165};
5166
5167struct mlx5_ifc_modify_scheduling_element_in_bits {
5168 u8 opcode[0x10];
5169 u8 reserved_at_10[0x10];
5170
5171 u8 reserved_at_20[0x10];
5172 u8 op_mod[0x10];
5173
5174 u8 scheduling_hierarchy[0x8];
5175 u8 reserved_at_48[0x18];
5176
5177 u8 scheduling_element_id[0x20];
5178
5179 u8 reserved_at_80[0x20];
5180
5181 u8 modify_bitmask[0x20];
5182
5183 u8 reserved_at_c0[0x40];
5184
5185 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5186
5187 u8 reserved_at_300[0x100];
5188};
5189
5190struct mlx5_ifc_modify_rqt_out_bits {
5191 u8 status[0x8];
5192 u8 reserved_at_8[0x18];
5193
5194 u8 syndrome[0x20];
5195
5196 u8 reserved_at_40[0x40];
5197};
5198
5199struct mlx5_ifc_rqt_bitmask_bits {
5200 u8 reserved_at_0[0x20];
5201
5202 u8 reserved_at_20[0x1f];
5203 u8 rqn_list[0x1];
5204};
5205
5206struct mlx5_ifc_modify_rqt_in_bits {
5207 u8 opcode[0x10];
5208 u8 reserved_at_10[0x10];
5209
5210 u8 reserved_at_20[0x10];
5211 u8 op_mod[0x10];
5212
5213 u8 reserved_at_40[0x8];
5214 u8 rqtn[0x18];
5215
5216 u8 reserved_at_60[0x20];
5217
5218 struct mlx5_ifc_rqt_bitmask_bits bitmask;
5219
5220 u8 reserved_at_c0[0x40];
5221
5222 struct mlx5_ifc_rqtc_bits ctx;
5223};
5224
5225struct mlx5_ifc_modify_rq_out_bits {
5226 u8 status[0x8];
5227 u8 reserved_at_8[0x18];
5228
5229 u8 syndrome[0x20];
5230
5231 u8 reserved_at_40[0x40];
5232};
5233
5234enum {
5235 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5236 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5237 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5238};
5239
5240struct mlx5_ifc_modify_rq_in_bits {
5241 u8 opcode[0x10];
5242 u8 reserved_at_10[0x10];
5243
5244 u8 reserved_at_20[0x10];
5245 u8 op_mod[0x10];
5246
5247 u8 rq_state[0x4];
5248 u8 reserved_at_44[0x4];
5249 u8 rqn[0x18];
5250
5251 u8 reserved_at_60[0x20];
5252
5253 u8 modify_bitmask[0x40];
5254
5255 u8 reserved_at_c0[0x40];
5256
5257 struct mlx5_ifc_rqc_bits ctx;
5258};
5259
5260struct mlx5_ifc_modify_rmp_out_bits {
5261 u8 status[0x8];
5262 u8 reserved_at_8[0x18];
5263
5264 u8 syndrome[0x20];
5265
5266 u8 reserved_at_40[0x40];
5267};
5268
5269struct mlx5_ifc_rmp_bitmask_bits {
5270 u8 reserved_at_0[0x20];
5271
5272 u8 reserved_at_20[0x1f];
5273 u8 lwm[0x1];
5274};
5275
5276struct mlx5_ifc_modify_rmp_in_bits {
5277 u8 opcode[0x10];
5278 u8 reserved_at_10[0x10];
5279
5280 u8 reserved_at_20[0x10];
5281 u8 op_mod[0x10];
5282
5283 u8 rmp_state[0x4];
5284 u8 reserved_at_44[0x4];
5285 u8 rmpn[0x18];
5286
5287 u8 reserved_at_60[0x20];
5288
5289 struct mlx5_ifc_rmp_bitmask_bits bitmask;
5290
5291 u8 reserved_at_c0[0x40];
5292
5293 struct mlx5_ifc_rmpc_bits ctx;
5294};
5295
5296struct mlx5_ifc_modify_nic_vport_context_out_bits {
5297 u8 status[0x8];
5298 u8 reserved_at_8[0x18];
5299
5300 u8 syndrome[0x20];
5301
5302 u8 reserved_at_40[0x40];
5303};
5304
5305struct mlx5_ifc_modify_nic_vport_field_select_bits {
5306 u8 reserved_at_0[0x14];
5307 u8 disable_uc_local_lb[0x1];
5308 u8 disable_mc_local_lb[0x1];
5309 u8 node_guid[0x1];
5310 u8 port_guid[0x1];
5311 u8 min_inline[0x1];
5312 u8 mtu[0x1];
5313 u8 change_event[0x1];
5314 u8 promisc[0x1];
5315 u8 permanent_address[0x1];
5316 u8 addresses_list[0x1];
5317 u8 roce_en[0x1];
5318 u8 reserved_at_1f[0x1];
5319};
5320
5321struct mlx5_ifc_modify_nic_vport_context_in_bits {
5322 u8 opcode[0x10];
5323 u8 reserved_at_10[0x10];
5324
5325 u8 reserved_at_20[0x10];
5326 u8 op_mod[0x10];
5327
5328 u8 other_vport[0x1];
5329 u8 reserved_at_41[0xf];
5330 u8 vport_number[0x10];
5331
5332 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5333
5334 u8 reserved_at_80[0x780];
5335
5336 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5337};
5338
5339struct mlx5_ifc_modify_hca_vport_context_out_bits {
5340 u8 status[0x8];
5341 u8 reserved_at_8[0x18];
5342
5343 u8 syndrome[0x20];
5344
5345 u8 reserved_at_40[0x40];
5346};
5347
5348struct mlx5_ifc_modify_hca_vport_context_in_bits {
5349 u8 opcode[0x10];
5350 u8 reserved_at_10[0x10];
5351
5352 u8 reserved_at_20[0x10];
5353 u8 op_mod[0x10];
5354
5355 u8 other_vport[0x1];
5356 u8 reserved_at_41[0xb];
5357 u8 port_num[0x4];
5358 u8 vport_number[0x10];
5359
5360 u8 reserved_at_60[0x20];
5361
5362 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5363};
5364
5365struct mlx5_ifc_modify_cq_out_bits {
5366 u8 status[0x8];
5367 u8 reserved_at_8[0x18];
5368
5369 u8 syndrome[0x20];
5370
5371 u8 reserved_at_40[0x40];
5372};
5373
5374enum {
5375 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5376 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5377};
5378
5379struct mlx5_ifc_modify_cq_in_bits {
5380 u8 opcode[0x10];
5381 u8 reserved_at_10[0x10];
5382
5383 u8 reserved_at_20[0x10];
5384 u8 op_mod[0x10];
5385
5386 u8 reserved_at_40[0x8];
5387 u8 cqn[0x18];
5388
5389 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5390
5391 struct mlx5_ifc_cqc_bits cq_context;
5392
5393 u8 reserved_at_280[0x600];
5394
5395 u8 pas[0][0x40];
5396};
5397
5398struct mlx5_ifc_modify_cong_status_out_bits {
5399 u8 status[0x8];
5400 u8 reserved_at_8[0x18];
5401
5402 u8 syndrome[0x20];
5403
5404 u8 reserved_at_40[0x40];
5405};
5406
5407struct mlx5_ifc_modify_cong_status_in_bits {
5408 u8 opcode[0x10];
5409 u8 reserved_at_10[0x10];
5410
5411 u8 reserved_at_20[0x10];
5412 u8 op_mod[0x10];
5413
5414 u8 reserved_at_40[0x18];
5415 u8 priority[0x4];
5416 u8 cong_protocol[0x4];
5417
5418 u8 enable[0x1];
5419 u8 tag_enable[0x1];
5420 u8 reserved_at_62[0x1e];
5421};
5422
5423struct mlx5_ifc_modify_cong_params_out_bits {
5424 u8 status[0x8];
5425 u8 reserved_at_8[0x18];
5426
5427 u8 syndrome[0x20];
5428
5429 u8 reserved_at_40[0x40];
5430};
5431
5432struct mlx5_ifc_modify_cong_params_in_bits {
5433 u8 opcode[0x10];
5434 u8 reserved_at_10[0x10];
5435
5436 u8 reserved_at_20[0x10];
5437 u8 op_mod[0x10];
5438
5439 u8 reserved_at_40[0x1c];
5440 u8 cong_protocol[0x4];
5441
5442 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5443
5444 u8 reserved_at_80[0x80];
5445
5446 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5447};
5448
5449struct mlx5_ifc_manage_pages_out_bits {
5450 u8 status[0x8];
5451 u8 reserved_at_8[0x18];
5452
5453 u8 syndrome[0x20];
5454
5455 u8 output_num_entries[0x20];
5456
5457 u8 reserved_at_60[0x20];
5458
5459 u8 pas[0][0x40];
5460};
5461
5462enum {
5463 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5464 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5465 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5466};
5467
5468struct mlx5_ifc_manage_pages_in_bits {
5469 u8 opcode[0x10];
5470 u8 reserved_at_10[0x10];
5471
5472 u8 reserved_at_20[0x10];
5473 u8 op_mod[0x10];
5474
5475 u8 reserved_at_40[0x10];
5476 u8 function_id[0x10];
5477
5478 u8 input_num_entries[0x20];
5479
5480 u8 pas[0][0x40];
5481};
5482
5483struct mlx5_ifc_mad_ifc_out_bits {
5484 u8 status[0x8];
5485 u8 reserved_at_8[0x18];
5486
5487 u8 syndrome[0x20];
5488
5489 u8 reserved_at_40[0x40];
5490
5491 u8 response_mad_packet[256][0x8];
5492};
5493
5494struct mlx5_ifc_mad_ifc_in_bits {
5495 u8 opcode[0x10];
5496 u8 reserved_at_10[0x10];
5497
5498 u8 reserved_at_20[0x10];
5499 u8 op_mod[0x10];
5500
5501 u8 remote_lid[0x10];
5502 u8 reserved_at_50[0x8];
5503 u8 port[0x8];
5504
5505 u8 reserved_at_60[0x20];
5506
5507 u8 mad[256][0x8];
5508};
5509
5510struct mlx5_ifc_init_hca_out_bits {
5511 u8 status[0x8];
5512 u8 reserved_at_8[0x18];
5513
5514 u8 syndrome[0x20];
5515
5516 u8 reserved_at_40[0x40];
5517};
5518
5519struct mlx5_ifc_init_hca_in_bits {
5520 u8 opcode[0x10];
5521 u8 reserved_at_10[0x10];
5522
5523 u8 reserved_at_20[0x10];
5524 u8 op_mod[0x10];
5525
5526 u8 reserved_at_40[0x40];
5527};
5528
5529struct mlx5_ifc_init2rtr_qp_out_bits {
5530 u8 status[0x8];
5531 u8 reserved_at_8[0x18];
5532
5533 u8 syndrome[0x20];
5534
5535 u8 reserved_at_40[0x40];
5536};
5537
5538struct mlx5_ifc_init2rtr_qp_in_bits {
5539 u8 opcode[0x10];
5540 u8 reserved_at_10[0x10];
5541
5542 u8 reserved_at_20[0x10];
5543 u8 op_mod[0x10];
5544
5545 u8 reserved_at_40[0x8];
5546 u8 qpn[0x18];
5547
5548 u8 reserved_at_60[0x20];
5549
5550 u8 opt_param_mask[0x20];
5551
5552 u8 reserved_at_a0[0x20];
5553
5554 struct mlx5_ifc_qpc_bits qpc;
5555
5556 u8 reserved_at_800[0x80];
5557};
5558
5559struct mlx5_ifc_init2init_qp_out_bits {
5560 u8 status[0x8];
5561 u8 reserved_at_8[0x18];
5562
5563 u8 syndrome[0x20];
5564
5565 u8 reserved_at_40[0x40];
5566};
5567
5568struct mlx5_ifc_init2init_qp_in_bits {
5569 u8 opcode[0x10];
5570 u8 reserved_at_10[0x10];
5571
5572 u8 reserved_at_20[0x10];
5573 u8 op_mod[0x10];
5574
5575 u8 reserved_at_40[0x8];
5576 u8 qpn[0x18];
5577
5578 u8 reserved_at_60[0x20];
5579
5580 u8 opt_param_mask[0x20];
5581
5582 u8 reserved_at_a0[0x20];
5583
5584 struct mlx5_ifc_qpc_bits qpc;
5585
5586 u8 reserved_at_800[0x80];
5587};
5588
5589struct mlx5_ifc_get_dropped_packet_log_out_bits {
5590 u8 status[0x8];
5591 u8 reserved_at_8[0x18];
5592
5593 u8 syndrome[0x20];
5594
5595 u8 reserved_at_40[0x40];
5596
5597 u8 packet_headers_log[128][0x8];
5598
5599 u8 packet_syndrome[64][0x8];
5600};
5601
5602struct mlx5_ifc_get_dropped_packet_log_in_bits {
5603 u8 opcode[0x10];
5604 u8 reserved_at_10[0x10];
5605
5606 u8 reserved_at_20[0x10];
5607 u8 op_mod[0x10];
5608
5609 u8 reserved_at_40[0x40];
5610};
5611
5612struct mlx5_ifc_gen_eqe_in_bits {
5613 u8 opcode[0x10];
5614 u8 reserved_at_10[0x10];
5615
5616 u8 reserved_at_20[0x10];
5617 u8 op_mod[0x10];
5618
5619 u8 reserved_at_40[0x18];
5620 u8 eq_number[0x8];
5621
5622 u8 reserved_at_60[0x20];
5623
5624 u8 eqe[64][0x8];
5625};
5626
5627struct mlx5_ifc_gen_eq_out_bits {
5628 u8 status[0x8];
5629 u8 reserved_at_8[0x18];
5630
5631 u8 syndrome[0x20];
5632
5633 u8 reserved_at_40[0x40];
5634};
5635
5636struct mlx5_ifc_enable_hca_out_bits {
5637 u8 status[0x8];
5638 u8 reserved_at_8[0x18];
5639
5640 u8 syndrome[0x20];
5641
5642 u8 reserved_at_40[0x20];
5643};
5644
5645struct mlx5_ifc_enable_hca_in_bits {
5646 u8 opcode[0x10];
5647 u8 reserved_at_10[0x10];
5648
5649 u8 reserved_at_20[0x10];
5650 u8 op_mod[0x10];
5651
5652 u8 reserved_at_40[0x10];
5653 u8 function_id[0x10];
5654
5655 u8 reserved_at_60[0x20];
5656};
5657
5658struct mlx5_ifc_drain_dct_out_bits {
5659 u8 status[0x8];
5660 u8 reserved_at_8[0x18];
5661
5662 u8 syndrome[0x20];
5663
5664 u8 reserved_at_40[0x40];
5665};
5666
5667struct mlx5_ifc_drain_dct_in_bits {
5668 u8 opcode[0x10];
5669 u8 reserved_at_10[0x10];
5670
5671 u8 reserved_at_20[0x10];
5672 u8 op_mod[0x10];
5673
5674 u8 reserved_at_40[0x8];
5675 u8 dctn[0x18];
5676
5677 u8 reserved_at_60[0x20];
5678};
5679
5680struct mlx5_ifc_disable_hca_out_bits {
5681 u8 status[0x8];
5682 u8 reserved_at_8[0x18];
5683
5684 u8 syndrome[0x20];
5685
5686 u8 reserved_at_40[0x20];
5687};
5688
5689struct mlx5_ifc_disable_hca_in_bits {
5690 u8 opcode[0x10];
5691 u8 reserved_at_10[0x10];
5692
5693 u8 reserved_at_20[0x10];
5694 u8 op_mod[0x10];
5695
5696 u8 reserved_at_40[0x10];
5697 u8 function_id[0x10];
5698
5699 u8 reserved_at_60[0x20];
5700};
5701
5702struct mlx5_ifc_detach_from_mcg_out_bits {
5703 u8 status[0x8];
5704 u8 reserved_at_8[0x18];
5705
5706 u8 syndrome[0x20];
5707
5708 u8 reserved_at_40[0x40];
5709};
5710
5711struct mlx5_ifc_detach_from_mcg_in_bits {
5712 u8 opcode[0x10];
5713 u8 reserved_at_10[0x10];
5714
5715 u8 reserved_at_20[0x10];
5716 u8 op_mod[0x10];
5717
5718 u8 reserved_at_40[0x8];
5719 u8 qpn[0x18];
5720
5721 u8 reserved_at_60[0x20];
5722
5723 u8 multicast_gid[16][0x8];
5724};
5725
5726struct mlx5_ifc_destroy_xrq_out_bits {
5727 u8 status[0x8];
5728 u8 reserved_at_8[0x18];
5729
5730 u8 syndrome[0x20];
5731
5732 u8 reserved_at_40[0x40];
5733};
5734
5735struct mlx5_ifc_destroy_xrq_in_bits {
5736 u8 opcode[0x10];
5737 u8 reserved_at_10[0x10];
5738
5739 u8 reserved_at_20[0x10];
5740 u8 op_mod[0x10];
5741
5742 u8 reserved_at_40[0x8];
5743 u8 xrqn[0x18];
5744
5745 u8 reserved_at_60[0x20];
5746};
5747
5748struct mlx5_ifc_destroy_xrc_srq_out_bits {
5749 u8 status[0x8];
5750 u8 reserved_at_8[0x18];
5751
5752 u8 syndrome[0x20];
5753
5754 u8 reserved_at_40[0x40];
5755};
5756
5757struct mlx5_ifc_destroy_xrc_srq_in_bits {
5758 u8 opcode[0x10];
5759 u8 reserved_at_10[0x10];
5760
5761 u8 reserved_at_20[0x10];
5762 u8 op_mod[0x10];
5763
5764 u8 reserved_at_40[0x8];
5765 u8 xrc_srqn[0x18];
5766
5767 u8 reserved_at_60[0x20];
5768};
5769
5770struct mlx5_ifc_destroy_tis_out_bits {
5771 u8 status[0x8];
5772 u8 reserved_at_8[0x18];
5773
5774 u8 syndrome[0x20];
5775
5776 u8 reserved_at_40[0x40];
5777};
5778
5779struct mlx5_ifc_destroy_tis_in_bits {
5780 u8 opcode[0x10];
5781 u8 reserved_at_10[0x10];
5782
5783 u8 reserved_at_20[0x10];
5784 u8 op_mod[0x10];
5785
5786 u8 reserved_at_40[0x8];
5787 u8 tisn[0x18];
5788
5789 u8 reserved_at_60[0x20];
5790};
5791
5792struct mlx5_ifc_destroy_tir_out_bits {
5793 u8 status[0x8];
5794 u8 reserved_at_8[0x18];
5795
5796 u8 syndrome[0x20];
5797
5798 u8 reserved_at_40[0x40];
5799};
5800
5801struct mlx5_ifc_destroy_tir_in_bits {
5802 u8 opcode[0x10];
5803 u8 reserved_at_10[0x10];
5804
5805 u8 reserved_at_20[0x10];
5806 u8 op_mod[0x10];
5807
5808 u8 reserved_at_40[0x8];
5809 u8 tirn[0x18];
5810
5811 u8 reserved_at_60[0x20];
5812};
5813
5814struct mlx5_ifc_destroy_srq_out_bits {
5815 u8 status[0x8];
5816 u8 reserved_at_8[0x18];
5817
5818 u8 syndrome[0x20];
5819
5820 u8 reserved_at_40[0x40];
5821};
5822
5823struct mlx5_ifc_destroy_srq_in_bits {
5824 u8 opcode[0x10];
5825 u8 reserved_at_10[0x10];
5826
5827 u8 reserved_at_20[0x10];
5828 u8 op_mod[0x10];
5829
5830 u8 reserved_at_40[0x8];
5831 u8 srqn[0x18];
5832
5833 u8 reserved_at_60[0x20];
5834};
5835
5836struct mlx5_ifc_destroy_sq_out_bits {
5837 u8 status[0x8];
5838 u8 reserved_at_8[0x18];
5839
5840 u8 syndrome[0x20];
5841
5842 u8 reserved_at_40[0x40];
5843};
5844
5845struct mlx5_ifc_destroy_sq_in_bits {
5846 u8 opcode[0x10];
5847 u8 reserved_at_10[0x10];
5848
5849 u8 reserved_at_20[0x10];
5850 u8 op_mod[0x10];
5851
5852 u8 reserved_at_40[0x8];
5853 u8 sqn[0x18];
5854
5855 u8 reserved_at_60[0x20];
5856};
5857
5858struct mlx5_ifc_destroy_scheduling_element_out_bits {
5859 u8 status[0x8];
5860 u8 reserved_at_8[0x18];
5861
5862 u8 syndrome[0x20];
5863
5864 u8 reserved_at_40[0x1c0];
5865};
5866
5867struct mlx5_ifc_destroy_scheduling_element_in_bits {
5868 u8 opcode[0x10];
5869 u8 reserved_at_10[0x10];
5870
5871 u8 reserved_at_20[0x10];
5872 u8 op_mod[0x10];
5873
5874 u8 scheduling_hierarchy[0x8];
5875 u8 reserved_at_48[0x18];
5876
5877 u8 scheduling_element_id[0x20];
5878
5879 u8 reserved_at_80[0x180];
5880};
5881
5882struct mlx5_ifc_destroy_rqt_out_bits {
5883 u8 status[0x8];
5884 u8 reserved_at_8[0x18];
5885
5886 u8 syndrome[0x20];
5887
5888 u8 reserved_at_40[0x40];
5889};
5890
5891struct mlx5_ifc_destroy_rqt_in_bits {
5892 u8 opcode[0x10];
5893 u8 reserved_at_10[0x10];
5894
5895 u8 reserved_at_20[0x10];
5896 u8 op_mod[0x10];
5897
5898 u8 reserved_at_40[0x8];
5899 u8 rqtn[0x18];
5900
5901 u8 reserved_at_60[0x20];
5902};
5903
5904struct mlx5_ifc_destroy_rq_out_bits {
5905 u8 status[0x8];
5906 u8 reserved_at_8[0x18];
5907
5908 u8 syndrome[0x20];
5909
5910 u8 reserved_at_40[0x40];
5911};
5912
5913struct mlx5_ifc_destroy_rq_in_bits {
5914 u8 opcode[0x10];
5915 u8 reserved_at_10[0x10];
5916
5917 u8 reserved_at_20[0x10];
5918 u8 op_mod[0x10];
5919
5920 u8 reserved_at_40[0x8];
5921 u8 rqn[0x18];
5922
5923 u8 reserved_at_60[0x20];
5924};
5925
5926struct mlx5_ifc_set_delay_drop_params_in_bits {
5927 u8 opcode[0x10];
5928 u8 reserved_at_10[0x10];
5929
5930 u8 reserved_at_20[0x10];
5931 u8 op_mod[0x10];
5932
5933 u8 reserved_at_40[0x20];
5934
5935 u8 reserved_at_60[0x10];
5936 u8 delay_drop_timeout[0x10];
5937};
5938
5939struct mlx5_ifc_set_delay_drop_params_out_bits {
5940 u8 status[0x8];
5941 u8 reserved_at_8[0x18];
5942
5943 u8 syndrome[0x20];
5944
5945 u8 reserved_at_40[0x40];
5946};
5947
5948struct mlx5_ifc_destroy_rmp_out_bits {
5949 u8 status[0x8];
5950 u8 reserved_at_8[0x18];
5951
5952 u8 syndrome[0x20];
5953
5954 u8 reserved_at_40[0x40];
5955};
5956
5957struct mlx5_ifc_destroy_rmp_in_bits {
5958 u8 opcode[0x10];
5959 u8 reserved_at_10[0x10];
5960
5961 u8 reserved_at_20[0x10];
5962 u8 op_mod[0x10];
5963
5964 u8 reserved_at_40[0x8];
5965 u8 rmpn[0x18];
5966
5967 u8 reserved_at_60[0x20];
5968};
5969
5970struct mlx5_ifc_destroy_qp_out_bits {
5971 u8 status[0x8];
5972 u8 reserved_at_8[0x18];
5973
5974 u8 syndrome[0x20];
5975
5976 u8 reserved_at_40[0x40];
5977};
5978
5979struct mlx5_ifc_destroy_qp_in_bits {
5980 u8 opcode[0x10];
5981 u8 reserved_at_10[0x10];
5982
5983 u8 reserved_at_20[0x10];
5984 u8 op_mod[0x10];
5985
5986 u8 reserved_at_40[0x8];
5987 u8 qpn[0x18];
5988
5989 u8 reserved_at_60[0x20];
5990};
5991
5992struct mlx5_ifc_destroy_psv_out_bits {
5993 u8 status[0x8];
5994 u8 reserved_at_8[0x18];
5995
5996 u8 syndrome[0x20];
5997
5998 u8 reserved_at_40[0x40];
5999};
6000
6001struct mlx5_ifc_destroy_psv_in_bits {
6002 u8 opcode[0x10];
6003 u8 reserved_at_10[0x10];
6004
6005 u8 reserved_at_20[0x10];
6006 u8 op_mod[0x10];
6007
6008 u8 reserved_at_40[0x8];
6009 u8 psvn[0x18];
6010
6011 u8 reserved_at_60[0x20];
6012};
6013
6014struct mlx5_ifc_destroy_mkey_out_bits {
6015 u8 status[0x8];
6016 u8 reserved_at_8[0x18];
6017
6018 u8 syndrome[0x20];
6019
6020 u8 reserved_at_40[0x40];
6021};
6022
6023struct mlx5_ifc_destroy_mkey_in_bits {
6024 u8 opcode[0x10];
6025 u8 reserved_at_10[0x10];
6026
6027 u8 reserved_at_20[0x10];
6028 u8 op_mod[0x10];
6029
6030 u8 reserved_at_40[0x8];
6031 u8 mkey_index[0x18];
6032
6033 u8 reserved_at_60[0x20];
6034};
6035
6036struct mlx5_ifc_destroy_flow_table_out_bits {
6037 u8 status[0x8];
6038 u8 reserved_at_8[0x18];
6039
6040 u8 syndrome[0x20];
6041
6042 u8 reserved_at_40[0x40];
6043};
6044
6045struct mlx5_ifc_destroy_flow_table_in_bits {
6046 u8 opcode[0x10];
6047 u8 reserved_at_10[0x10];
6048
6049 u8 reserved_at_20[0x10];
6050 u8 op_mod[0x10];
6051
6052 u8 other_vport[0x1];
6053 u8 reserved_at_41[0xf];
6054 u8 vport_number[0x10];
6055
6056 u8 reserved_at_60[0x20];
6057
6058 u8 table_type[0x8];
6059 u8 reserved_at_88[0x18];
6060
6061 u8 reserved_at_a0[0x8];
6062 u8 table_id[0x18];
6063
6064 u8 reserved_at_c0[0x140];
6065};
6066
6067struct mlx5_ifc_destroy_flow_group_out_bits {
6068 u8 status[0x8];
6069 u8 reserved_at_8[0x18];
6070
6071 u8 syndrome[0x20];
6072
6073 u8 reserved_at_40[0x40];
6074};
6075
6076struct mlx5_ifc_destroy_flow_group_in_bits {
6077 u8 opcode[0x10];
6078 u8 reserved_at_10[0x10];
6079
6080 u8 reserved_at_20[0x10];
6081 u8 op_mod[0x10];
6082
6083 u8 other_vport[0x1];
6084 u8 reserved_at_41[0xf];
6085 u8 vport_number[0x10];
6086
6087 u8 reserved_at_60[0x20];
6088
6089 u8 table_type[0x8];
6090 u8 reserved_at_88[0x18];
6091
6092 u8 reserved_at_a0[0x8];
6093 u8 table_id[0x18];
6094
6095 u8 group_id[0x20];
6096
6097 u8 reserved_at_e0[0x120];
6098};
6099
6100struct mlx5_ifc_destroy_eq_out_bits {
6101 u8 status[0x8];
6102 u8 reserved_at_8[0x18];
6103
6104 u8 syndrome[0x20];
6105
6106 u8 reserved_at_40[0x40];
6107};
6108
6109struct mlx5_ifc_destroy_eq_in_bits {
6110 u8 opcode[0x10];
6111 u8 reserved_at_10[0x10];
6112
6113 u8 reserved_at_20[0x10];
6114 u8 op_mod[0x10];
6115
6116 u8 reserved_at_40[0x18];
6117 u8 eq_number[0x8];
6118
6119 u8 reserved_at_60[0x20];
6120};
6121
6122struct mlx5_ifc_destroy_dct_out_bits {
6123 u8 status[0x8];
6124 u8 reserved_at_8[0x18];
6125
6126 u8 syndrome[0x20];
6127
6128 u8 reserved_at_40[0x40];
6129};
6130
6131struct mlx5_ifc_destroy_dct_in_bits {
6132 u8 opcode[0x10];
6133 u8 reserved_at_10[0x10];
6134
6135 u8 reserved_at_20[0x10];
6136 u8 op_mod[0x10];
6137
6138 u8 reserved_at_40[0x8];
6139 u8 dctn[0x18];
6140
6141 u8 reserved_at_60[0x20];
6142};
6143
6144struct mlx5_ifc_destroy_cq_out_bits {
6145 u8 status[0x8];
6146 u8 reserved_at_8[0x18];
6147
6148 u8 syndrome[0x20];
6149
6150 u8 reserved_at_40[0x40];
6151};
6152
6153struct mlx5_ifc_destroy_cq_in_bits {
6154 u8 opcode[0x10];
6155 u8 reserved_at_10[0x10];
6156
6157 u8 reserved_at_20[0x10];
6158 u8 op_mod[0x10];
6159
6160 u8 reserved_at_40[0x8];
6161 u8 cqn[0x18];
6162
6163 u8 reserved_at_60[0x20];
6164};
6165
6166struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6167 u8 status[0x8];
6168 u8 reserved_at_8[0x18];
6169
6170 u8 syndrome[0x20];
6171
6172 u8 reserved_at_40[0x40];
6173};
6174
6175struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6176 u8 opcode[0x10];
6177 u8 reserved_at_10[0x10];
6178
6179 u8 reserved_at_20[0x10];
6180 u8 op_mod[0x10];
6181
6182 u8 reserved_at_40[0x20];
6183
6184 u8 reserved_at_60[0x10];
6185 u8 vxlan_udp_port[0x10];
6186};
6187
6188struct mlx5_ifc_delete_l2_table_entry_out_bits {
6189 u8 status[0x8];
6190 u8 reserved_at_8[0x18];
6191
6192 u8 syndrome[0x20];
6193
6194 u8 reserved_at_40[0x40];
6195};
6196
6197struct mlx5_ifc_delete_l2_table_entry_in_bits {
6198 u8 opcode[0x10];
6199 u8 reserved_at_10[0x10];
6200
6201 u8 reserved_at_20[0x10];
6202 u8 op_mod[0x10];
6203
6204 u8 reserved_at_40[0x60];
6205
6206 u8 reserved_at_a0[0x8];
6207 u8 table_index[0x18];
6208
6209 u8 reserved_at_c0[0x140];
6210};
6211
6212struct mlx5_ifc_delete_fte_out_bits {
6213 u8 status[0x8];
6214 u8 reserved_at_8[0x18];
6215
6216 u8 syndrome[0x20];
6217
6218 u8 reserved_at_40[0x40];
6219};
6220
6221struct mlx5_ifc_delete_fte_in_bits {
6222 u8 opcode[0x10];
6223 u8 reserved_at_10[0x10];
6224
6225 u8 reserved_at_20[0x10];
6226 u8 op_mod[0x10];
6227
6228 u8 other_vport[0x1];
6229 u8 reserved_at_41[0xf];
6230 u8 vport_number[0x10];
6231
6232 u8 reserved_at_60[0x20];
6233
6234 u8 table_type[0x8];
6235 u8 reserved_at_88[0x18];
6236
6237 u8 reserved_at_a0[0x8];
6238 u8 table_id[0x18];
6239
6240 u8 reserved_at_c0[0x40];
6241
6242 u8 flow_index[0x20];
6243
6244 u8 reserved_at_120[0xe0];
6245};
6246
6247struct mlx5_ifc_dealloc_xrcd_out_bits {
6248 u8 status[0x8];
6249 u8 reserved_at_8[0x18];
6250
6251 u8 syndrome[0x20];
6252
6253 u8 reserved_at_40[0x40];
6254};
6255
6256struct mlx5_ifc_dealloc_xrcd_in_bits {
6257 u8 opcode[0x10];
6258 u8 reserved_at_10[0x10];
6259
6260 u8 reserved_at_20[0x10];
6261 u8 op_mod[0x10];
6262
6263 u8 reserved_at_40[0x8];
6264 u8 xrcd[0x18];
6265
6266 u8 reserved_at_60[0x20];
6267};
6268
6269struct mlx5_ifc_dealloc_uar_out_bits {
6270 u8 status[0x8];
6271 u8 reserved_at_8[0x18];
6272
6273 u8 syndrome[0x20];
6274
6275 u8 reserved_at_40[0x40];
6276};
6277
6278struct mlx5_ifc_dealloc_uar_in_bits {
6279 u8 opcode[0x10];
6280 u8 reserved_at_10[0x10];
6281
6282 u8 reserved_at_20[0x10];
6283 u8 op_mod[0x10];
6284
6285 u8 reserved_at_40[0x8];
6286 u8 uar[0x18];
6287
6288 u8 reserved_at_60[0x20];
6289};
6290
6291struct mlx5_ifc_dealloc_transport_domain_out_bits {
6292 u8 status[0x8];
6293 u8 reserved_at_8[0x18];
6294
6295 u8 syndrome[0x20];
6296
6297 u8 reserved_at_40[0x40];
6298};
6299
6300struct mlx5_ifc_dealloc_transport_domain_in_bits {
6301 u8 opcode[0x10];
6302 u8 reserved_at_10[0x10];
6303
6304 u8 reserved_at_20[0x10];
6305 u8 op_mod[0x10];
6306
6307 u8 reserved_at_40[0x8];
6308 u8 transport_domain[0x18];
6309
6310 u8 reserved_at_60[0x20];
6311};
6312
6313struct mlx5_ifc_dealloc_q_counter_out_bits {
6314 u8 status[0x8];
6315 u8 reserved_at_8[0x18];
6316
6317 u8 syndrome[0x20];
6318
6319 u8 reserved_at_40[0x40];
6320};
6321
6322struct mlx5_ifc_dealloc_q_counter_in_bits {
6323 u8 opcode[0x10];
6324 u8 reserved_at_10[0x10];
6325
6326 u8 reserved_at_20[0x10];
6327 u8 op_mod[0x10];
6328
6329 u8 reserved_at_40[0x18];
6330 u8 counter_set_id[0x8];
6331
6332 u8 reserved_at_60[0x20];
6333};
6334
6335struct mlx5_ifc_dealloc_pd_out_bits {
6336 u8 status[0x8];
6337 u8 reserved_at_8[0x18];
6338
6339 u8 syndrome[0x20];
6340
6341 u8 reserved_at_40[0x40];
6342};
6343
6344struct mlx5_ifc_dealloc_pd_in_bits {
6345 u8 opcode[0x10];
6346 u8 reserved_at_10[0x10];
6347
6348 u8 reserved_at_20[0x10];
6349 u8 op_mod[0x10];
6350
6351 u8 reserved_at_40[0x8];
6352 u8 pd[0x18];
6353
6354 u8 reserved_at_60[0x20];
6355};
6356
6357struct mlx5_ifc_dealloc_flow_counter_out_bits {
6358 u8 status[0x8];
6359 u8 reserved_at_8[0x18];
6360
6361 u8 syndrome[0x20];
6362
6363 u8 reserved_at_40[0x40];
6364};
6365
6366struct mlx5_ifc_dealloc_flow_counter_in_bits {
6367 u8 opcode[0x10];
6368 u8 reserved_at_10[0x10];
6369
6370 u8 reserved_at_20[0x10];
6371 u8 op_mod[0x10];
6372
6373 u8 flow_counter_id[0x20];
6374
6375 u8 reserved_at_60[0x20];
6376};
6377
6378struct mlx5_ifc_create_xrq_out_bits {
6379 u8 status[0x8];
6380 u8 reserved_at_8[0x18];
6381
6382 u8 syndrome[0x20];
6383
6384 u8 reserved_at_40[0x8];
6385 u8 xrqn[0x18];
6386
6387 u8 reserved_at_60[0x20];
6388};
6389
6390struct mlx5_ifc_create_xrq_in_bits {
6391 u8 opcode[0x10];
6392 u8 reserved_at_10[0x10];
6393
6394 u8 reserved_at_20[0x10];
6395 u8 op_mod[0x10];
6396
6397 u8 reserved_at_40[0x40];
6398
6399 struct mlx5_ifc_xrqc_bits xrq_context;
6400};
6401
6402struct mlx5_ifc_create_xrc_srq_out_bits {
6403 u8 status[0x8];
6404 u8 reserved_at_8[0x18];
6405
6406 u8 syndrome[0x20];
6407
6408 u8 reserved_at_40[0x8];
6409 u8 xrc_srqn[0x18];
6410
6411 u8 reserved_at_60[0x20];
6412};
6413
6414struct mlx5_ifc_create_xrc_srq_in_bits {
6415 u8 opcode[0x10];
6416 u8 reserved_at_10[0x10];
6417
6418 u8 reserved_at_20[0x10];
6419 u8 op_mod[0x10];
6420
6421 u8 reserved_at_40[0x40];
6422
6423 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6424
6425 u8 reserved_at_280[0x600];
6426
6427 u8 pas[0][0x40];
6428};
6429
6430struct mlx5_ifc_create_tis_out_bits {
6431 u8 status[0x8];
6432 u8 reserved_at_8[0x18];
6433
6434 u8 syndrome[0x20];
6435
6436 u8 reserved_at_40[0x8];
6437 u8 tisn[0x18];
6438
6439 u8 reserved_at_60[0x20];
6440};
6441
6442struct mlx5_ifc_create_tis_in_bits {
6443 u8 opcode[0x10];
6444 u8 reserved_at_10[0x10];
6445
6446 u8 reserved_at_20[0x10];
6447 u8 op_mod[0x10];
6448
6449 u8 reserved_at_40[0xc0];
6450
6451 struct mlx5_ifc_tisc_bits ctx;
6452};
6453
6454struct mlx5_ifc_create_tir_out_bits {
6455 u8 status[0x8];
6456 u8 reserved_at_8[0x18];
6457
6458 u8 syndrome[0x20];
6459
6460 u8 reserved_at_40[0x8];
6461 u8 tirn[0x18];
6462
6463 u8 reserved_at_60[0x20];
6464};
6465
6466struct mlx5_ifc_create_tir_in_bits {
6467 u8 opcode[0x10];
6468 u8 reserved_at_10[0x10];
6469
6470 u8 reserved_at_20[0x10];
6471 u8 op_mod[0x10];
6472
6473 u8 reserved_at_40[0xc0];
6474
6475 struct mlx5_ifc_tirc_bits ctx;
6476};
6477
6478struct mlx5_ifc_create_srq_out_bits {
6479 u8 status[0x8];
6480 u8 reserved_at_8[0x18];
6481
6482 u8 syndrome[0x20];
6483
6484 u8 reserved_at_40[0x8];
6485 u8 srqn[0x18];
6486
6487 u8 reserved_at_60[0x20];
6488};
6489
6490struct mlx5_ifc_create_srq_in_bits {
6491 u8 opcode[0x10];
6492 u8 reserved_at_10[0x10];
6493
6494 u8 reserved_at_20[0x10];
6495 u8 op_mod[0x10];
6496
6497 u8 reserved_at_40[0x40];
6498
6499 struct mlx5_ifc_srqc_bits srq_context_entry;
6500
6501 u8 reserved_at_280[0x600];
6502
6503 u8 pas[0][0x40];
6504};
6505
6506struct mlx5_ifc_create_sq_out_bits {
6507 u8 status[0x8];
6508 u8 reserved_at_8[0x18];
6509
6510 u8 syndrome[0x20];
6511
6512 u8 reserved_at_40[0x8];
6513 u8 sqn[0x18];
6514
6515 u8 reserved_at_60[0x20];
6516};
6517
6518struct mlx5_ifc_create_sq_in_bits {
6519 u8 opcode[0x10];
6520 u8 reserved_at_10[0x10];
6521
6522 u8 reserved_at_20[0x10];
6523 u8 op_mod[0x10];
6524
6525 u8 reserved_at_40[0xc0];
6526
6527 struct mlx5_ifc_sqc_bits ctx;
6528};
6529
6530struct mlx5_ifc_create_scheduling_element_out_bits {
6531 u8 status[0x8];
6532 u8 reserved_at_8[0x18];
6533
6534 u8 syndrome[0x20];
6535
6536 u8 reserved_at_40[0x40];
6537
6538 u8 scheduling_element_id[0x20];
6539
6540 u8 reserved_at_a0[0x160];
6541};
6542
6543struct mlx5_ifc_create_scheduling_element_in_bits {
6544 u8 opcode[0x10];
6545 u8 reserved_at_10[0x10];
6546
6547 u8 reserved_at_20[0x10];
6548 u8 op_mod[0x10];
6549
6550 u8 scheduling_hierarchy[0x8];
6551 u8 reserved_at_48[0x18];
6552
6553 u8 reserved_at_60[0xa0];
6554
6555 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6556
6557 u8 reserved_at_300[0x100];
6558};
6559
6560struct mlx5_ifc_create_rqt_out_bits {
6561 u8 status[0x8];
6562 u8 reserved_at_8[0x18];
6563
6564 u8 syndrome[0x20];
6565
6566 u8 reserved_at_40[0x8];
6567 u8 rqtn[0x18];
6568
6569 u8 reserved_at_60[0x20];
6570};
6571
6572struct mlx5_ifc_create_rqt_in_bits {
6573 u8 opcode[0x10];
6574 u8 reserved_at_10[0x10];
6575
6576 u8 reserved_at_20[0x10];
6577 u8 op_mod[0x10];
6578
6579 u8 reserved_at_40[0xc0];
6580
6581 struct mlx5_ifc_rqtc_bits rqt_context;
6582};
6583
6584struct mlx5_ifc_create_rq_out_bits {
6585 u8 status[0x8];
6586 u8 reserved_at_8[0x18];
6587
6588 u8 syndrome[0x20];
6589
6590 u8 reserved_at_40[0x8];
6591 u8 rqn[0x18];
6592
6593 u8 reserved_at_60[0x20];
6594};
6595
6596struct mlx5_ifc_create_rq_in_bits {
6597 u8 opcode[0x10];
6598 u8 reserved_at_10[0x10];
6599
6600 u8 reserved_at_20[0x10];
6601 u8 op_mod[0x10];
6602
6603 u8 reserved_at_40[0xc0];
6604
6605 struct mlx5_ifc_rqc_bits ctx;
6606};
6607
6608struct mlx5_ifc_create_rmp_out_bits {
6609 u8 status[0x8];
6610 u8 reserved_at_8[0x18];
6611
6612 u8 syndrome[0x20];
6613
6614 u8 reserved_at_40[0x8];
6615 u8 rmpn[0x18];
6616
6617 u8 reserved_at_60[0x20];
6618};
6619
6620struct mlx5_ifc_create_rmp_in_bits {
6621 u8 opcode[0x10];
6622 u8 reserved_at_10[0x10];
6623
6624 u8 reserved_at_20[0x10];
6625 u8 op_mod[0x10];
6626
6627 u8 reserved_at_40[0xc0];
6628
6629 struct mlx5_ifc_rmpc_bits ctx;
6630};
6631
6632struct mlx5_ifc_create_qp_out_bits {
6633 u8 status[0x8];
6634 u8 reserved_at_8[0x18];
6635
6636 u8 syndrome[0x20];
6637
6638 u8 reserved_at_40[0x8];
6639 u8 qpn[0x18];
6640
6641 u8 reserved_at_60[0x20];
6642};
6643
6644struct mlx5_ifc_create_qp_in_bits {
6645 u8 opcode[0x10];
6646 u8 reserved_at_10[0x10];
6647
6648 u8 reserved_at_20[0x10];
6649 u8 op_mod[0x10];
6650
6651 u8 reserved_at_40[0x40];
6652
6653 u8 opt_param_mask[0x20];
6654
6655 u8 reserved_at_a0[0x20];
6656
6657 struct mlx5_ifc_qpc_bits qpc;
6658
6659 u8 reserved_at_800[0x80];
6660
6661 u8 pas[0][0x40];
6662};
6663
6664struct mlx5_ifc_create_psv_out_bits {
6665 u8 status[0x8];
6666 u8 reserved_at_8[0x18];
6667
6668 u8 syndrome[0x20];
6669
6670 u8 reserved_at_40[0x40];
6671
6672 u8 reserved_at_80[0x8];
6673 u8 psv0_index[0x18];
6674
6675 u8 reserved_at_a0[0x8];
6676 u8 psv1_index[0x18];
6677
6678 u8 reserved_at_c0[0x8];
6679 u8 psv2_index[0x18];
6680
6681 u8 reserved_at_e0[0x8];
6682 u8 psv3_index[0x18];
6683};
6684
6685struct mlx5_ifc_create_psv_in_bits {
6686 u8 opcode[0x10];
6687 u8 reserved_at_10[0x10];
6688
6689 u8 reserved_at_20[0x10];
6690 u8 op_mod[0x10];
6691
6692 u8 num_psv[0x4];
6693 u8 reserved_at_44[0x4];
6694 u8 pd[0x18];
6695
6696 u8 reserved_at_60[0x20];
6697};
6698
6699struct mlx5_ifc_create_mkey_out_bits {
6700 u8 status[0x8];
6701 u8 reserved_at_8[0x18];
6702
6703 u8 syndrome[0x20];
6704
6705 u8 reserved_at_40[0x8];
6706 u8 mkey_index[0x18];
6707
6708 u8 reserved_at_60[0x20];
6709};
6710
6711struct mlx5_ifc_create_mkey_in_bits {
6712 u8 opcode[0x10];
6713 u8 reserved_at_10[0x10];
6714
6715 u8 reserved_at_20[0x10];
6716 u8 op_mod[0x10];
6717
6718 u8 reserved_at_40[0x20];
6719
6720 u8 pg_access[0x1];
6721 u8 reserved_at_61[0x1f];
6722
6723 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6724
6725 u8 reserved_at_280[0x80];
6726
6727 u8 translations_octword_actual_size[0x20];
6728
6729 u8 reserved_at_320[0x560];
6730
6731 u8 klm_pas_mtt[0][0x20];
6732};
6733
6734struct mlx5_ifc_create_flow_table_out_bits {
6735 u8 status[0x8];
6736 u8 reserved_at_8[0x18];
6737
6738 u8 syndrome[0x20];
6739
6740 u8 reserved_at_40[0x8];
6741 u8 table_id[0x18];
6742
6743 u8 reserved_at_60[0x20];
6744};
6745
6746struct mlx5_ifc_flow_table_context_bits {
6747 u8 encap_en[0x1];
6748 u8 decap_en[0x1];
6749 u8 reserved_at_2[0x2];
6750 u8 table_miss_action[0x4];
6751 u8 level[0x8];
6752 u8 reserved_at_10[0x8];
6753 u8 log_size[0x8];
6754
6755 u8 reserved_at_20[0x8];
6756 u8 table_miss_id[0x18];
6757
6758 u8 reserved_at_40[0x8];
6759 u8 lag_master_next_table_id[0x18];
6760
6761 u8 reserved_at_60[0xe0];
6762};
6763
6764struct mlx5_ifc_create_flow_table_in_bits {
6765 u8 opcode[0x10];
6766 u8 reserved_at_10[0x10];
6767
6768 u8 reserved_at_20[0x10];
6769 u8 op_mod[0x10];
6770
6771 u8 other_vport[0x1];
6772 u8 reserved_at_41[0xf];
6773 u8 vport_number[0x10];
6774
6775 u8 reserved_at_60[0x20];
6776
6777 u8 table_type[0x8];
6778 u8 reserved_at_88[0x18];
6779
6780 u8 reserved_at_a0[0x20];
6781
6782 struct mlx5_ifc_flow_table_context_bits flow_table_context;
6783};
6784
6785struct mlx5_ifc_create_flow_group_out_bits {
6786 u8 status[0x8];
6787 u8 reserved_at_8[0x18];
6788
6789 u8 syndrome[0x20];
6790
6791 u8 reserved_at_40[0x8];
6792 u8 group_id[0x18];
6793
6794 u8 reserved_at_60[0x20];
6795};
6796
6797enum {
6798 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6799 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6800 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6801};
6802
6803struct mlx5_ifc_create_flow_group_in_bits {
6804 u8 opcode[0x10];
6805 u8 reserved_at_10[0x10];
6806
6807 u8 reserved_at_20[0x10];
6808 u8 op_mod[0x10];
6809
6810 u8 other_vport[0x1];
6811 u8 reserved_at_41[0xf];
6812 u8 vport_number[0x10];
6813
6814 u8 reserved_at_60[0x20];
6815
6816 u8 table_type[0x8];
6817 u8 reserved_at_88[0x18];
6818
6819 u8 reserved_at_a0[0x8];
6820 u8 table_id[0x18];
6821
6822 u8 reserved_at_c0[0x20];
6823
6824 u8 start_flow_index[0x20];
6825
6826 u8 reserved_at_100[0x20];
6827
6828 u8 end_flow_index[0x20];
6829
6830 u8 reserved_at_140[0xa0];
6831
6832 u8 reserved_at_1e0[0x18];
6833 u8 match_criteria_enable[0x8];
6834
6835 struct mlx5_ifc_fte_match_param_bits match_criteria;
6836
6837 u8 reserved_at_1200[0xe00];
6838};
6839
6840struct mlx5_ifc_create_eq_out_bits {
6841 u8 status[0x8];
6842 u8 reserved_at_8[0x18];
6843
6844 u8 syndrome[0x20];
6845
6846 u8 reserved_at_40[0x18];
6847 u8 eq_number[0x8];
6848
6849 u8 reserved_at_60[0x20];
6850};
6851
6852struct mlx5_ifc_create_eq_in_bits {
6853 u8 opcode[0x10];
6854 u8 reserved_at_10[0x10];
6855
6856 u8 reserved_at_20[0x10];
6857 u8 op_mod[0x10];
6858
6859 u8 reserved_at_40[0x40];
6860
6861 struct mlx5_ifc_eqc_bits eq_context_entry;
6862
6863 u8 reserved_at_280[0x40];
6864
6865 u8 event_bitmask[0x40];
6866
6867 u8 reserved_at_300[0x580];
6868
6869 u8 pas[0][0x40];
6870};
6871
6872struct mlx5_ifc_create_dct_out_bits {
6873 u8 status[0x8];
6874 u8 reserved_at_8[0x18];
6875
6876 u8 syndrome[0x20];
6877
6878 u8 reserved_at_40[0x8];
6879 u8 dctn[0x18];
6880
6881 u8 reserved_at_60[0x20];
6882};
6883
6884struct mlx5_ifc_create_dct_in_bits {
6885 u8 opcode[0x10];
6886 u8 reserved_at_10[0x10];
6887
6888 u8 reserved_at_20[0x10];
6889 u8 op_mod[0x10];
6890
6891 u8 reserved_at_40[0x40];
6892
6893 struct mlx5_ifc_dctc_bits dct_context_entry;
6894
6895 u8 reserved_at_280[0x180];
6896};
6897
6898struct mlx5_ifc_create_cq_out_bits {
6899 u8 status[0x8];
6900 u8 reserved_at_8[0x18];
6901
6902 u8 syndrome[0x20];
6903
6904 u8 reserved_at_40[0x8];
6905 u8 cqn[0x18];
6906
6907 u8 reserved_at_60[0x20];
6908};
6909
6910struct mlx5_ifc_create_cq_in_bits {
6911 u8 opcode[0x10];
6912 u8 reserved_at_10[0x10];
6913
6914 u8 reserved_at_20[0x10];
6915 u8 op_mod[0x10];
6916
6917 u8 reserved_at_40[0x40];
6918
6919 struct mlx5_ifc_cqc_bits cq_context;
6920
6921 u8 reserved_at_280[0x600];
6922
6923 u8 pas[0][0x40];
6924};
6925
6926struct mlx5_ifc_config_int_moderation_out_bits {
6927 u8 status[0x8];
6928 u8 reserved_at_8[0x18];
6929
6930 u8 syndrome[0x20];
6931
6932 u8 reserved_at_40[0x4];
6933 u8 min_delay[0xc];
6934 u8 int_vector[0x10];
6935
6936 u8 reserved_at_60[0x20];
6937};
6938
6939enum {
6940 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6941 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6942};
6943
6944struct mlx5_ifc_config_int_moderation_in_bits {
6945 u8 opcode[0x10];
6946 u8 reserved_at_10[0x10];
6947
6948 u8 reserved_at_20[0x10];
6949 u8 op_mod[0x10];
6950
6951 u8 reserved_at_40[0x4];
6952 u8 min_delay[0xc];
6953 u8 int_vector[0x10];
6954
6955 u8 reserved_at_60[0x20];
6956};
6957
6958struct mlx5_ifc_attach_to_mcg_out_bits {
6959 u8 status[0x8];
6960 u8 reserved_at_8[0x18];
6961
6962 u8 syndrome[0x20];
6963
6964 u8 reserved_at_40[0x40];
6965};
6966
6967struct mlx5_ifc_attach_to_mcg_in_bits {
6968 u8 opcode[0x10];
6969 u8 reserved_at_10[0x10];
6970
6971 u8 reserved_at_20[0x10];
6972 u8 op_mod[0x10];
6973
6974 u8 reserved_at_40[0x8];
6975 u8 qpn[0x18];
6976
6977 u8 reserved_at_60[0x20];
6978
6979 u8 multicast_gid[16][0x8];
6980};
6981
6982struct mlx5_ifc_arm_xrq_out_bits {
6983 u8 status[0x8];
6984 u8 reserved_at_8[0x18];
6985
6986 u8 syndrome[0x20];
6987
6988 u8 reserved_at_40[0x40];
6989};
6990
6991struct mlx5_ifc_arm_xrq_in_bits {
6992 u8 opcode[0x10];
6993 u8 reserved_at_10[0x10];
6994
6995 u8 reserved_at_20[0x10];
6996 u8 op_mod[0x10];
6997
6998 u8 reserved_at_40[0x8];
6999 u8 xrqn[0x18];
7000
7001 u8 reserved_at_60[0x10];
7002 u8 lwm[0x10];
7003};
7004
7005struct mlx5_ifc_arm_xrc_srq_out_bits {
7006 u8 status[0x8];
7007 u8 reserved_at_8[0x18];
7008
7009 u8 syndrome[0x20];
7010
7011 u8 reserved_at_40[0x40];
7012};
7013
7014enum {
7015 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7016};
7017
7018struct mlx5_ifc_arm_xrc_srq_in_bits {
7019 u8 opcode[0x10];
7020 u8 reserved_at_10[0x10];
7021
7022 u8 reserved_at_20[0x10];
7023 u8 op_mod[0x10];
7024
7025 u8 reserved_at_40[0x8];
7026 u8 xrc_srqn[0x18];
7027
7028 u8 reserved_at_60[0x10];
7029 u8 lwm[0x10];
7030};
7031
7032struct mlx5_ifc_arm_rq_out_bits {
7033 u8 status[0x8];
7034 u8 reserved_at_8[0x18];
7035
7036 u8 syndrome[0x20];
7037
7038 u8 reserved_at_40[0x40];
7039};
7040
7041enum {
7042 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7043 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7044};
7045
7046struct mlx5_ifc_arm_rq_in_bits {
7047 u8 opcode[0x10];
7048 u8 reserved_at_10[0x10];
7049
7050 u8 reserved_at_20[0x10];
7051 u8 op_mod[0x10];
7052
7053 u8 reserved_at_40[0x8];
7054 u8 srq_number[0x18];
7055
7056 u8 reserved_at_60[0x10];
7057 u8 lwm[0x10];
7058};
7059
7060struct mlx5_ifc_arm_dct_out_bits {
7061 u8 status[0x8];
7062 u8 reserved_at_8[0x18];
7063
7064 u8 syndrome[0x20];
7065
7066 u8 reserved_at_40[0x40];
7067};
7068
7069struct mlx5_ifc_arm_dct_in_bits {
7070 u8 opcode[0x10];
7071 u8 reserved_at_10[0x10];
7072
7073 u8 reserved_at_20[0x10];
7074 u8 op_mod[0x10];
7075
7076 u8 reserved_at_40[0x8];
7077 u8 dct_number[0x18];
7078
7079 u8 reserved_at_60[0x20];
7080};
7081
7082struct mlx5_ifc_alloc_xrcd_out_bits {
7083 u8 status[0x8];
7084 u8 reserved_at_8[0x18];
7085
7086 u8 syndrome[0x20];
7087
7088 u8 reserved_at_40[0x8];
7089 u8 xrcd[0x18];
7090
7091 u8 reserved_at_60[0x20];
7092};
7093
7094struct mlx5_ifc_alloc_xrcd_in_bits {
7095 u8 opcode[0x10];
7096 u8 reserved_at_10[0x10];
7097
7098 u8 reserved_at_20[0x10];
7099 u8 op_mod[0x10];
7100
7101 u8 reserved_at_40[0x40];
7102};
7103
7104struct mlx5_ifc_alloc_uar_out_bits {
7105 u8 status[0x8];
7106 u8 reserved_at_8[0x18];
7107
7108 u8 syndrome[0x20];
7109
7110 u8 reserved_at_40[0x8];
7111 u8 uar[0x18];
7112
7113 u8 reserved_at_60[0x20];
7114};
7115
7116struct mlx5_ifc_alloc_uar_in_bits {
7117 u8 opcode[0x10];
7118 u8 reserved_at_10[0x10];
7119
7120 u8 reserved_at_20[0x10];
7121 u8 op_mod[0x10];
7122
7123 u8 reserved_at_40[0x40];
7124};
7125
7126struct mlx5_ifc_alloc_transport_domain_out_bits {
7127 u8 status[0x8];
7128 u8 reserved_at_8[0x18];
7129
7130 u8 syndrome[0x20];
7131
7132 u8 reserved_at_40[0x8];
7133 u8 transport_domain[0x18];
7134
7135 u8 reserved_at_60[0x20];
7136};
7137
7138struct mlx5_ifc_alloc_transport_domain_in_bits {
7139 u8 opcode[0x10];
7140 u8 reserved_at_10[0x10];
7141
7142 u8 reserved_at_20[0x10];
7143 u8 op_mod[0x10];
7144
7145 u8 reserved_at_40[0x40];
7146};
7147
7148struct mlx5_ifc_alloc_q_counter_out_bits {
7149 u8 status[0x8];
7150 u8 reserved_at_8[0x18];
7151
7152 u8 syndrome[0x20];
7153
7154 u8 reserved_at_40[0x18];
7155 u8 counter_set_id[0x8];
7156
7157 u8 reserved_at_60[0x20];
7158};
7159
7160struct mlx5_ifc_alloc_q_counter_in_bits {
7161 u8 opcode[0x10];
7162 u8 reserved_at_10[0x10];
7163
7164 u8 reserved_at_20[0x10];
7165 u8 op_mod[0x10];
7166
7167 u8 reserved_at_40[0x40];
7168};
7169
7170struct mlx5_ifc_alloc_pd_out_bits {
7171 u8 status[0x8];
7172 u8 reserved_at_8[0x18];
7173
7174 u8 syndrome[0x20];
7175
7176 u8 reserved_at_40[0x8];
7177 u8 pd[0x18];
7178
7179 u8 reserved_at_60[0x20];
7180};
7181
7182struct mlx5_ifc_alloc_pd_in_bits {
7183 u8 opcode[0x10];
7184 u8 reserved_at_10[0x10];
7185
7186 u8 reserved_at_20[0x10];
7187 u8 op_mod[0x10];
7188
7189 u8 reserved_at_40[0x40];
7190};
7191
7192struct mlx5_ifc_alloc_flow_counter_out_bits {
7193 u8 status[0x8];
7194 u8 reserved_at_8[0x18];
7195
7196 u8 syndrome[0x20];
7197
7198 u8 flow_counter_id[0x20];
7199
7200 u8 reserved_at_60[0x20];
7201};
7202
7203struct mlx5_ifc_alloc_flow_counter_in_bits {
7204 u8 opcode[0x10];
7205 u8 reserved_at_10[0x10];
7206
7207 u8 reserved_at_20[0x10];
7208 u8 op_mod[0x10];
7209
7210 u8 reserved_at_40[0x40];
7211};
7212
7213struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7214 u8 status[0x8];
7215 u8 reserved_at_8[0x18];
7216
7217 u8 syndrome[0x20];
7218
7219 u8 reserved_at_40[0x40];
7220};
7221
7222struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7223 u8 opcode[0x10];
7224 u8 reserved_at_10[0x10];
7225
7226 u8 reserved_at_20[0x10];
7227 u8 op_mod[0x10];
7228
7229 u8 reserved_at_40[0x20];
7230
7231 u8 reserved_at_60[0x10];
7232 u8 vxlan_udp_port[0x10];
7233};
7234
7235struct mlx5_ifc_set_rate_limit_out_bits {
7236 u8 status[0x8];
7237 u8 reserved_at_8[0x18];
7238
7239 u8 syndrome[0x20];
7240
7241 u8 reserved_at_40[0x40];
7242};
7243
7244struct mlx5_ifc_set_rate_limit_in_bits {
7245 u8 opcode[0x10];
7246 u8 reserved_at_10[0x10];
7247
7248 u8 reserved_at_20[0x10];
7249 u8 op_mod[0x10];
7250
7251 u8 reserved_at_40[0x10];
7252 u8 rate_limit_index[0x10];
7253
7254 u8 reserved_at_60[0x20];
7255
7256 u8 rate_limit[0x20];
7257};
7258
7259struct mlx5_ifc_access_register_out_bits {
7260 u8 status[0x8];
7261 u8 reserved_at_8[0x18];
7262
7263 u8 syndrome[0x20];
7264
7265 u8 reserved_at_40[0x40];
7266
7267 u8 register_data[0][0x20];
7268};
7269
7270enum {
7271 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7272 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7273};
7274
7275struct mlx5_ifc_access_register_in_bits {
7276 u8 opcode[0x10];
7277 u8 reserved_at_10[0x10];
7278
7279 u8 reserved_at_20[0x10];
7280 u8 op_mod[0x10];
7281
7282 u8 reserved_at_40[0x10];
7283 u8 register_id[0x10];
7284
7285 u8 argument[0x20];
7286
7287 u8 register_data[0][0x20];
7288};
7289
7290struct mlx5_ifc_sltp_reg_bits {
7291 u8 status[0x4];
7292 u8 version[0x4];
7293 u8 local_port[0x8];
7294 u8 pnat[0x2];
7295 u8 reserved_at_12[0x2];
7296 u8 lane[0x4];
7297 u8 reserved_at_18[0x8];
7298
7299 u8 reserved_at_20[0x20];
7300
7301 u8 reserved_at_40[0x7];
7302 u8 polarity[0x1];
7303 u8 ob_tap0[0x8];
7304 u8 ob_tap1[0x8];
7305 u8 ob_tap2[0x8];
7306
7307 u8 reserved_at_60[0xc];
7308 u8 ob_preemp_mode[0x4];
7309 u8 ob_reg[0x8];
7310 u8 ob_bias[0x8];
7311
7312 u8 reserved_at_80[0x20];
7313};
7314
7315struct mlx5_ifc_slrg_reg_bits {
7316 u8 status[0x4];
7317 u8 version[0x4];
7318 u8 local_port[0x8];
7319 u8 pnat[0x2];
7320 u8 reserved_at_12[0x2];
7321 u8 lane[0x4];
7322 u8 reserved_at_18[0x8];
7323
7324 u8 time_to_link_up[0x10];
7325 u8 reserved_at_30[0xc];
7326 u8 grade_lane_speed[0x4];
7327
7328 u8 grade_version[0x8];
7329 u8 grade[0x18];
7330
7331 u8 reserved_at_60[0x4];
7332 u8 height_grade_type[0x4];
7333 u8 height_grade[0x18];
7334
7335 u8 height_dz[0x10];
7336 u8 height_dv[0x10];
7337
7338 u8 reserved_at_a0[0x10];
7339 u8 height_sigma[0x10];
7340
7341 u8 reserved_at_c0[0x20];
7342
7343 u8 reserved_at_e0[0x4];
7344 u8 phase_grade_type[0x4];
7345 u8 phase_grade[0x18];
7346
7347 u8 reserved_at_100[0x8];
7348 u8 phase_eo_pos[0x8];
7349 u8 reserved_at_110[0x8];
7350 u8 phase_eo_neg[0x8];
7351
7352 u8 ffe_set_tested[0x10];
7353 u8 test_errors_per_lane[0x10];
7354};
7355
7356struct mlx5_ifc_pvlc_reg_bits {
7357 u8 reserved_at_0[0x8];
7358 u8 local_port[0x8];
7359 u8 reserved_at_10[0x10];
7360
7361 u8 reserved_at_20[0x1c];
7362 u8 vl_hw_cap[0x4];
7363
7364 u8 reserved_at_40[0x1c];
7365 u8 vl_admin[0x4];
7366
7367 u8 reserved_at_60[0x1c];
7368 u8 vl_operational[0x4];
7369};
7370
7371struct mlx5_ifc_pude_reg_bits {
7372 u8 swid[0x8];
7373 u8 local_port[0x8];
7374 u8 reserved_at_10[0x4];
7375 u8 admin_status[0x4];
7376 u8 reserved_at_18[0x4];
7377 u8 oper_status[0x4];
7378
7379 u8 reserved_at_20[0x60];
7380};
7381
7382struct mlx5_ifc_ptys_reg_bits {
7383 u8 reserved_at_0[0x1];
7384 u8 an_disable_admin[0x1];
7385 u8 an_disable_cap[0x1];
7386 u8 reserved_at_3[0x5];
7387 u8 local_port[0x8];
7388 u8 reserved_at_10[0xd];
7389 u8 proto_mask[0x3];
7390
7391 u8 an_status[0x4];
7392 u8 reserved_at_24[0x3c];
7393
7394 u8 eth_proto_capability[0x20];
7395
7396 u8 ib_link_width_capability[0x10];
7397 u8 ib_proto_capability[0x10];
7398
7399 u8 reserved_at_a0[0x20];
7400
7401 u8 eth_proto_admin[0x20];
7402
7403 u8 ib_link_width_admin[0x10];
7404 u8 ib_proto_admin[0x10];
7405
7406 u8 reserved_at_100[0x20];
7407
7408 u8 eth_proto_oper[0x20];
7409
7410 u8 ib_link_width_oper[0x10];
7411 u8 ib_proto_oper[0x10];
7412
7413 u8 reserved_at_160[0x1c];
7414 u8 connector_type[0x4];
7415
7416 u8 eth_proto_lp_advertise[0x20];
7417
7418 u8 reserved_at_1a0[0x60];
7419};
7420
7421struct mlx5_ifc_mlcr_reg_bits {
7422 u8 reserved_at_0[0x8];
7423 u8 local_port[0x8];
7424 u8 reserved_at_10[0x20];
7425
7426 u8 beacon_duration[0x10];
7427 u8 reserved_at_40[0x10];
7428
7429 u8 beacon_remain[0x10];
7430};
7431
7432struct mlx5_ifc_ptas_reg_bits {
7433 u8 reserved_at_0[0x20];
7434
7435 u8 algorithm_options[0x10];
7436 u8 reserved_at_30[0x4];
7437 u8 repetitions_mode[0x4];
7438 u8 num_of_repetitions[0x8];
7439
7440 u8 grade_version[0x8];
7441 u8 height_grade_type[0x4];
7442 u8 phase_grade_type[0x4];
7443 u8 height_grade_weight[0x8];
7444 u8 phase_grade_weight[0x8];
7445
7446 u8 gisim_measure_bits[0x10];
7447 u8 adaptive_tap_measure_bits[0x10];
7448
7449 u8 ber_bath_high_error_threshold[0x10];
7450 u8 ber_bath_mid_error_threshold[0x10];
7451
7452 u8 ber_bath_low_error_threshold[0x10];
7453 u8 one_ratio_high_threshold[0x10];
7454
7455 u8 one_ratio_high_mid_threshold[0x10];
7456 u8 one_ratio_low_mid_threshold[0x10];
7457
7458 u8 one_ratio_low_threshold[0x10];
7459 u8 ndeo_error_threshold[0x10];
7460
7461 u8 mixer_offset_step_size[0x10];
7462 u8 reserved_at_110[0x8];
7463 u8 mix90_phase_for_voltage_bath[0x8];
7464
7465 u8 mixer_offset_start[0x10];
7466 u8 mixer_offset_end[0x10];
7467
7468 u8 reserved_at_140[0x15];
7469 u8 ber_test_time[0xb];
7470};
7471
7472struct mlx5_ifc_pspa_reg_bits {
7473 u8 swid[0x8];
7474 u8 local_port[0x8];
7475 u8 sub_port[0x8];
7476 u8 reserved_at_18[0x8];
7477
7478 u8 reserved_at_20[0x20];
7479};
7480
7481struct mlx5_ifc_pqdr_reg_bits {
7482 u8 reserved_at_0[0x8];
7483 u8 local_port[0x8];
7484 u8 reserved_at_10[0x5];
7485 u8 prio[0x3];
7486 u8 reserved_at_18[0x6];
7487 u8 mode[0x2];
7488
7489 u8 reserved_at_20[0x20];
7490
7491 u8 reserved_at_40[0x10];
7492 u8 min_threshold[0x10];
7493
7494 u8 reserved_at_60[0x10];
7495 u8 max_threshold[0x10];
7496
7497 u8 reserved_at_80[0x10];
7498 u8 mark_probability_denominator[0x10];
7499
7500 u8 reserved_at_a0[0x60];
7501};
7502
7503struct mlx5_ifc_ppsc_reg_bits {
7504 u8 reserved_at_0[0x8];
7505 u8 local_port[0x8];
7506 u8 reserved_at_10[0x10];
7507
7508 u8 reserved_at_20[0x60];
7509
7510 u8 reserved_at_80[0x1c];
7511 u8 wrps_admin[0x4];
7512
7513 u8 reserved_at_a0[0x1c];
7514 u8 wrps_status[0x4];
7515
7516 u8 reserved_at_c0[0x8];
7517 u8 up_threshold[0x8];
7518 u8 reserved_at_d0[0x8];
7519 u8 down_threshold[0x8];
7520
7521 u8 reserved_at_e0[0x20];
7522
7523 u8 reserved_at_100[0x1c];
7524 u8 srps_admin[0x4];
7525
7526 u8 reserved_at_120[0x1c];
7527 u8 srps_status[0x4];
7528
7529 u8 reserved_at_140[0x40];
7530};
7531
7532struct mlx5_ifc_pplr_reg_bits {
7533 u8 reserved_at_0[0x8];
7534 u8 local_port[0x8];
7535 u8 reserved_at_10[0x10];
7536
7537 u8 reserved_at_20[0x8];
7538 u8 lb_cap[0x8];
7539 u8 reserved_at_30[0x8];
7540 u8 lb_en[0x8];
7541};
7542
7543struct mlx5_ifc_pplm_reg_bits {
7544 u8 reserved_at_0[0x8];
7545 u8 local_port[0x8];
7546 u8 reserved_at_10[0x10];
7547
7548 u8 reserved_at_20[0x20];
7549
7550 u8 port_profile_mode[0x8];
7551 u8 static_port_profile[0x8];
7552 u8 active_port_profile[0x8];
7553 u8 reserved_at_58[0x8];
7554
7555 u8 retransmission_active[0x8];
7556 u8 fec_mode_active[0x18];
7557
7558 u8 reserved_at_80[0x20];
7559};
7560
7561struct mlx5_ifc_ppcnt_reg_bits {
7562 u8 swid[0x8];
7563 u8 local_port[0x8];
7564 u8 pnat[0x2];
7565 u8 reserved_at_12[0x8];
7566 u8 grp[0x6];
7567
7568 u8 clr[0x1];
7569 u8 reserved_at_21[0x1c];
7570 u8 prio_tc[0x3];
7571
7572 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7573};
7574
7575struct mlx5_ifc_mpcnt_reg_bits {
7576 u8 reserved_at_0[0x8];
7577 u8 pcie_index[0x8];
7578 u8 reserved_at_10[0xa];
7579 u8 grp[0x6];
7580
7581 u8 clr[0x1];
7582 u8 reserved_at_21[0x1f];
7583
7584 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7585};
7586
7587struct mlx5_ifc_ppad_reg_bits {
7588 u8 reserved_at_0[0x3];
7589 u8 single_mac[0x1];
7590 u8 reserved_at_4[0x4];
7591 u8 local_port[0x8];
7592 u8 mac_47_32[0x10];
7593
7594 u8 mac_31_0[0x20];
7595
7596 u8 reserved_at_40[0x40];
7597};
7598
7599struct mlx5_ifc_pmtu_reg_bits {
7600 u8 reserved_at_0[0x8];
7601 u8 local_port[0x8];
7602 u8 reserved_at_10[0x10];
7603
7604 u8 max_mtu[0x10];
7605 u8 reserved_at_30[0x10];
7606
7607 u8 admin_mtu[0x10];
7608 u8 reserved_at_50[0x10];
7609
7610 u8 oper_mtu[0x10];
7611 u8 reserved_at_70[0x10];
7612};
7613
7614struct mlx5_ifc_pmpr_reg_bits {
7615 u8 reserved_at_0[0x8];
7616 u8 module[0x8];
7617 u8 reserved_at_10[0x10];
7618
7619 u8 reserved_at_20[0x18];
7620 u8 attenuation_5g[0x8];
7621
7622 u8 reserved_at_40[0x18];
7623 u8 attenuation_7g[0x8];
7624
7625 u8 reserved_at_60[0x18];
7626 u8 attenuation_12g[0x8];
7627};
7628
7629struct mlx5_ifc_pmpe_reg_bits {
7630 u8 reserved_at_0[0x8];
7631 u8 module[0x8];
7632 u8 reserved_at_10[0xc];
7633 u8 module_status[0x4];
7634
7635 u8 reserved_at_20[0x60];
7636};
7637
7638struct mlx5_ifc_pmpc_reg_bits {
7639 u8 module_state_updated[32][0x8];
7640};
7641
7642struct mlx5_ifc_pmlpn_reg_bits {
7643 u8 reserved_at_0[0x4];
7644 u8 mlpn_status[0x4];
7645 u8 local_port[0x8];
7646 u8 reserved_at_10[0x10];
7647
7648 u8 e[0x1];
7649 u8 reserved_at_21[0x1f];
7650};
7651
7652struct mlx5_ifc_pmlp_reg_bits {
7653 u8 rxtx[0x1];
7654 u8 reserved_at_1[0x7];
7655 u8 local_port[0x8];
7656 u8 reserved_at_10[0x8];
7657 u8 width[0x8];
7658
7659 u8 lane0_module_mapping[0x20];
7660
7661 u8 lane1_module_mapping[0x20];
7662
7663 u8 lane2_module_mapping[0x20];
7664
7665 u8 lane3_module_mapping[0x20];
7666
7667 u8 reserved_at_a0[0x160];
7668};
7669
7670struct mlx5_ifc_pmaos_reg_bits {
7671 u8 reserved_at_0[0x8];
7672 u8 module[0x8];
7673 u8 reserved_at_10[0x4];
7674 u8 admin_status[0x4];
7675 u8 reserved_at_18[0x4];
7676 u8 oper_status[0x4];
7677
7678 u8 ase[0x1];
7679 u8 ee[0x1];
7680 u8 reserved_at_22[0x1c];
7681 u8 e[0x2];
7682
7683 u8 reserved_at_40[0x40];
7684};
7685
7686struct mlx5_ifc_plpc_reg_bits {
7687 u8 reserved_at_0[0x4];
7688 u8 profile_id[0xc];
7689 u8 reserved_at_10[0x4];
7690 u8 proto_mask[0x4];
7691 u8 reserved_at_18[0x8];
7692
7693 u8 reserved_at_20[0x10];
7694 u8 lane_speed[0x10];
7695
7696 u8 reserved_at_40[0x17];
7697 u8 lpbf[0x1];
7698 u8 fec_mode_policy[0x8];
7699
7700 u8 retransmission_capability[0x8];
7701 u8 fec_mode_capability[0x18];
7702
7703 u8 retransmission_support_admin[0x8];
7704 u8 fec_mode_support_admin[0x18];
7705
7706 u8 retransmission_request_admin[0x8];
7707 u8 fec_mode_request_admin[0x18];
7708
7709 u8 reserved_at_c0[0x80];
7710};
7711
7712struct mlx5_ifc_plib_reg_bits {
7713 u8 reserved_at_0[0x8];
7714 u8 local_port[0x8];
7715 u8 reserved_at_10[0x8];
7716 u8 ib_port[0x8];
7717
7718 u8 reserved_at_20[0x60];
7719};
7720
7721struct mlx5_ifc_plbf_reg_bits {
7722 u8 reserved_at_0[0x8];
7723 u8 local_port[0x8];
7724 u8 reserved_at_10[0xd];
7725 u8 lbf_mode[0x3];
7726
7727 u8 reserved_at_20[0x20];
7728};
7729
7730struct mlx5_ifc_pipg_reg_bits {
7731 u8 reserved_at_0[0x8];
7732 u8 local_port[0x8];
7733 u8 reserved_at_10[0x10];
7734
7735 u8 dic[0x1];
7736 u8 reserved_at_21[0x19];
7737 u8 ipg[0x4];
7738 u8 reserved_at_3e[0x2];
7739};
7740
7741struct mlx5_ifc_pifr_reg_bits {
7742 u8 reserved_at_0[0x8];
7743 u8 local_port[0x8];
7744 u8 reserved_at_10[0x10];
7745
7746 u8 reserved_at_20[0xe0];
7747
7748 u8 port_filter[8][0x20];
7749
7750 u8 port_filter_update_en[8][0x20];
7751};
7752
7753struct mlx5_ifc_pfcc_reg_bits {
7754 u8 reserved_at_0[0x8];
7755 u8 local_port[0x8];
7756 u8 reserved_at_10[0x10];
7757
7758 u8 ppan[0x4];
7759 u8 reserved_at_24[0x4];
7760 u8 prio_mask_tx[0x8];
7761 u8 reserved_at_30[0x8];
7762 u8 prio_mask_rx[0x8];
7763
7764 u8 pptx[0x1];
7765 u8 aptx[0x1];
7766 u8 reserved_at_42[0x6];
7767 u8 pfctx[0x8];
7768 u8 reserved_at_50[0x10];
7769
7770 u8 pprx[0x1];
7771 u8 aprx[0x1];
7772 u8 reserved_at_62[0x6];
7773 u8 pfcrx[0x8];
7774 u8 reserved_at_70[0x10];
7775
7776 u8 reserved_at_80[0x80];
7777};
7778
7779struct mlx5_ifc_pelc_reg_bits {
7780 u8 op[0x4];
7781 u8 reserved_at_4[0x4];
7782 u8 local_port[0x8];
7783 u8 reserved_at_10[0x10];
7784
7785 u8 op_admin[0x8];
7786 u8 op_capability[0x8];
7787 u8 op_request[0x8];
7788 u8 op_active[0x8];
7789
7790 u8 admin[0x40];
7791
7792 u8 capability[0x40];
7793
7794 u8 request[0x40];
7795
7796 u8 active[0x40];
7797
7798 u8 reserved_at_140[0x80];
7799};
7800
7801struct mlx5_ifc_peir_reg_bits {
7802 u8 reserved_at_0[0x8];
7803 u8 local_port[0x8];
7804 u8 reserved_at_10[0x10];
7805
7806 u8 reserved_at_20[0xc];
7807 u8 error_count[0x4];
7808 u8 reserved_at_30[0x10];
7809
7810 u8 reserved_at_40[0xc];
7811 u8 lane[0x4];
7812 u8 reserved_at_50[0x8];
7813 u8 error_type[0x8];
7814};
7815
7816struct mlx5_ifc_pcam_enhanced_features_bits {
7817 u8 reserved_at_0[0x7b];
7818
7819 u8 rx_buffer_fullness_counters[0x1];
7820 u8 ptys_connector_type[0x1];
7821 u8 reserved_at_7d[0x1];
7822 u8 ppcnt_discard_group[0x1];
7823 u8 ppcnt_statistical_group[0x1];
7824};
7825
7826struct mlx5_ifc_pcam_reg_bits {
7827 u8 reserved_at_0[0x8];
7828 u8 feature_group[0x8];
7829 u8 reserved_at_10[0x8];
7830 u8 access_reg_group[0x8];
7831
7832 u8 reserved_at_20[0x20];
7833
7834 union {
7835 u8 reserved_at_0[0x80];
7836 } port_access_reg_cap_mask;
7837
7838 u8 reserved_at_c0[0x80];
7839
7840 union {
7841 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7842 u8 reserved_at_0[0x80];
7843 } feature_cap_mask;
7844
7845 u8 reserved_at_1c0[0xc0];
7846};
7847
7848struct mlx5_ifc_mcam_enhanced_features_bits {
7849 u8 reserved_at_0[0x7b];
7850 u8 pcie_outbound_stalled[0x1];
7851 u8 tx_overflow_buffer_pkt[0x1];
7852 u8 mtpps_enh_out_per_adj[0x1];
7853 u8 mtpps_fs[0x1];
7854 u8 pcie_performance_group[0x1];
7855};
7856
7857struct mlx5_ifc_mcam_access_reg_bits {
7858 u8 reserved_at_0[0x1c];
7859 u8 mcda[0x1];
7860 u8 mcc[0x1];
7861 u8 mcqi[0x1];
7862 u8 reserved_at_1f[0x1];
7863
7864 u8 regs_95_to_64[0x20];
7865 u8 regs_63_to_32[0x20];
7866 u8 regs_31_to_0[0x20];
7867};
7868
7869struct mlx5_ifc_mcam_reg_bits {
7870 u8 reserved_at_0[0x8];
7871 u8 feature_group[0x8];
7872 u8 reserved_at_10[0x8];
7873 u8 access_reg_group[0x8];
7874
7875 u8 reserved_at_20[0x20];
7876
7877 union {
7878 struct mlx5_ifc_mcam_access_reg_bits access_regs;
7879 u8 reserved_at_0[0x80];
7880 } mng_access_reg_cap_mask;
7881
7882 u8 reserved_at_c0[0x80];
7883
7884 union {
7885 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7886 u8 reserved_at_0[0x80];
7887 } mng_feature_cap_mask;
7888
7889 u8 reserved_at_1c0[0x80];
7890};
7891
7892struct mlx5_ifc_pcap_reg_bits {
7893 u8 reserved_at_0[0x8];
7894 u8 local_port[0x8];
7895 u8 reserved_at_10[0x10];
7896
7897 u8 port_capability_mask[4][0x20];
7898};
7899
7900struct mlx5_ifc_paos_reg_bits {
7901 u8 swid[0x8];
7902 u8 local_port[0x8];
7903 u8 reserved_at_10[0x4];
7904 u8 admin_status[0x4];
7905 u8 reserved_at_18[0x4];
7906 u8 oper_status[0x4];
7907
7908 u8 ase[0x1];
7909 u8 ee[0x1];
7910 u8 reserved_at_22[0x1c];
7911 u8 e[0x2];
7912
7913 u8 reserved_at_40[0x40];
7914};
7915
7916struct mlx5_ifc_pamp_reg_bits {
7917 u8 reserved_at_0[0x8];
7918 u8 opamp_group[0x8];
7919 u8 reserved_at_10[0xc];
7920 u8 opamp_group_type[0x4];
7921
7922 u8 start_index[0x10];
7923 u8 reserved_at_30[0x4];
7924 u8 num_of_indices[0xc];
7925
7926 u8 index_data[18][0x10];
7927};
7928
7929struct mlx5_ifc_pcmr_reg_bits {
7930 u8 reserved_at_0[0x8];
7931 u8 local_port[0x8];
7932 u8 reserved_at_10[0x2e];
7933 u8 fcs_cap[0x1];
7934 u8 reserved_at_3f[0x1f];
7935 u8 fcs_chk[0x1];
7936 u8 reserved_at_5f[0x1];
7937};
7938
7939struct mlx5_ifc_lane_2_module_mapping_bits {
7940 u8 reserved_at_0[0x6];
7941 u8 rx_lane[0x2];
7942 u8 reserved_at_8[0x6];
7943 u8 tx_lane[0x2];
7944 u8 reserved_at_10[0x8];
7945 u8 module[0x8];
7946};
7947
7948struct mlx5_ifc_bufferx_reg_bits {
7949 u8 reserved_at_0[0x6];
7950 u8 lossy[0x1];
7951 u8 epsb[0x1];
7952 u8 reserved_at_8[0xc];
7953 u8 size[0xc];
7954
7955 u8 xoff_threshold[0x10];
7956 u8 xon_threshold[0x10];
7957};
7958
7959struct mlx5_ifc_set_node_in_bits {
7960 u8 node_description[64][0x8];
7961};
7962
7963struct mlx5_ifc_register_power_settings_bits {
7964 u8 reserved_at_0[0x18];
7965 u8 power_settings_level[0x8];
7966
7967 u8 reserved_at_20[0x60];
7968};
7969
7970struct mlx5_ifc_register_host_endianness_bits {
7971 u8 he[0x1];
7972 u8 reserved_at_1[0x1f];
7973
7974 u8 reserved_at_20[0x60];
7975};
7976
7977struct mlx5_ifc_umr_pointer_desc_argument_bits {
7978 u8 reserved_at_0[0x20];
7979
7980 u8 mkey[0x20];
7981
7982 u8 addressh_63_32[0x20];
7983
7984 u8 addressl_31_0[0x20];
7985};
7986
7987struct mlx5_ifc_ud_adrs_vector_bits {
7988 u8 dc_key[0x40];
7989
7990 u8 ext[0x1];
7991 u8 reserved_at_41[0x7];
7992 u8 destination_qp_dct[0x18];
7993
7994 u8 static_rate[0x4];
7995 u8 sl_eth_prio[0x4];
7996 u8 fl[0x1];
7997 u8 mlid[0x7];
7998 u8 rlid_udp_sport[0x10];
7999
8000 u8 reserved_at_80[0x20];
8001
8002 u8 rmac_47_16[0x20];
8003
8004 u8 rmac_15_0[0x10];
8005 u8 tclass[0x8];
8006 u8 hop_limit[0x8];
8007
8008 u8 reserved_at_e0[0x1];
8009 u8 grh[0x1];
8010 u8 reserved_at_e2[0x2];
8011 u8 src_addr_index[0x8];
8012 u8 flow_label[0x14];
8013
8014 u8 rgid_rip[16][0x8];
8015};
8016
8017struct mlx5_ifc_pages_req_event_bits {
8018 u8 reserved_at_0[0x10];
8019 u8 function_id[0x10];
8020
8021 u8 num_pages[0x20];
8022
8023 u8 reserved_at_40[0xa0];
8024};
8025
8026struct mlx5_ifc_eqe_bits {
8027 u8 reserved_at_0[0x8];
8028 u8 event_type[0x8];
8029 u8 reserved_at_10[0x8];
8030 u8 event_sub_type[0x8];
8031
8032 u8 reserved_at_20[0xe0];
8033
8034 union mlx5_ifc_event_auto_bits event_data;
8035
8036 u8 reserved_at_1e0[0x10];
8037 u8 signature[0x8];
8038 u8 reserved_at_1f8[0x7];
8039 u8 owner[0x1];
8040};
8041
8042enum {
8043 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
8044};
8045
8046struct mlx5_ifc_cmd_queue_entry_bits {
8047 u8 type[0x8];
8048 u8 reserved_at_8[0x18];
8049
8050 u8 input_length[0x20];
8051
8052 u8 input_mailbox_pointer_63_32[0x20];
8053
8054 u8 input_mailbox_pointer_31_9[0x17];
8055 u8 reserved_at_77[0x9];
8056
8057 u8 command_input_inline_data[16][0x8];
8058
8059 u8 command_output_inline_data[16][0x8];
8060
8061 u8 output_mailbox_pointer_63_32[0x20];
8062
8063 u8 output_mailbox_pointer_31_9[0x17];
8064 u8 reserved_at_1b7[0x9];
8065
8066 u8 output_length[0x20];
8067
8068 u8 token[0x8];
8069 u8 signature[0x8];
8070 u8 reserved_at_1f0[0x8];
8071 u8 status[0x7];
8072 u8 ownership[0x1];
8073};
8074
8075struct mlx5_ifc_cmd_out_bits {
8076 u8 status[0x8];
8077 u8 reserved_at_8[0x18];
8078
8079 u8 syndrome[0x20];
8080
8081 u8 command_output[0x20];
8082};
8083
8084struct mlx5_ifc_cmd_in_bits {
8085 u8 opcode[0x10];
8086 u8 reserved_at_10[0x10];
8087
8088 u8 reserved_at_20[0x10];
8089 u8 op_mod[0x10];
8090
8091 u8 command[0][0x20];
8092};
8093
8094struct mlx5_ifc_cmd_if_box_bits {
8095 u8 mailbox_data[512][0x8];
8096
8097 u8 reserved_at_1000[0x180];
8098
8099 u8 next_pointer_63_32[0x20];
8100
8101 u8 next_pointer_31_10[0x16];
8102 u8 reserved_at_11b6[0xa];
8103
8104 u8 block_number[0x20];
8105
8106 u8 reserved_at_11e0[0x8];
8107 u8 token[0x8];
8108 u8 ctrl_signature[0x8];
8109 u8 signature[0x8];
8110};
8111
8112struct mlx5_ifc_mtt_bits {
8113 u8 ptag_63_32[0x20];
8114
8115 u8 ptag_31_8[0x18];
8116 u8 reserved_at_38[0x6];
8117 u8 wr_en[0x1];
8118 u8 rd_en[0x1];
8119};
8120
8121struct mlx5_ifc_query_wol_rol_out_bits {
8122 u8 status[0x8];
8123 u8 reserved_at_8[0x18];
8124
8125 u8 syndrome[0x20];
8126
8127 u8 reserved_at_40[0x10];
8128 u8 rol_mode[0x8];
8129 u8 wol_mode[0x8];
8130
8131 u8 reserved_at_60[0x20];
8132};
8133
8134struct mlx5_ifc_query_wol_rol_in_bits {
8135 u8 opcode[0x10];
8136 u8 reserved_at_10[0x10];
8137
8138 u8 reserved_at_20[0x10];
8139 u8 op_mod[0x10];
8140
8141 u8 reserved_at_40[0x40];
8142};
8143
8144struct mlx5_ifc_set_wol_rol_out_bits {
8145 u8 status[0x8];
8146 u8 reserved_at_8[0x18];
8147
8148 u8 syndrome[0x20];
8149
8150 u8 reserved_at_40[0x40];
8151};
8152
8153struct mlx5_ifc_set_wol_rol_in_bits {
8154 u8 opcode[0x10];
8155 u8 reserved_at_10[0x10];
8156
8157 u8 reserved_at_20[0x10];
8158 u8 op_mod[0x10];
8159
8160 u8 rol_mode_valid[0x1];
8161 u8 wol_mode_valid[0x1];
8162 u8 reserved_at_42[0xe];
8163 u8 rol_mode[0x8];
8164 u8 wol_mode[0x8];
8165
8166 u8 reserved_at_60[0x20];
8167};
8168
8169enum {
8170 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8171 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8172 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8173};
8174
8175enum {
8176 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8177 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8178 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8179};
8180
8181enum {
8182 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8183 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8184 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8185 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8186 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8187 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8188 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8189 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8190 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8191 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8192 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8193};
8194
8195struct mlx5_ifc_initial_seg_bits {
8196 u8 fw_rev_minor[0x10];
8197 u8 fw_rev_major[0x10];
8198
8199 u8 cmd_interface_rev[0x10];
8200 u8 fw_rev_subminor[0x10];
8201
8202 u8 reserved_at_40[0x40];
8203
8204 u8 cmdq_phy_addr_63_32[0x20];
8205
8206 u8 cmdq_phy_addr_31_12[0x14];
8207 u8 reserved_at_b4[0x2];
8208 u8 nic_interface[0x2];
8209 u8 log_cmdq_size[0x4];
8210 u8 log_cmdq_stride[0x4];
8211
8212 u8 command_doorbell_vector[0x20];
8213
8214 u8 reserved_at_e0[0xf00];
8215
8216 u8 initializing[0x1];
8217 u8 reserved_at_fe1[0x4];
8218 u8 nic_interface_supported[0x3];
8219 u8 reserved_at_fe8[0x18];
8220
8221 struct mlx5_ifc_health_buffer_bits health_buffer;
8222
8223 u8 no_dram_nic_offset[0x20];
8224
8225 u8 reserved_at_1220[0x6e40];
8226
8227 u8 reserved_at_8060[0x1f];
8228 u8 clear_int[0x1];
8229
8230 u8 health_syndrome[0x8];
8231 u8 health_counter[0x18];
8232
8233 u8 reserved_at_80a0[0x17fc0];
8234};
8235
8236struct mlx5_ifc_mtpps_reg_bits {
8237 u8 reserved_at_0[0xc];
8238 u8 cap_number_of_pps_pins[0x4];
8239 u8 reserved_at_10[0x4];
8240 u8 cap_max_num_of_pps_in_pins[0x4];
8241 u8 reserved_at_18[0x4];
8242 u8 cap_max_num_of_pps_out_pins[0x4];
8243
8244 u8 reserved_at_20[0x24];
8245 u8 cap_pin_3_mode[0x4];
8246 u8 reserved_at_48[0x4];
8247 u8 cap_pin_2_mode[0x4];
8248 u8 reserved_at_50[0x4];
8249 u8 cap_pin_1_mode[0x4];
8250 u8 reserved_at_58[0x4];
8251 u8 cap_pin_0_mode[0x4];
8252
8253 u8 reserved_at_60[0x4];
8254 u8 cap_pin_7_mode[0x4];
8255 u8 reserved_at_68[0x4];
8256 u8 cap_pin_6_mode[0x4];
8257 u8 reserved_at_70[0x4];
8258 u8 cap_pin_5_mode[0x4];
8259 u8 reserved_at_78[0x4];
8260 u8 cap_pin_4_mode[0x4];
8261
8262 u8 field_select[0x20];
8263 u8 reserved_at_a0[0x60];
8264
8265 u8 enable[0x1];
8266 u8 reserved_at_101[0xb];
8267 u8 pattern[0x4];
8268 u8 reserved_at_110[0x4];
8269 u8 pin_mode[0x4];
8270 u8 pin[0x8];
8271
8272 u8 reserved_at_120[0x20];
8273
8274 u8 time_stamp[0x40];
8275
8276 u8 out_pulse_duration[0x10];
8277 u8 out_periodic_adjustment[0x10];
8278 u8 enhanced_out_periodic_adjustment[0x20];
8279
8280 u8 reserved_at_1c0[0x20];
8281};
8282
8283struct mlx5_ifc_mtppse_reg_bits {
8284 u8 reserved_at_0[0x18];
8285 u8 pin[0x8];
8286 u8 event_arm[0x1];
8287 u8 reserved_at_21[0x1b];
8288 u8 event_generation_mode[0x4];
8289 u8 reserved_at_40[0x40];
8290};
8291
8292struct mlx5_ifc_mcqi_cap_bits {
8293 u8 supported_info_bitmask[0x20];
8294
8295 u8 component_size[0x20];
8296
8297 u8 max_component_size[0x20];
8298
8299 u8 log_mcda_word_size[0x4];
8300 u8 reserved_at_64[0xc];
8301 u8 mcda_max_write_size[0x10];
8302
8303 u8 rd_en[0x1];
8304 u8 reserved_at_81[0x1];
8305 u8 match_chip_id[0x1];
8306 u8 match_psid[0x1];
8307 u8 check_user_timestamp[0x1];
8308 u8 match_base_guid_mac[0x1];
8309 u8 reserved_at_86[0x1a];
8310};
8311
8312struct mlx5_ifc_mcqi_reg_bits {
8313 u8 read_pending_component[0x1];
8314 u8 reserved_at_1[0xf];
8315 u8 component_index[0x10];
8316
8317 u8 reserved_at_20[0x20];
8318
8319 u8 reserved_at_40[0x1b];
8320 u8 info_type[0x5];
8321
8322 u8 info_size[0x20];
8323
8324 u8 offset[0x20];
8325
8326 u8 reserved_at_a0[0x10];
8327 u8 data_size[0x10];
8328
8329 u8 data[0][0x20];
8330};
8331
8332struct mlx5_ifc_mcc_reg_bits {
8333 u8 reserved_at_0[0x4];
8334 u8 time_elapsed_since_last_cmd[0xc];
8335 u8 reserved_at_10[0x8];
8336 u8 instruction[0x8];
8337
8338 u8 reserved_at_20[0x10];
8339 u8 component_index[0x10];
8340
8341 u8 reserved_at_40[0x8];
8342 u8 update_handle[0x18];
8343
8344 u8 handle_owner_type[0x4];
8345 u8 handle_owner_host_id[0x4];
8346 u8 reserved_at_68[0x1];
8347 u8 control_progress[0x7];
8348 u8 error_code[0x8];
8349 u8 reserved_at_78[0x4];
8350 u8 control_state[0x4];
8351
8352 u8 component_size[0x20];
8353
8354 u8 reserved_at_a0[0x60];
8355};
8356
8357struct mlx5_ifc_mcda_reg_bits {
8358 u8 reserved_at_0[0x8];
8359 u8 update_handle[0x18];
8360
8361 u8 offset[0x20];
8362
8363 u8 reserved_at_40[0x10];
8364 u8 size[0x10];
8365
8366 u8 reserved_at_60[0x20];
8367
8368 u8 data[0][0x20];
8369};
8370
8371union mlx5_ifc_ports_control_registers_document_bits {
8372 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8373 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8374 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8375 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8376 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8377 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8378 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8379 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8380 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8381 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8382 struct mlx5_ifc_paos_reg_bits paos_reg;
8383 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8384 struct mlx5_ifc_peir_reg_bits peir_reg;
8385 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8386 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8387 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8388 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8389 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8390 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8391 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8392 struct mlx5_ifc_plib_reg_bits plib_reg;
8393 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8394 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8395 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8396 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8397 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8398 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8399 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8400 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8401 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8402 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8403 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8404 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8405 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8406 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8407 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8408 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8409 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8410 struct mlx5_ifc_ptys_reg_bits ptys_reg;
8411 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8412 struct mlx5_ifc_pude_reg_bits pude_reg;
8413 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8414 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8415 struct mlx5_ifc_sltp_reg_bits sltp_reg;
8416 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8417 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8418 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8419 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8420 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8421 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8422 struct mlx5_ifc_mcc_reg_bits mcc_reg;
8423 struct mlx5_ifc_mcda_reg_bits mcda_reg;
8424 u8 reserved_at_0[0x60e0];
8425};
8426
8427union mlx5_ifc_debug_enhancements_document_bits {
8428 struct mlx5_ifc_health_buffer_bits health_buffer;
8429 u8 reserved_at_0[0x200];
8430};
8431
8432union mlx5_ifc_uplink_pci_interface_document_bits {
8433 struct mlx5_ifc_initial_seg_bits initial_seg;
8434 u8 reserved_at_0[0x20060];
8435};
8436
8437struct mlx5_ifc_set_flow_table_root_out_bits {
8438 u8 status[0x8];
8439 u8 reserved_at_8[0x18];
8440
8441 u8 syndrome[0x20];
8442
8443 u8 reserved_at_40[0x40];
8444};
8445
8446struct mlx5_ifc_set_flow_table_root_in_bits {
8447 u8 opcode[0x10];
8448 u8 reserved_at_10[0x10];
8449
8450 u8 reserved_at_20[0x10];
8451 u8 op_mod[0x10];
8452
8453 u8 other_vport[0x1];
8454 u8 reserved_at_41[0xf];
8455 u8 vport_number[0x10];
8456
8457 u8 reserved_at_60[0x20];
8458
8459 u8 table_type[0x8];
8460 u8 reserved_at_88[0x18];
8461
8462 u8 reserved_at_a0[0x8];
8463 u8 table_id[0x18];
8464
8465 u8 reserved_at_c0[0x8];
8466 u8 underlay_qpn[0x18];
8467 u8 reserved_at_e0[0x120];
8468};
8469
8470enum {
8471 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8472 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8473};
8474
8475struct mlx5_ifc_modify_flow_table_out_bits {
8476 u8 status[0x8];
8477 u8 reserved_at_8[0x18];
8478
8479 u8 syndrome[0x20];
8480
8481 u8 reserved_at_40[0x40];
8482};
8483
8484struct mlx5_ifc_modify_flow_table_in_bits {
8485 u8 opcode[0x10];
8486 u8 reserved_at_10[0x10];
8487
8488 u8 reserved_at_20[0x10];
8489 u8 op_mod[0x10];
8490
8491 u8 other_vport[0x1];
8492 u8 reserved_at_41[0xf];
8493 u8 vport_number[0x10];
8494
8495 u8 reserved_at_60[0x10];
8496 u8 modify_field_select[0x10];
8497
8498 u8 table_type[0x8];
8499 u8 reserved_at_88[0x18];
8500
8501 u8 reserved_at_a0[0x8];
8502 u8 table_id[0x18];
8503
8504 struct mlx5_ifc_flow_table_context_bits flow_table_context;
8505};
8506
8507struct mlx5_ifc_ets_tcn_config_reg_bits {
8508 u8 g[0x1];
8509 u8 b[0x1];
8510 u8 r[0x1];
8511 u8 reserved_at_3[0x9];
8512 u8 group[0x4];
8513 u8 reserved_at_10[0x9];
8514 u8 bw_allocation[0x7];
8515
8516 u8 reserved_at_20[0xc];
8517 u8 max_bw_units[0x4];
8518 u8 reserved_at_30[0x8];
8519 u8 max_bw_value[0x8];
8520};
8521
8522struct mlx5_ifc_ets_global_config_reg_bits {
8523 u8 reserved_at_0[0x2];
8524 u8 r[0x1];
8525 u8 reserved_at_3[0x1d];
8526
8527 u8 reserved_at_20[0xc];
8528 u8 max_bw_units[0x4];
8529 u8 reserved_at_30[0x8];
8530 u8 max_bw_value[0x8];
8531};
8532
8533struct mlx5_ifc_qetc_reg_bits {
8534 u8 reserved_at_0[0x8];
8535 u8 port_number[0x8];
8536 u8 reserved_at_10[0x30];
8537
8538 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8539 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8540};
8541
8542struct mlx5_ifc_qtct_reg_bits {
8543 u8 reserved_at_0[0x8];
8544 u8 port_number[0x8];
8545 u8 reserved_at_10[0xd];
8546 u8 prio[0x3];
8547
8548 u8 reserved_at_20[0x1d];
8549 u8 tclass[0x3];
8550};
8551
8552struct mlx5_ifc_mcia_reg_bits {
8553 u8 l[0x1];
8554 u8 reserved_at_1[0x7];
8555 u8 module[0x8];
8556 u8 reserved_at_10[0x8];
8557 u8 status[0x8];
8558
8559 u8 i2c_device_address[0x8];
8560 u8 page_number[0x8];
8561 u8 device_address[0x10];
8562
8563 u8 reserved_at_40[0x10];
8564 u8 size[0x10];
8565
8566 u8 reserved_at_60[0x20];
8567
8568 u8 dword_0[0x20];
8569 u8 dword_1[0x20];
8570 u8 dword_2[0x20];
8571 u8 dword_3[0x20];
8572 u8 dword_4[0x20];
8573 u8 dword_5[0x20];
8574 u8 dword_6[0x20];
8575 u8 dword_7[0x20];
8576 u8 dword_8[0x20];
8577 u8 dword_9[0x20];
8578 u8 dword_10[0x20];
8579 u8 dword_11[0x20];
8580};
8581
8582struct mlx5_ifc_dcbx_param_bits {
8583 u8 dcbx_cee_cap[0x1];
8584 u8 dcbx_ieee_cap[0x1];
8585 u8 dcbx_standby_cap[0x1];
8586 u8 reserved_at_0[0x5];
8587 u8 port_number[0x8];
8588 u8 reserved_at_10[0xa];
8589 u8 max_application_table_size[6];
8590 u8 reserved_at_20[0x15];
8591 u8 version_oper[0x3];
8592 u8 reserved_at_38[5];
8593 u8 version_admin[0x3];
8594 u8 willing_admin[0x1];
8595 u8 reserved_at_41[0x3];
8596 u8 pfc_cap_oper[0x4];
8597 u8 reserved_at_48[0x4];
8598 u8 pfc_cap_admin[0x4];
8599 u8 reserved_at_50[0x4];
8600 u8 num_of_tc_oper[0x4];
8601 u8 reserved_at_58[0x4];
8602 u8 num_of_tc_admin[0x4];
8603 u8 remote_willing[0x1];
8604 u8 reserved_at_61[3];
8605 u8 remote_pfc_cap[4];
8606 u8 reserved_at_68[0x14];
8607 u8 remote_num_of_tc[0x4];
8608 u8 reserved_at_80[0x18];
8609 u8 error[0x8];
8610 u8 reserved_at_a0[0x160];
8611};
8612
8613struct mlx5_ifc_lagc_bits {
8614 u8 reserved_at_0[0x1d];
8615 u8 lag_state[0x3];
8616
8617 u8 reserved_at_20[0x14];
8618 u8 tx_remap_affinity_2[0x4];
8619 u8 reserved_at_38[0x4];
8620 u8 tx_remap_affinity_1[0x4];
8621};
8622
8623struct mlx5_ifc_create_lag_out_bits {
8624 u8 status[0x8];
8625 u8 reserved_at_8[0x18];
8626
8627 u8 syndrome[0x20];
8628
8629 u8 reserved_at_40[0x40];
8630};
8631
8632struct mlx5_ifc_create_lag_in_bits {
8633 u8 opcode[0x10];
8634 u8 reserved_at_10[0x10];
8635
8636 u8 reserved_at_20[0x10];
8637 u8 op_mod[0x10];
8638
8639 struct mlx5_ifc_lagc_bits ctx;
8640};
8641
8642struct mlx5_ifc_modify_lag_out_bits {
8643 u8 status[0x8];
8644 u8 reserved_at_8[0x18];
8645
8646 u8 syndrome[0x20];
8647
8648 u8 reserved_at_40[0x40];
8649};
8650
8651struct mlx5_ifc_modify_lag_in_bits {
8652 u8 opcode[0x10];
8653 u8 reserved_at_10[0x10];
8654
8655 u8 reserved_at_20[0x10];
8656 u8 op_mod[0x10];
8657
8658 u8 reserved_at_40[0x20];
8659 u8 field_select[0x20];
8660
8661 struct mlx5_ifc_lagc_bits ctx;
8662};
8663
8664struct mlx5_ifc_query_lag_out_bits {
8665 u8 status[0x8];
8666 u8 reserved_at_8[0x18];
8667
8668 u8 syndrome[0x20];
8669
8670 u8 reserved_at_40[0x40];
8671
8672 struct mlx5_ifc_lagc_bits ctx;
8673};
8674
8675struct mlx5_ifc_query_lag_in_bits {
8676 u8 opcode[0x10];
8677 u8 reserved_at_10[0x10];
8678
8679 u8 reserved_at_20[0x10];
8680 u8 op_mod[0x10];
8681
8682 u8 reserved_at_40[0x40];
8683};
8684
8685struct mlx5_ifc_destroy_lag_out_bits {
8686 u8 status[0x8];
8687 u8 reserved_at_8[0x18];
8688
8689 u8 syndrome[0x20];
8690
8691 u8 reserved_at_40[0x40];
8692};
8693
8694struct mlx5_ifc_destroy_lag_in_bits {
8695 u8 opcode[0x10];
8696 u8 reserved_at_10[0x10];
8697
8698 u8 reserved_at_20[0x10];
8699 u8 op_mod[0x10];
8700
8701 u8 reserved_at_40[0x40];
8702};
8703
8704struct mlx5_ifc_create_vport_lag_out_bits {
8705 u8 status[0x8];
8706 u8 reserved_at_8[0x18];
8707
8708 u8 syndrome[0x20];
8709
8710 u8 reserved_at_40[0x40];
8711};
8712
8713struct mlx5_ifc_create_vport_lag_in_bits {
8714 u8 opcode[0x10];
8715 u8 reserved_at_10[0x10];
8716
8717 u8 reserved_at_20[0x10];
8718 u8 op_mod[0x10];
8719
8720 u8 reserved_at_40[0x40];
8721};
8722
8723struct mlx5_ifc_destroy_vport_lag_out_bits {
8724 u8 status[0x8];
8725 u8 reserved_at_8[0x18];
8726
8727 u8 syndrome[0x20];
8728
8729 u8 reserved_at_40[0x40];
8730};
8731
8732struct mlx5_ifc_destroy_vport_lag_in_bits {
8733 u8 opcode[0x10];
8734 u8 reserved_at_10[0x10];
8735
8736 u8 reserved_at_20[0x10];
8737 u8 op_mod[0x10];
8738
8739 u8 reserved_at_40[0x40];
8740};
8741
8742#endif /* MLX5_IFC_H */