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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * linux/arch/arm/include/asm/pmu.h
3 *
4 * Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#ifndef __ARM_PMU_H__
13#define __ARM_PMU_H__
14
15#include <linux/interrupt.h>
16#include <linux/perf_event.h>
17#include <linux/sysfs.h>
18#include <asm/cputype.h>
19
20/*
21 * struct arm_pmu_platdata - ARM PMU platform data
22 *
23 * @handle_irq: an optional handler which will be called from the
24 * interrupt and passed the address of the low level handler,
25 * and can be used to implement any platform specific handling
26 * before or after calling it.
27 *
28 * @irq_flags: if non-zero, these flags will be passed to request_irq
29 * when requesting interrupts for this PMU device.
30 */
31struct arm_pmu_platdata {
32 irqreturn_t (*handle_irq)(int irq, void *dev,
33 irq_handler_t pmu_handler);
34 unsigned long irq_flags;
35};
36
37#ifdef CONFIG_ARM_PMU
38
39/*
40 * The ARMv7 CPU PMU supports up to 32 event counters.
41 */
42#define ARMPMU_MAX_HWEVENTS 32
43
44#define HW_OP_UNSUPPORTED 0xFFFF
45#define C(_x) PERF_COUNT_HW_CACHE_##_x
46#define CACHE_OP_UNSUPPORTED 0xFFFF
47
48#define PERF_MAP_ALL_UNSUPPORTED \
49 [0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED
50
51#define PERF_CACHE_MAP_ALL_UNSUPPORTED \
52[0 ... C(MAX) - 1] = { \
53 [0 ... C(OP_MAX) - 1] = { \
54 [0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED, \
55 }, \
56}
57
58/* The events for a given PMU register set. */
59struct pmu_hw_events {
60 /*
61 * The events that are active on the PMU for the given index.
62 */
63 struct perf_event *events[ARMPMU_MAX_HWEVENTS];
64
65 /*
66 * A 1 bit for an index indicates that the counter is being used for
67 * an event. A 0 means that the counter can be used.
68 */
69 DECLARE_BITMAP(used_mask, ARMPMU_MAX_HWEVENTS);
70
71 /*
72 * Hardware lock to serialize accesses to PMU registers. Needed for the
73 * read/modify/write sequences.
74 */
75 raw_spinlock_t pmu_lock;
76
77 /*
78 * When using percpu IRQs, we need a percpu dev_id. Place it here as we
79 * already have to allocate this struct per cpu.
80 */
81 struct arm_pmu *percpu_pmu;
82
83 int irq;
84};
85
86enum armpmu_attr_groups {
87 ARMPMU_ATTR_GROUP_COMMON,
88 ARMPMU_ATTR_GROUP_EVENTS,
89 ARMPMU_ATTR_GROUP_FORMATS,
90 ARMPMU_NR_ATTR_GROUPS
91};
92
93struct arm_pmu {
94 struct pmu pmu;
95 cpumask_t active_irqs;
96 cpumask_t supported_cpus;
97 char *name;
98 irqreturn_t (*handle_irq)(int irq_num, void *dev);
99 void (*enable)(struct perf_event *event);
100 void (*disable)(struct perf_event *event);
101 int (*get_event_idx)(struct pmu_hw_events *hw_events,
102 struct perf_event *event);
103 void (*clear_event_idx)(struct pmu_hw_events *hw_events,
104 struct perf_event *event);
105 int (*set_event_filter)(struct hw_perf_event *evt,
106 struct perf_event_attr *attr);
107 u32 (*read_counter)(struct perf_event *event);
108 void (*write_counter)(struct perf_event *event, u32 val);
109 void (*start)(struct arm_pmu *);
110 void (*stop)(struct arm_pmu *);
111 void (*reset)(void *);
112 int (*map_event)(struct perf_event *event);
113 int num_events;
114 u64 max_period;
115 bool secure_access; /* 32-bit ARM only */
116#define ARMV8_PMUV3_MAX_COMMON_EVENTS 0x40
117 DECLARE_BITMAP(pmceid_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS);
118 struct platform_device *plat_device;
119 struct pmu_hw_events __percpu *hw_events;
120 struct hlist_node node;
121 struct notifier_block cpu_pm_nb;
122 /* the attr_groups array must be NULL-terminated */
123 const struct attribute_group *attr_groups[ARMPMU_NR_ATTR_GROUPS + 1];
124
125 /* Only to be used by ACPI probing code */
126 unsigned long acpi_cpuid;
127};
128
129#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
130
131u64 armpmu_event_update(struct perf_event *event);
132
133int armpmu_event_set_period(struct perf_event *event);
134
135int armpmu_map_event(struct perf_event *event,
136 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
137 const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
138 [PERF_COUNT_HW_CACHE_OP_MAX]
139 [PERF_COUNT_HW_CACHE_RESULT_MAX],
140 u32 raw_event_mask);
141
142typedef int (*armpmu_init_fn)(struct arm_pmu *);
143
144struct pmu_probe_info {
145 unsigned int cpuid;
146 unsigned int mask;
147 armpmu_init_fn init;
148};
149
150#define PMU_PROBE(_cpuid, _mask, _fn) \
151{ \
152 .cpuid = (_cpuid), \
153 .mask = (_mask), \
154 .init = (_fn), \
155}
156
157#define ARM_PMU_PROBE(_cpuid, _fn) \
158 PMU_PROBE(_cpuid, ARM_CPU_PART_MASK, _fn)
159
160#define ARM_PMU_XSCALE_MASK ((0xff << 24) | ARM_CPU_XSCALE_ARCH_MASK)
161
162#define XSCALE_PMU_PROBE(_version, _fn) \
163 PMU_PROBE(ARM_CPU_IMP_INTEL << 24 | _version, ARM_PMU_XSCALE_MASK, _fn)
164
165int arm_pmu_device_probe(struct platform_device *pdev,
166 const struct of_device_id *of_table,
167 const struct pmu_probe_info *probe_table);
168
169#ifdef CONFIG_ACPI
170int arm_pmu_acpi_probe(armpmu_init_fn init_fn);
171#else
172static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; }
173#endif
174
175/* Internal functions only for core arm_pmu code */
176struct arm_pmu *armpmu_alloc(void);
177void armpmu_free(struct arm_pmu *pmu);
178int armpmu_register(struct arm_pmu *pmu);
179int armpmu_request_irqs(struct arm_pmu *armpmu);
180void armpmu_free_irqs(struct arm_pmu *armpmu);
181int armpmu_request_irq(struct arm_pmu *armpmu, int cpu);
182void armpmu_free_irq(struct arm_pmu *armpmu, int cpu);
183
184#define ARMV8_PMU_PDEV_NAME "armv8-pmu"
185
186#endif /* CONFIG_ARM_PMU */
187
188#endif /* __ARM_PMU_H__ */