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1/*
2 * include/asm-xtensa/pgtable.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Copyright (C) 2001 - 2007 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_PGTABLE_H
12#define _XTENSA_PGTABLE_H
13
14#include <asm-generic/pgtable-nopmd.h>
15#include <asm/page.h>
16
17/*
18 * We only use two ring levels, user and kernel space.
19 */
20
21#define USER_RING 1 /* user ring level */
22#define KERNEL_RING 0 /* kernel ring level */
23
24/*
25 * The Xtensa architecture port of Linux has a two-level page table system,
26 * i.e. the logical three-level Linux page table layout is folded.
27 * Each task has the following memory page tables:
28 *
29 * PGD table (page directory), ie. 3rd-level page table:
30 * One page (4 kB) of 1024 (PTRS_PER_PGD) pointers to PTE tables
31 * (Architectures that don't have the PMD folded point to the PMD tables)
32 *
33 * The pointer to the PGD table for a given task can be retrieved from
34 * the task structure (struct task_struct*) t, e.g. current():
35 * (t->mm ? t->mm : t->active_mm)->pgd
36 *
37 * PMD tables (page middle-directory), ie. 2nd-level page tables:
38 * Absent for the Xtensa architecture (folded, PTRS_PER_PMD == 1).
39 *
40 * PTE tables (page table entry), ie. 1st-level page tables:
41 * One page (4 kB) of 1024 (PTRS_PER_PTE) PTEs with a special PTE
42 * invalid_pte_table for absent mappings.
43 *
44 * The individual pages are 4 kB big with special pages for the empty_zero_page.
45 */
46
47#define PGDIR_SHIFT 22
48#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
49#define PGDIR_MASK (~(PGDIR_SIZE-1))
50
51/*
52 * Entries per page directory level: we use two-level, so
53 * we don't really have any PMD directory physically.
54 */
55#define PTRS_PER_PTE 1024
56#define PTRS_PER_PTE_SHIFT 10
57#define PTRS_PER_PGD 1024
58#define PGD_ORDER 0
59#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
60#define FIRST_USER_ADDRESS 0
61#define FIRST_USER_PGD_NR (FIRST_USER_ADDRESS >> PGDIR_SHIFT)
62
63/*
64 * Virtual memory area. We keep a distance to other memory regions to be
65 * on the safe side. We also use this area for cache aliasing.
66 */
67
68#define VMALLOC_START 0xC0000000
69#define VMALLOC_END 0xC6FEFFFF
70#define TLBTEMP_BASE_1 0xC6FF0000
71#define TLBTEMP_BASE_2 0xC6FF8000
72#define MODULE_START 0xC7000000
73#define MODULE_END 0xC7FFFFFF
74
75/*
76 * Xtensa Linux config PTE layout (when present):
77 * 31-12: PPN
78 * 11-6: Software
79 * 5-4: RING
80 * 3-0: CA
81 *
82 * Similar to the Alpha and MIPS ports, we need to keep track of the ref
83 * and mod bits in software. We have a software "you can read
84 * from this page" bit, and a hardware one which actually lets the
85 * process read from the page. On the same token we have a software
86 * writable bit and the real hardware one which actually lets the
87 * process write to the page.
88 *
89 * See further below for PTE layout for swapped-out pages.
90 */
91
92#define _PAGE_HW_EXEC (1<<0) /* hardware: page is executable */
93#define _PAGE_HW_WRITE (1<<1) /* hardware: page is writable */
94
95#define _PAGE_FILE (1<<1) /* non-linear mapping, if !present */
96#define _PAGE_PROTNONE (3<<0) /* special case for VM_PROT_NONE */
97
98/* None of these cache modes include MP coherency: */
99#define _PAGE_CA_BYPASS (0<<2) /* bypass, non-speculative */
100#define _PAGE_CA_WB (1<<2) /* write-back */
101#define _PAGE_CA_WT (2<<2) /* write-through */
102#define _PAGE_CA_MASK (3<<2)
103#define _PAGE_INVALID (3<<2)
104
105#define _PAGE_USER (1<<4) /* user access (ring=1) */
106
107/* Software */
108#define _PAGE_WRITABLE_BIT 6
109#define _PAGE_WRITABLE (1<<6) /* software: page writable */
110#define _PAGE_DIRTY (1<<7) /* software: page dirty */
111#define _PAGE_ACCESSED (1<<8) /* software: page accessed (read) */
112
113/* On older HW revisions, we always have to set bit 0 */
114#if XCHAL_HW_VERSION_MAJOR < 2000
115# define _PAGE_VALID (1<<0)
116#else
117# define _PAGE_VALID 0
118#endif
119
120#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
121#define _PAGE_PRESENT (_PAGE_VALID | _PAGE_CA_WB | _PAGE_ACCESSED)
122
123#ifdef CONFIG_MMU
124
125#define PAGE_NONE __pgprot(_PAGE_INVALID | _PAGE_USER | _PAGE_PROTNONE)
126#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER)
127#define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
128#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER)
129#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
130#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE)
131#define PAGE_SHARED_EXEC \
132 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE | _PAGE_HW_EXEC)
133#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_HW_WRITE)
134#define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT|_PAGE_HW_WRITE|_PAGE_HW_EXEC)
135
136#if (DCACHE_WAY_SIZE > PAGE_SIZE)
137# define _PAGE_DIRECTORY (_PAGE_VALID | _PAGE_ACCESSED)
138#else
139# define _PAGE_DIRECTORY (_PAGE_VALID | _PAGE_ACCESSED | _PAGE_CA_WB)
140#endif
141
142#else /* no mmu */
143
144# define PAGE_NONE __pgprot(0)
145# define PAGE_SHARED __pgprot(0)
146# define PAGE_COPY __pgprot(0)
147# define PAGE_READONLY __pgprot(0)
148# define PAGE_KERNEL __pgprot(0)
149
150#endif
151
152/*
153 * On certain configurations of Xtensa MMUs (eg. the initial Linux config),
154 * the MMU can't do page protection for execute, and considers that the same as
155 * read. Also, write permissions may imply read permissions.
156 * What follows is the closest we can get by reasonable means..
157 * See linux/mm/mmap.c for protection_map[] array that uses these definitions.
158 */
159#define __P000 PAGE_NONE /* private --- */
160#define __P001 PAGE_READONLY /* private --r */
161#define __P010 PAGE_COPY /* private -w- */
162#define __P011 PAGE_COPY /* private -wr */
163#define __P100 PAGE_READONLY_EXEC /* private x-- */
164#define __P101 PAGE_READONLY_EXEC /* private x-r */
165#define __P110 PAGE_COPY_EXEC /* private xw- */
166#define __P111 PAGE_COPY_EXEC /* private xwr */
167
168#define __S000 PAGE_NONE /* shared --- */
169#define __S001 PAGE_READONLY /* shared --r */
170#define __S010 PAGE_SHARED /* shared -w- */
171#define __S011 PAGE_SHARED /* shared -wr */
172#define __S100 PAGE_READONLY_EXEC /* shared x-- */
173#define __S101 PAGE_READONLY_EXEC /* shared x-r */
174#define __S110 PAGE_SHARED_EXEC /* shared xw- */
175#define __S111 PAGE_SHARED_EXEC /* shared xwr */
176
177#ifndef __ASSEMBLY__
178
179#define pte_ERROR(e) \
180 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
181#define pgd_ERROR(e) \
182 printk("%s:%d: bad pgd entry %08lx.\n", __FILE__, __LINE__, pgd_val(e))
183
184extern unsigned long empty_zero_page[1024];
185
186#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
187
188extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)];
189
190/*
191 * The pmd contains the kernel virtual address of the pte page.
192 */
193#define pmd_page_vaddr(pmd) ((unsigned long)(pmd_val(pmd) & PAGE_MASK))
194#define pmd_page(pmd) virt_to_page(pmd_val(pmd))
195
196/*
197 * pte status.
198 */
199#define pte_none(pte) (pte_val(pte) == _PAGE_INVALID)
200#define pte_present(pte) \
201 (((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_INVALID) \
202 || ((pte_val(pte) & _PAGE_PROTNONE) == _PAGE_PROTNONE))
203#define pte_clear(mm,addr,ptep) \
204 do { update_pte(ptep, __pte(_PAGE_INVALID)); } while(0)
205
206#define pmd_none(pmd) (!pmd_val(pmd))
207#define pmd_present(pmd) (pmd_val(pmd) & PAGE_MASK)
208#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
209#define pmd_clear(pmdp) do { set_pmd(pmdp, __pmd(0)); } while (0)
210
211static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITABLE; }
212static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
213static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
214static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
215static inline pte_t pte_wrprotect(pte_t pte)
216 { pte_val(pte) &= ~(_PAGE_WRITABLE | _PAGE_HW_WRITE); return pte; }
217static inline pte_t pte_mkclean(pte_t pte)
218 { pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HW_WRITE); return pte; }
219static inline pte_t pte_mkold(pte_t pte)
220 { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
221static inline pte_t pte_mkdirty(pte_t pte)
222 { pte_val(pte) |= _PAGE_DIRTY; return pte; }
223static inline pte_t pte_mkyoung(pte_t pte)
224 { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
225static inline pte_t pte_mkwrite(pte_t pte)
226 { pte_val(pte) |= _PAGE_WRITABLE; return pte; }
227
228/*
229 * Conversion functions: convert a page and protection to a page entry,
230 * and a page entry and page directory to the page they refer to.
231 */
232
233#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
234#define pte_same(a,b) (pte_val(a) == pte_val(b))
235#define pte_page(x) pfn_to_page(pte_pfn(x))
236#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
237#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
238
239static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
240{
241 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
242}
243
244/*
245 * Certain architectures need to do special things when pte's
246 * within a page table are directly modified. Thus, the following
247 * hook is made available.
248 */
249static inline void update_pte(pte_t *ptep, pte_t pteval)
250{
251 *ptep = pteval;
252#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
253 __asm__ __volatile__ ("dhwb %0, 0" :: "a" (ptep));
254#endif
255
256}
257
258struct mm_struct;
259
260static inline void
261set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pteval)
262{
263 update_pte(ptep, pteval);
264}
265
266
267static inline void
268set_pmd(pmd_t *pmdp, pmd_t pmdval)
269{
270 *pmdp = pmdval;
271}
272
273struct vm_area_struct;
274
275static inline int
276ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr,
277 pte_t *ptep)
278{
279 pte_t pte = *ptep;
280 if (!pte_young(pte))
281 return 0;
282 update_pte(ptep, pte_mkold(pte));
283 return 1;
284}
285
286static inline pte_t
287ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
288{
289 pte_t pte = *ptep;
290 pte_clear(mm, addr, ptep);
291 return pte;
292}
293
294static inline void
295ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
296{
297 pte_t pte = *ptep;
298 update_pte(ptep, pte_wrprotect(pte));
299}
300
301/* to find an entry in a kernel page-table-directory */
302#define pgd_offset_k(address) pgd_offset(&init_mm, address)
303
304/* to find an entry in a page-table-directory */
305#define pgd_offset(mm,address) ((mm)->pgd + pgd_index(address))
306
307#define pgd_index(address) ((address) >> PGDIR_SHIFT)
308
309/* Find an entry in the second-level page table.. */
310#define pmd_offset(dir,address) ((pmd_t*)(dir))
311
312/* Find an entry in the third-level page table.. */
313#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
314#define pte_offset_kernel(dir,addr) \
315 ((pte_t*) pmd_page_vaddr(*(dir)) + pte_index(addr))
316#define pte_offset_map(dir,addr) pte_offset_kernel((dir),(addr))
317#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir),(addr))
318
319#define pte_unmap(pte) do { } while (0)
320#define pte_unmap_nested(pte) do { } while (0)
321
322
323/*
324 * Encode and decode a swap entry.
325 *
326 * Format of swap pte:
327 * bit 0 MBZ
328 * bit 1 page-file (must be zero)
329 * bits 2 - 3 page hw access mode (must be 11: _PAGE_INVALID)
330 * bits 4 - 5 ring protection (must be 01: _PAGE_USER)
331 * bits 6 - 10 swap type (5 bits -> 32 types)
332 * bits 11 - 31 swap offset / PAGE_SIZE (21 bits -> 8GB)
333
334 * Format of file pte:
335 * bit 0 MBZ
336 * bit 1 page-file (must be one: _PAGE_FILE)
337 * bits 2 - 3 page hw access mode (must be 11: _PAGE_INVALID)
338 * bits 4 - 5 ring protection (must be 01: _PAGE_USER)
339 * bits 6 - 31 file offset / PAGE_SIZE
340 */
341
342#define __swp_type(entry) (((entry).val >> 6) & 0x1f)
343#define __swp_offset(entry) ((entry).val >> 11)
344#define __swp_entry(type,offs) \
345 ((swp_entry_t) {((type) << 6) | ((offs) << 11) | _PAGE_INVALID})
346#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
347#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
348
349#define PTE_FILE_MAX_BITS 28
350#define pte_to_pgoff(pte) (pte_val(pte) >> 4)
351#define pgoff_to_pte(off) \
352 ((pte_t) { ((off) << 4) | _PAGE_INVALID | _PAGE_FILE })
353
354#endif /* !defined (__ASSEMBLY__) */
355
356
357#ifdef __ASSEMBLY__
358
359/* Assembly macro _PGD_INDEX is the same as C pgd_index(unsigned long),
360 * _PGD_OFFSET as C pgd_offset(struct mm_struct*, unsigned long),
361 * _PMD_OFFSET as C pmd_offset(pgd_t*, unsigned long)
362 * _PTE_OFFSET as C pte_offset(pmd_t*, unsigned long)
363 *
364 * Note: We require an additional temporary register which can be the same as
365 * the register that holds the address.
366 *
367 * ((pte_t*) ((unsigned long)(pmd_val(*pmd) & PAGE_MASK)) + pte_index(addr))
368 *
369 */
370#define _PGD_INDEX(rt,rs) extui rt, rs, PGDIR_SHIFT, 32-PGDIR_SHIFT
371#define _PTE_INDEX(rt,rs) extui rt, rs, PAGE_SHIFT, PTRS_PER_PTE_SHIFT
372
373#define _PGD_OFFSET(mm,adr,tmp) l32i mm, mm, MM_PGD; \
374 _PGD_INDEX(tmp, adr); \
375 addx4 mm, tmp, mm
376
377#define _PTE_OFFSET(pmd,adr,tmp) _PTE_INDEX(tmp, adr); \
378 srli pmd, pmd, PAGE_SHIFT; \
379 slli pmd, pmd, PAGE_SHIFT; \
380 addx4 pmd, tmp, pmd
381
382#else
383
384extern void paging_init(void);
385
386#define kern_addr_valid(addr) (1)
387
388extern void update_mmu_cache(struct vm_area_struct * vma,
389 unsigned long address, pte_t pte);
390
391/*
392 * remap a physical page `pfn' of size `size' with page protection `prot'
393 * into virtual address `from'
394 */
395
396#define io_remap_pfn_range(vma,from,pfn,size,prot) \
397 remap_pfn_range(vma, from, pfn, size, prot)
398
399
400extern void pgtable_cache_init(void);
401
402typedef pte_t *pte_addr_t;
403
404#endif /* !defined (__ASSEMBLY__) */
405
406#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
407#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
408#define __HAVE_ARCH_PTEP_SET_WRPROTECT
409#define __HAVE_ARCH_PTEP_MKDIRTY
410#define __HAVE_ARCH_PTE_SAME
411
412#include <asm-generic/pgtable.h>
413
414#endif /* _XTENSA_PGTABLE_H */