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Linux kernel mirror (for testing)
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linux
1#ifndef __PXAFB_H__
2#define __PXAFB_H__
3
4/*
5 * linux/drivers/video/pxafb.h
6 * -- Intel PXA250/210 LCD Controller Frame Buffer Device
7 *
8 * Copyright (C) 1999 Eric A. Thomas.
9 * Copyright (C) 2004 Jean-Frederic Clere.
10 * Copyright (C) 2004 Ian Campbell.
11 * Copyright (C) 2004 Jeff Lackey.
12 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
13 * which in turn is
14 * Based on acornfb.c Copyright (C) Russell King.
15 *
16 * 2001-08-03: Cliff Brake <cbrake@acclent.com>
17 * - ported SA1100 code to PXA
18 *
19 * This file is subject to the terms and conditions of the GNU General Public
20 * License. See the file COPYING in the main directory of this archive
21 * for more details.
22 */
23
24/* Shadows for LCD controller registers */
25struct pxafb_lcd_reg {
26 unsigned int lccr0;
27 unsigned int lccr1;
28 unsigned int lccr2;
29 unsigned int lccr3;
30};
31
32/* PXA LCD DMA descriptor */
33struct pxafb_dma_descriptor {
34 unsigned int fdadr;
35 unsigned int fsadr;
36 unsigned int fidr;
37 unsigned int ldcmd;
38};
39
40struct pxafb_info {
41 struct fb_info fb;
42 struct device *dev;
43 struct clk *clk;
44
45 /*
46 * These are the addresses we mapped
47 * the framebuffer memory region to.
48 */
49 /* raw memory addresses */
50 dma_addr_t map_dma; /* physical */
51 u_char * map_cpu; /* virtual */
52 u_int map_size;
53
54 /* addresses of pieces placed in raw buffer */
55 u_char * screen_cpu; /* virtual address of frame buffer */
56 dma_addr_t screen_dma; /* physical address of frame buffer */
57 u16 * palette_cpu; /* virtual address of palette memory */
58 dma_addr_t palette_dma; /* physical address of palette memory */
59 u_int palette_size;
60
61 /* DMA descriptors */
62 struct pxafb_dma_descriptor * dmadesc_fblow_cpu;
63 dma_addr_t dmadesc_fblow_dma;
64 struct pxafb_dma_descriptor * dmadesc_fbhigh_cpu;
65 dma_addr_t dmadesc_fbhigh_dma;
66 struct pxafb_dma_descriptor * dmadesc_palette_cpu;
67 dma_addr_t dmadesc_palette_dma;
68
69 dma_addr_t fdadr0;
70 dma_addr_t fdadr1;
71
72 u_int lccr0;
73 u_int lccr3;
74 u_int lccr4;
75 u_int cmap_inverse:1,
76 cmap_static:1,
77 unused:30;
78
79 u_int reg_lccr0;
80 u_int reg_lccr1;
81 u_int reg_lccr2;
82 u_int reg_lccr3;
83 u_int reg_lccr4;
84
85 unsigned long hsync_time;
86
87 volatile u_char state;
88 volatile u_char task_state;
89 struct semaphore ctrlr_sem;
90 wait_queue_head_t ctrlr_wait;
91 struct work_struct task;
92
93#ifdef CONFIG_CPU_FREQ
94 struct notifier_block freq_transition;
95 struct notifier_block freq_policy;
96#endif
97};
98
99#define TO_INF(ptr,member) container_of(ptr,struct pxafb_info,member)
100
101/*
102 * These are the actions for set_ctrlr_state
103 */
104#define C_DISABLE (0)
105#define C_ENABLE (1)
106#define C_DISABLE_CLKCHANGE (2)
107#define C_ENABLE_CLKCHANGE (3)
108#define C_REENABLE (4)
109#define C_DISABLE_PM (5)
110#define C_ENABLE_PM (6)
111#define C_STARTUP (7)
112
113#define PXA_NAME "PXA"
114
115/*
116 * Minimum X and Y resolutions
117 */
118#define MIN_XRES 64
119#define MIN_YRES 64
120
121#endif /* __PXAFB_H__ */