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at c9a28fa7b9ac19b676deefa0a171ce7df8755c08 265 lines 7.1 kB view raw
1/* 2 * linux/drivers/usb/gadget/pxa2xx_udc.h 3 * Intel PXA2xx on-chip full speed USB device controller 4 * 5 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix 6 * Copyright (C) 2003 David Brownell 7 * 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 */ 23 24#ifndef __LINUX_USB_GADGET_PXA2XX_H 25#define __LINUX_USB_GADGET_PXA2XX_H 26 27#include <linux/types.h> 28 29/*-------------------------------------------------------------------------*/ 30 31/* pxa2xx has this (move to include/asm-arm/arch-pxa/pxa-regs.h) */ 32#define UFNRH_SIR (1 << 7) /* SOF interrupt request */ 33#define UFNRH_SIM (1 << 6) /* SOF interrupt mask */ 34#define UFNRH_IPE14 (1 << 5) /* ISO packet error, ep14 */ 35#define UFNRH_IPE9 (1 << 4) /* ISO packet error, ep9 */ 36#define UFNRH_IPE4 (1 << 3) /* ISO packet error, ep4 */ 37 38/* pxa255 has this (move to include/asm-arm/arch-pxa/pxa-regs.h) */ 39#define UDCCFR UDC_RES2 /* UDC Control Function Register */ 40#define UDCCFR_AREN (1 << 7) /* ACK response enable (now) */ 41#define UDCCFR_ACM (1 << 2) /* ACK control mode (wait for AREN) */ 42 43/* latest pxa255 errata define new "must be one" bits in UDCCFR */ 44#define UDCCFR_MB1 (0xff & ~(UDCCFR_AREN|UDCCFR_ACM)) 45 46/*-------------------------------------------------------------------------*/ 47 48struct pxa2xx_udc; 49 50struct pxa2xx_ep { 51 struct usb_ep ep; 52 struct pxa2xx_udc *dev; 53 54 const struct usb_endpoint_descriptor *desc; 55 struct list_head queue; 56 unsigned long pio_irqs; 57 58 unsigned short fifo_size; 59 u8 bEndpointAddress; 60 u8 bmAttributes; 61 62 unsigned stopped : 1; 63 unsigned dma_fixup : 1; 64 65 /* UDCCS = UDC Control/Status for this EP 66 * UBCR = UDC Byte Count Remaining (contents of OUT fifo) 67 * UDDR = UDC Endpoint Data Register (the fifo) 68 * DRCM = DMA Request Channel Map 69 */ 70 volatile u32 *reg_udccs; 71 volatile u32 *reg_ubcr; 72 volatile u32 *reg_uddr; 73}; 74 75struct pxa2xx_request { 76 struct usb_request req; 77 struct list_head queue; 78}; 79 80enum ep0_state { 81 EP0_IDLE, 82 EP0_IN_DATA_PHASE, 83 EP0_OUT_DATA_PHASE, 84 EP0_END_XFER, 85 EP0_STALL, 86}; 87 88#define EP0_FIFO_SIZE ((unsigned)16) 89#define BULK_FIFO_SIZE ((unsigned)64) 90#define ISO_FIFO_SIZE ((unsigned)256) 91#define INT_FIFO_SIZE ((unsigned)8) 92 93struct udc_stats { 94 struct ep0stats { 95 unsigned long ops; 96 unsigned long bytes; 97 } read, write; 98 unsigned long irqs; 99}; 100 101#ifdef CONFIG_USB_PXA2XX_SMALL 102/* when memory's tight, SMALL config saves code+data. */ 103#define PXA_UDC_NUM_ENDPOINTS 3 104#endif 105 106#ifndef PXA_UDC_NUM_ENDPOINTS 107#define PXA_UDC_NUM_ENDPOINTS 16 108#endif 109 110struct pxa2xx_udc { 111 struct usb_gadget gadget; 112 struct usb_gadget_driver *driver; 113 114 enum ep0_state ep0state; 115 struct udc_stats stats; 116 unsigned got_irq : 1, 117 vbus : 1, 118 pullup : 1, 119 has_cfr : 1, 120 req_pending : 1, 121 req_std : 1, 122 req_config : 1; 123 124#define start_watchdog(dev) mod_timer(&dev->timer, jiffies + (HZ/200)) 125 struct timer_list timer; 126 127 struct device *dev; 128 struct clk *clk; 129 struct pxa2xx_udc_mach_info *mach; 130 u64 dma_mask; 131 struct pxa2xx_ep ep [PXA_UDC_NUM_ENDPOINTS]; 132 133#ifdef CONFIG_USB_GADGET_DEBUG_FS 134 struct dentry *debugfs_udc; 135#endif 136}; 137 138/*-------------------------------------------------------------------------*/ 139 140#ifdef CONFIG_ARCH_LUBBOCK 141#include <asm/arch/lubbock.h> 142/* lubbock can also report usb connect/disconnect irqs */ 143#endif 144 145static struct pxa2xx_udc *the_controller; 146 147/*-------------------------------------------------------------------------*/ 148 149/* 150 * Debugging support vanishes in non-debug builds. DBG_NORMAL should be 151 * mostly silent during normal use/testing, with no timing side-effects. 152 */ 153#define DBG_NORMAL 1 /* error paths, device state transitions */ 154#define DBG_VERBOSE 2 /* add some success path trace info */ 155#define DBG_NOISY 3 /* ... even more: request level */ 156#define DBG_VERY_NOISY 4 /* ... even more: packet level */ 157 158#define DMSG(stuff...) pr_debug("udc: " stuff) 159 160#ifdef DEBUG 161 162static int is_vbus_present(void); 163 164static const char *state_name[] = { 165 "EP0_IDLE", 166 "EP0_IN_DATA_PHASE", "EP0_OUT_DATA_PHASE", 167 "EP0_END_XFER", "EP0_STALL" 168}; 169 170#ifdef VERBOSE_DEBUG 171# define UDC_DEBUG DBG_VERBOSE 172#else 173# define UDC_DEBUG DBG_NORMAL 174#endif 175 176static void __maybe_unused 177dump_udccr(const char *label) 178{ 179 u32 udccr = UDCCR; 180 DMSG("%s %02X =%s%s%s%s%s%s%s%s\n", 181 label, udccr, 182 (udccr & UDCCR_REM) ? " rem" : "", 183 (udccr & UDCCR_RSTIR) ? " rstir" : "", 184 (udccr & UDCCR_SRM) ? " srm" : "", 185 (udccr & UDCCR_SUSIR) ? " susir" : "", 186 (udccr & UDCCR_RESIR) ? " resir" : "", 187 (udccr & UDCCR_RSM) ? " rsm" : "", 188 (udccr & UDCCR_UDA) ? " uda" : "", 189 (udccr & UDCCR_UDE) ? " ude" : ""); 190} 191 192static void __maybe_unused 193dump_udccs0(const char *label) 194{ 195 u32 udccs0 = UDCCS0; 196 197 DMSG("%s %s %02X =%s%s%s%s%s%s%s%s\n", 198 label, state_name[the_controller->ep0state], udccs0, 199 (udccs0 & UDCCS0_SA) ? " sa" : "", 200 (udccs0 & UDCCS0_RNE) ? " rne" : "", 201 (udccs0 & UDCCS0_FST) ? " fst" : "", 202 (udccs0 & UDCCS0_SST) ? " sst" : "", 203 (udccs0 & UDCCS0_DRWF) ? " dwrf" : "", 204 (udccs0 & UDCCS0_FTF) ? " ftf" : "", 205 (udccs0 & UDCCS0_IPR) ? " ipr" : "", 206 (udccs0 & UDCCS0_OPR) ? " opr" : ""); 207} 208 209static void __maybe_unused 210dump_state(struct pxa2xx_udc *dev) 211{ 212 u32 tmp; 213 unsigned i; 214 215 DMSG("%s %s, uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n", 216 is_vbus_present() ? "host " : "disconnected", 217 state_name[dev->ep0state], 218 UICR1, UICR0, USIR1, USIR0, UFNRH, UFNRL); 219 dump_udccr("udccr"); 220 if (dev->has_cfr) { 221 tmp = UDCCFR; 222 DMSG("udccfr %02X =%s%s\n", tmp, 223 (tmp & UDCCFR_AREN) ? " aren" : "", 224 (tmp & UDCCFR_ACM) ? " acm" : ""); 225 } 226 227 if (!dev->driver) { 228 DMSG("no gadget driver bound\n"); 229 return; 230 } else 231 DMSG("ep0 driver '%s'\n", dev->driver->driver.name); 232 233 if (!is_vbus_present()) 234 return; 235 236 dump_udccs0 ("udccs0"); 237 DMSG("ep0 IN %lu/%lu, OUT %lu/%lu\n", 238 dev->stats.write.bytes, dev->stats.write.ops, 239 dev->stats.read.bytes, dev->stats.read.ops); 240 241 for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) { 242 if (dev->ep [i].desc == NULL) 243 continue; 244 DMSG ("udccs%d = %02x\n", i, *dev->ep->reg_udccs); 245 } 246} 247 248#else 249 250#define dump_udccr(x) do{}while(0) 251#define dump_udccs0(x) do{}while(0) 252#define dump_state(x) do{}while(0) 253 254#define UDC_DEBUG ((unsigned)0) 255 256#endif 257 258#define DBG(lvl, stuff...) do{if ((lvl) <= UDC_DEBUG) DMSG(stuff);}while(0) 259 260#define ERR(stuff...) pr_err("udc: " stuff) 261#define WARN(stuff...) pr_warning("udc: " stuff) 262#define INFO(stuff...) pr_info("udc: " stuff) 263 264 265#endif /* __LINUX_USB_GADGET_PXA2XX_H */