tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*------------------------------------------------------------------------
2 . smc911x.h - macros for SMSC's LAN911{5,6,7,8} single-chip Ethernet device.
3 .
4 . Copyright (C) 2005 Sensoria Corp.
5 . Derived from the unified SMC91x driver by Nicolas Pitre
6 .
7 . This program is free software; you can redistribute it and/or modify
8 . it under the terms of the GNU General Public License as published by
9 . the Free Software Foundation; either version 2 of the License, or
10 . (at your option) any later version.
11 .
12 . This program is distributed in the hope that it will be useful,
13 . but WITHOUT ANY WARRANTY; without even the implied warranty of
14 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 . GNU General Public License for more details.
16 .
17 . You should have received a copy of the GNU General Public License
18 . along with this program; if not, write to the Free Software
19 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 .
21 . Information contained in this file was obtained from the LAN9118
22 . manual from SMC. To get a copy, if you really want one, you can find
23 . information under www.smsc.com.
24 .
25 . Authors
26 . Dustin McIntire <dustin@sensoria.com>
27 .
28 ---------------------------------------------------------------------------*/
29#ifndef _SMC911X_H_
30#define _SMC911X_H_
31
32/*
33 * Use the DMA feature on PXA chips
34 */
35#ifdef CONFIG_ARCH_PXA
36 #define SMC_USE_PXA_DMA 1
37 #define SMC_USE_16BIT 0
38 #define SMC_USE_32BIT 1
39 #define SMC_IRQ_SENSE IRQF_TRIGGER_FALLING
40#elif defined(CONFIG_SH_MAGIC_PANEL_R2)
41 #define SMC_USE_SH_DMA 0
42 #define SMC_USE_16BIT 0
43 #define SMC_USE_32BIT 1
44 #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
45#endif
46
47
48/*
49 * Define the bus width specific IO macros
50 */
51
52#if SMC_USE_16BIT
53#define SMC_inb(a, r) readb((a) + (r))
54#define SMC_inw(a, r) readw((a) + (r))
55#define SMC_inl(a, r) ((SMC_inw(a, r) & 0xFFFF)+(SMC_inw(a+2, r)<<16))
56#define SMC_outb(v, a, r) writeb(v, (a) + (r))
57#define SMC_outw(v, a, r) writew(v, (a) + (r))
58#define SMC_outl(v, a, r) \
59 do{ \
60 writel(v & 0xFFFF, (a) + (r)); \
61 writel(v >> 16, (a) + (r) + 2); \
62 } while (0)
63#define SMC_insl(a, r, p, l) readsw((short*)((a) + (r)), p, l*2)
64#define SMC_outsl(a, r, p, l) writesw((short*)((a) + (r)), p, l*2)
65
66#elif SMC_USE_32BIT
67#define SMC_inb(a, r) readb((a) + (r))
68#define SMC_inw(a, r) readw((a) + (r))
69#define SMC_inl(a, r) readl((a) + (r))
70#define SMC_outb(v, a, r) writeb(v, (a) + (r))
71#define SMC_outl(v, a, r) writel(v, (a) + (r))
72#define SMC_insl(a, r, p, l) readsl((int*)((a) + (r)), p, l)
73#define SMC_outsl(a, r, p, l) writesl((int*)((a) + (r)), p, l)
74
75#endif /* SMC_USE_16BIT */
76
77
78
79#ifdef SMC_USE_PXA_DMA
80#define SMC_USE_DMA
81
82/*
83 * Define the request and free functions
84 * These are unfortunately architecture specific as no generic allocation
85 * mechanism exits
86 */
87#define SMC_DMA_REQUEST(dev, handler) \
88 pxa_request_dma(dev->name, DMA_PRIO_LOW, handler, dev)
89
90#define SMC_DMA_FREE(dev, dma) \
91 pxa_free_dma(dma)
92
93#define SMC_DMA_ACK_IRQ(dev, dma) \
94{ \
95 if (DCSR(dma) & DCSR_BUSERR) { \
96 printk("%s: DMA %d bus error!\n", dev->name, dma); \
97 } \
98 DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; \
99}
100
101/*
102 * Use a DMA for RX and TX packets.
103 */
104#include <linux/dma-mapping.h>
105#include <asm/dma.h>
106#include <asm/arch/pxa-regs.h>
107
108static dma_addr_t rx_dmabuf, tx_dmabuf;
109static int rx_dmalen, tx_dmalen;
110
111#ifdef SMC_insl
112#undef SMC_insl
113#define SMC_insl(a, r, p, l) \
114 smc_pxa_dma_insl(lp->dev, a, lp->physaddr, r, lp->rxdma, p, l)
115
116static inline void
117smc_pxa_dma_insl(struct device *dev, u_long ioaddr, u_long physaddr,
118 int reg, int dma, u_char *buf, int len)
119{
120 /* 64 bit alignment is required for memory to memory DMA */
121 if ((long)buf & 4) {
122 *((u32 *)buf) = SMC_inl(ioaddr, reg);
123 buf += 4;
124 len--;
125 }
126
127 len *= 4;
128 rx_dmabuf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE);
129 rx_dmalen = len;
130 DCSR(dma) = DCSR_NODESC;
131 DTADR(dma) = rx_dmabuf;
132 DSADR(dma) = physaddr + reg;
133 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
134 DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & rx_dmalen));
135 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
136}
137#endif
138
139#ifdef SMC_insw
140#undef SMC_insw
141#define SMC_insw(a, r, p, l) \
142 smc_pxa_dma_insw(lp->dev, a, lp->physaddr, r, lp->rxdma, p, l)
143
144static inline void
145smc_pxa_dma_insw(struct device *dev, u_long ioaddr, u_long physaddr,
146 int reg, int dma, u_char *buf, int len)
147{
148 /* 64 bit alignment is required for memory to memory DMA */
149 while ((long)buf & 6) {
150 *((u16 *)buf) = SMC_inw(ioaddr, reg);
151 buf += 2;
152 len--;
153 }
154
155 len *= 2;
156 rx_dmabuf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE);
157 rx_dmalen = len;
158 DCSR(dma) = DCSR_NODESC;
159 DTADR(dma) = rx_dmabuf;
160 DSADR(dma) = physaddr + reg;
161 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
162 DCMD_WIDTH2 | DCMD_ENDIRQEN | (DCMD_LENGTH & rx_dmalen));
163 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
164}
165#endif
166
167#ifdef SMC_outsl
168#undef SMC_outsl
169#define SMC_outsl(a, r, p, l) \
170 smc_pxa_dma_outsl(lp->dev, a, lp->physaddr, r, lp->txdma, p, l)
171
172static inline void
173smc_pxa_dma_outsl(struct device *dev, u_long ioaddr, u_long physaddr,
174 int reg, int dma, u_char *buf, int len)
175{
176 /* 64 bit alignment is required for memory to memory DMA */
177 if ((long)buf & 4) {
178 SMC_outl(*((u32 *)buf), ioaddr, reg);
179 buf += 4;
180 len--;
181 }
182
183 len *= 4;
184 tx_dmabuf = dma_map_single(dev, buf, len, DMA_TO_DEVICE);
185 tx_dmalen = len;
186 DCSR(dma) = DCSR_NODESC;
187 DSADR(dma) = tx_dmabuf;
188 DTADR(dma) = physaddr + reg;
189 DCMD(dma) = (DCMD_INCSRCADDR | DCMD_BURST32 |
190 DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & tx_dmalen));
191 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
192}
193#endif
194
195#ifdef SMC_outsw
196#undef SMC_outsw
197#define SMC_outsw(a, r, p, l) \
198 smc_pxa_dma_outsw(lp->dev, a, lp->physaddr, r, lp->txdma, p, l)
199
200static inline void
201smc_pxa_dma_outsw(struct device *dev, u_long ioaddr, u_long physaddr,
202 int reg, int dma, u_char *buf, int len)
203{
204 /* 64 bit alignment is required for memory to memory DMA */
205 while ((long)buf & 6) {
206 SMC_outw(*((u16 *)buf), ioaddr, reg);
207 buf += 2;
208 len--;
209 }
210
211 len *= 2;
212 tx_dmabuf = dma_map_single(dev, buf, len, DMA_TO_DEVICE);
213 tx_dmalen = len;
214 DCSR(dma) = DCSR_NODESC;
215 DSADR(dma) = tx_dmabuf;
216 DTADR(dma) = physaddr + reg;
217 DCMD(dma) = (DCMD_INCSRCADDR | DCMD_BURST32 |
218 DCMD_WIDTH2 | DCMD_ENDIRQEN | (DCMD_LENGTH & tx_dmalen));
219 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
220}
221#endif
222
223#endif /* SMC_USE_PXA_DMA */
224
225
226/* Chip Parameters and Register Definitions */
227
228#define SMC911X_TX_FIFO_LOW_THRESHOLD (1536*2)
229
230#define SMC911X_IO_EXTENT 0x100
231
232#define SMC911X_EEPROM_LEN 7
233
234/* Below are the register offsets and bit definitions
235 * of the Lan911x memory space
236 */
237#define RX_DATA_FIFO (0x00)
238
239#define TX_DATA_FIFO (0x20)
240#define TX_CMD_A_INT_ON_COMP_ (0x80000000)
241#define TX_CMD_A_INT_BUF_END_ALGN_ (0x03000000)
242#define TX_CMD_A_INT_4_BYTE_ALGN_ (0x00000000)
243#define TX_CMD_A_INT_16_BYTE_ALGN_ (0x01000000)
244#define TX_CMD_A_INT_32_BYTE_ALGN_ (0x02000000)
245#define TX_CMD_A_INT_DATA_OFFSET_ (0x001F0000)
246#define TX_CMD_A_INT_FIRST_SEG_ (0x00002000)
247#define TX_CMD_A_INT_LAST_SEG_ (0x00001000)
248#define TX_CMD_A_BUF_SIZE_ (0x000007FF)
249#define TX_CMD_B_PKT_TAG_ (0xFFFF0000)
250#define TX_CMD_B_ADD_CRC_DISABLE_ (0x00002000)
251#define TX_CMD_B_DISABLE_PADDING_ (0x00001000)
252#define TX_CMD_B_PKT_BYTE_LENGTH_ (0x000007FF)
253
254#define RX_STATUS_FIFO (0x40)
255#define RX_STS_PKT_LEN_ (0x3FFF0000)
256#define RX_STS_ES_ (0x00008000)
257#define RX_STS_BCST_ (0x00002000)
258#define RX_STS_LEN_ERR_ (0x00001000)
259#define RX_STS_RUNT_ERR_ (0x00000800)
260#define RX_STS_MCAST_ (0x00000400)
261#define RX_STS_TOO_LONG_ (0x00000080)
262#define RX_STS_COLL_ (0x00000040)
263#define RX_STS_ETH_TYPE_ (0x00000020)
264#define RX_STS_WDOG_TMT_ (0x00000010)
265#define RX_STS_MII_ERR_ (0x00000008)
266#define RX_STS_DRIBBLING_ (0x00000004)
267#define RX_STS_CRC_ERR_ (0x00000002)
268#define RX_STATUS_FIFO_PEEK (0x44)
269#define TX_STATUS_FIFO (0x48)
270#define TX_STS_TAG_ (0xFFFF0000)
271#define TX_STS_ES_ (0x00008000)
272#define TX_STS_LOC_ (0x00000800)
273#define TX_STS_NO_CARR_ (0x00000400)
274#define TX_STS_LATE_COLL_ (0x00000200)
275#define TX_STS_MANY_COLL_ (0x00000100)
276#define TX_STS_COLL_CNT_ (0x00000078)
277#define TX_STS_MANY_DEFER_ (0x00000004)
278#define TX_STS_UNDERRUN_ (0x00000002)
279#define TX_STS_DEFERRED_ (0x00000001)
280#define TX_STATUS_FIFO_PEEK (0x4C)
281#define ID_REV (0x50)
282#define ID_REV_CHIP_ID_ (0xFFFF0000) /* RO */
283#define ID_REV_REV_ID_ (0x0000FFFF) /* RO */
284
285#define INT_CFG (0x54)
286#define INT_CFG_INT_DEAS_ (0xFF000000) /* R/W */
287#define INT_CFG_INT_DEAS_CLR_ (0x00004000)
288#define INT_CFG_INT_DEAS_STS_ (0x00002000)
289#define INT_CFG_IRQ_INT_ (0x00001000) /* RO */
290#define INT_CFG_IRQ_EN_ (0x00000100) /* R/W */
291#define INT_CFG_IRQ_POL_ (0x00000010) /* R/W Not Affected by SW Reset */
292#define INT_CFG_IRQ_TYPE_ (0x00000001) /* R/W Not Affected by SW Reset */
293
294#define INT_STS (0x58)
295#define INT_STS_SW_INT_ (0x80000000) /* R/WC */
296#define INT_STS_TXSTOP_INT_ (0x02000000) /* R/WC */
297#define INT_STS_RXSTOP_INT_ (0x01000000) /* R/WC */
298#define INT_STS_RXDFH_INT_ (0x00800000) /* R/WC */
299#define INT_STS_RXDF_INT_ (0x00400000) /* R/WC */
300#define INT_STS_TX_IOC_ (0x00200000) /* R/WC */
301#define INT_STS_RXD_INT_ (0x00100000) /* R/WC */
302#define INT_STS_GPT_INT_ (0x00080000) /* R/WC */
303#define INT_STS_PHY_INT_ (0x00040000) /* RO */
304#define INT_STS_PME_INT_ (0x00020000) /* R/WC */
305#define INT_STS_TXSO_ (0x00010000) /* R/WC */
306#define INT_STS_RWT_ (0x00008000) /* R/WC */
307#define INT_STS_RXE_ (0x00004000) /* R/WC */
308#define INT_STS_TXE_ (0x00002000) /* R/WC */
309//#define INT_STS_ERX_ (0x00001000) /* R/WC */
310#define INT_STS_TDFU_ (0x00000800) /* R/WC */
311#define INT_STS_TDFO_ (0x00000400) /* R/WC */
312#define INT_STS_TDFA_ (0x00000200) /* R/WC */
313#define INT_STS_TSFF_ (0x00000100) /* R/WC */
314#define INT_STS_TSFL_ (0x00000080) /* R/WC */
315//#define INT_STS_RXDF_ (0x00000040) /* R/WC */
316#define INT_STS_RDFO_ (0x00000040) /* R/WC */
317#define INT_STS_RDFL_ (0x00000020) /* R/WC */
318#define INT_STS_RSFF_ (0x00000010) /* R/WC */
319#define INT_STS_RSFL_ (0x00000008) /* R/WC */
320#define INT_STS_GPIO2_INT_ (0x00000004) /* R/WC */
321#define INT_STS_GPIO1_INT_ (0x00000002) /* R/WC */
322#define INT_STS_GPIO0_INT_ (0x00000001) /* R/WC */
323
324#define INT_EN (0x5C)
325#define INT_EN_SW_INT_EN_ (0x80000000) /* R/W */
326#define INT_EN_TXSTOP_INT_EN_ (0x02000000) /* R/W */
327#define INT_EN_RXSTOP_INT_EN_ (0x01000000) /* R/W */
328#define INT_EN_RXDFH_INT_EN_ (0x00800000) /* R/W */
329//#define INT_EN_RXDF_INT_EN_ (0x00400000) /* R/W */
330#define INT_EN_TIOC_INT_EN_ (0x00200000) /* R/W */
331#define INT_EN_RXD_INT_EN_ (0x00100000) /* R/W */
332#define INT_EN_GPT_INT_EN_ (0x00080000) /* R/W */
333#define INT_EN_PHY_INT_EN_ (0x00040000) /* R/W */
334#define INT_EN_PME_INT_EN_ (0x00020000) /* R/W */
335#define INT_EN_TXSO_EN_ (0x00010000) /* R/W */
336#define INT_EN_RWT_EN_ (0x00008000) /* R/W */
337#define INT_EN_RXE_EN_ (0x00004000) /* R/W */
338#define INT_EN_TXE_EN_ (0x00002000) /* R/W */
339//#define INT_EN_ERX_EN_ (0x00001000) /* R/W */
340#define INT_EN_TDFU_EN_ (0x00000800) /* R/W */
341#define INT_EN_TDFO_EN_ (0x00000400) /* R/W */
342#define INT_EN_TDFA_EN_ (0x00000200) /* R/W */
343#define INT_EN_TSFF_EN_ (0x00000100) /* R/W */
344#define INT_EN_TSFL_EN_ (0x00000080) /* R/W */
345//#define INT_EN_RXDF_EN_ (0x00000040) /* R/W */
346#define INT_EN_RDFO_EN_ (0x00000040) /* R/W */
347#define INT_EN_RDFL_EN_ (0x00000020) /* R/W */
348#define INT_EN_RSFF_EN_ (0x00000010) /* R/W */
349#define INT_EN_RSFL_EN_ (0x00000008) /* R/W */
350#define INT_EN_GPIO2_INT_ (0x00000004) /* R/W */
351#define INT_EN_GPIO1_INT_ (0x00000002) /* R/W */
352#define INT_EN_GPIO0_INT_ (0x00000001) /* R/W */
353
354#define BYTE_TEST (0x64)
355#define FIFO_INT (0x68)
356#define FIFO_INT_TX_AVAIL_LEVEL_ (0xFF000000) /* R/W */
357#define FIFO_INT_TX_STS_LEVEL_ (0x00FF0000) /* R/W */
358#define FIFO_INT_RX_AVAIL_LEVEL_ (0x0000FF00) /* R/W */
359#define FIFO_INT_RX_STS_LEVEL_ (0x000000FF) /* R/W */
360
361#define RX_CFG (0x6C)
362#define RX_CFG_RX_END_ALGN_ (0xC0000000) /* R/W */
363#define RX_CFG_RX_END_ALGN4_ (0x00000000) /* R/W */
364#define RX_CFG_RX_END_ALGN16_ (0x40000000) /* R/W */
365#define RX_CFG_RX_END_ALGN32_ (0x80000000) /* R/W */
366#define RX_CFG_RX_DMA_CNT_ (0x0FFF0000) /* R/W */
367#define RX_CFG_RX_DUMP_ (0x00008000) /* R/W */
368#define RX_CFG_RXDOFF_ (0x00001F00) /* R/W */
369//#define RX_CFG_RXBAD_ (0x00000001) /* R/W */
370
371#define TX_CFG (0x70)
372//#define TX_CFG_TX_DMA_LVL_ (0xE0000000) /* R/W */
373//#define TX_CFG_TX_DMA_CNT_ (0x0FFF0000) /* R/W Self Clearing */
374#define TX_CFG_TXS_DUMP_ (0x00008000) /* Self Clearing */
375#define TX_CFG_TXD_DUMP_ (0x00004000) /* Self Clearing */
376#define TX_CFG_TXSAO_ (0x00000004) /* R/W */
377#define TX_CFG_TX_ON_ (0x00000002) /* R/W */
378#define TX_CFG_STOP_TX_ (0x00000001) /* Self Clearing */
379
380#define HW_CFG (0x74)
381#define HW_CFG_TTM_ (0x00200000) /* R/W */
382#define HW_CFG_SF_ (0x00100000) /* R/W */
383#define HW_CFG_TX_FIF_SZ_ (0x000F0000) /* R/W */
384#define HW_CFG_TR_ (0x00003000) /* R/W */
385#define HW_CFG_PHY_CLK_SEL_ (0x00000060) /* R/W */
386#define HW_CFG_PHY_CLK_SEL_INT_PHY_ (0x00000000) /* R/W */
387#define HW_CFG_PHY_CLK_SEL_EXT_PHY_ (0x00000020) /* R/W */
388#define HW_CFG_PHY_CLK_SEL_CLK_DIS_ (0x00000040) /* R/W */
389#define HW_CFG_SMI_SEL_ (0x00000010) /* R/W */
390#define HW_CFG_EXT_PHY_DET_ (0x00000008) /* RO */
391#define HW_CFG_EXT_PHY_EN_ (0x00000004) /* R/W */
392#define HW_CFG_32_16_BIT_MODE_ (0x00000004) /* RO */
393#define HW_CFG_SRST_TO_ (0x00000002) /* RO */
394#define HW_CFG_SRST_ (0x00000001) /* Self Clearing */
395
396#define RX_DP_CTRL (0x78)
397#define RX_DP_CTRL_RX_FFWD_ (0x80000000) /* R/W */
398#define RX_DP_CTRL_FFWD_BUSY_ (0x80000000) /* RO */
399
400#define RX_FIFO_INF (0x7C)
401#define RX_FIFO_INF_RXSUSED_ (0x00FF0000) /* RO */
402#define RX_FIFO_INF_RXDUSED_ (0x0000FFFF) /* RO */
403
404#define TX_FIFO_INF (0x80)
405#define TX_FIFO_INF_TSUSED_ (0x00FF0000) /* RO */
406#define TX_FIFO_INF_TDFREE_ (0x0000FFFF) /* RO */
407
408#define PMT_CTRL (0x84)
409#define PMT_CTRL_PM_MODE_ (0x00003000) /* Self Clearing */
410#define PMT_CTRL_PHY_RST_ (0x00000400) /* Self Clearing */
411#define PMT_CTRL_WOL_EN_ (0x00000200) /* R/W */
412#define PMT_CTRL_ED_EN_ (0x00000100) /* R/W */
413#define PMT_CTRL_PME_TYPE_ (0x00000040) /* R/W Not Affected by SW Reset */
414#define PMT_CTRL_WUPS_ (0x00000030) /* R/WC */
415#define PMT_CTRL_WUPS_NOWAKE_ (0x00000000) /* R/WC */
416#define PMT_CTRL_WUPS_ED_ (0x00000010) /* R/WC */
417#define PMT_CTRL_WUPS_WOL_ (0x00000020) /* R/WC */
418#define PMT_CTRL_WUPS_MULTI_ (0x00000030) /* R/WC */
419#define PMT_CTRL_PME_IND_ (0x00000008) /* R/W */
420#define PMT_CTRL_PME_POL_ (0x00000004) /* R/W */
421#define PMT_CTRL_PME_EN_ (0x00000002) /* R/W Not Affected by SW Reset */
422#define PMT_CTRL_READY_ (0x00000001) /* RO */
423
424#define GPIO_CFG (0x88)
425#define GPIO_CFG_LED3_EN_ (0x40000000) /* R/W */
426#define GPIO_CFG_LED2_EN_ (0x20000000) /* R/W */
427#define GPIO_CFG_LED1_EN_ (0x10000000) /* R/W */
428#define GPIO_CFG_GPIO2_INT_POL_ (0x04000000) /* R/W */
429#define GPIO_CFG_GPIO1_INT_POL_ (0x02000000) /* R/W */
430#define GPIO_CFG_GPIO0_INT_POL_ (0x01000000) /* R/W */
431#define GPIO_CFG_EEPR_EN_ (0x00700000) /* R/W */
432#define GPIO_CFG_GPIOBUF2_ (0x00040000) /* R/W */
433#define GPIO_CFG_GPIOBUF1_ (0x00020000) /* R/W */
434#define GPIO_CFG_GPIOBUF0_ (0x00010000) /* R/W */
435#define GPIO_CFG_GPIODIR2_ (0x00000400) /* R/W */
436#define GPIO_CFG_GPIODIR1_ (0x00000200) /* R/W */
437#define GPIO_CFG_GPIODIR0_ (0x00000100) /* R/W */
438#define GPIO_CFG_GPIOD4_ (0x00000010) /* R/W */
439#define GPIO_CFG_GPIOD3_ (0x00000008) /* R/W */
440#define GPIO_CFG_GPIOD2_ (0x00000004) /* R/W */
441#define GPIO_CFG_GPIOD1_ (0x00000002) /* R/W */
442#define GPIO_CFG_GPIOD0_ (0x00000001) /* R/W */
443
444#define GPT_CFG (0x8C)
445#define GPT_CFG_TIMER_EN_ (0x20000000) /* R/W */
446#define GPT_CFG_GPT_LOAD_ (0x0000FFFF) /* R/W */
447
448#define GPT_CNT (0x90)
449#define GPT_CNT_GPT_CNT_ (0x0000FFFF) /* RO */
450
451#define ENDIAN (0x98)
452#define FREE_RUN (0x9C)
453#define RX_DROP (0xA0)
454#define MAC_CSR_CMD (0xA4)
455#define MAC_CSR_CMD_CSR_BUSY_ (0x80000000) /* Self Clearing */
456#define MAC_CSR_CMD_R_NOT_W_ (0x40000000) /* R/W */
457#define MAC_CSR_CMD_CSR_ADDR_ (0x000000FF) /* R/W */
458
459#define MAC_CSR_DATA (0xA8)
460#define AFC_CFG (0xAC)
461#define AFC_CFG_AFC_HI_ (0x00FF0000) /* R/W */
462#define AFC_CFG_AFC_LO_ (0x0000FF00) /* R/W */
463#define AFC_CFG_BACK_DUR_ (0x000000F0) /* R/W */
464#define AFC_CFG_FCMULT_ (0x00000008) /* R/W */
465#define AFC_CFG_FCBRD_ (0x00000004) /* R/W */
466#define AFC_CFG_FCADD_ (0x00000002) /* R/W */
467#define AFC_CFG_FCANY_ (0x00000001) /* R/W */
468
469#define E2P_CMD (0xB0)
470#define E2P_CMD_EPC_BUSY_ (0x80000000) /* Self Clearing */
471#define E2P_CMD_EPC_CMD_ (0x70000000) /* R/W */
472#define E2P_CMD_EPC_CMD_READ_ (0x00000000) /* R/W */
473#define E2P_CMD_EPC_CMD_EWDS_ (0x10000000) /* R/W */
474#define E2P_CMD_EPC_CMD_EWEN_ (0x20000000) /* R/W */
475#define E2P_CMD_EPC_CMD_WRITE_ (0x30000000) /* R/W */
476#define E2P_CMD_EPC_CMD_WRAL_ (0x40000000) /* R/W */
477#define E2P_CMD_EPC_CMD_ERASE_ (0x50000000) /* R/W */
478#define E2P_CMD_EPC_CMD_ERAL_ (0x60000000) /* R/W */
479#define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000) /* R/W */
480#define E2P_CMD_EPC_TIMEOUT_ (0x00000200) /* RO */
481#define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100) /* RO */
482#define E2P_CMD_EPC_ADDR_ (0x000000FF) /* R/W */
483
484#define E2P_DATA (0xB4)
485#define E2P_DATA_EEPROM_DATA_ (0x000000FF) /* R/W */
486/* end of LAN register offsets and bit definitions */
487
488/*
489 ****************************************************************************
490 ****************************************************************************
491 * MAC Control and Status Register (Indirect Address)
492 * Offset (through the MAC_CSR CMD and DATA port)
493 ****************************************************************************
494 ****************************************************************************
495 *
496 */
497#define MAC_CR (0x01) /* R/W */
498
499/* MAC_CR - MAC Control Register */
500#define MAC_CR_RXALL_ (0x80000000)
501// TODO: delete this bit? It is not described in the data sheet.
502#define MAC_CR_HBDIS_ (0x10000000)
503#define MAC_CR_RCVOWN_ (0x00800000)
504#define MAC_CR_LOOPBK_ (0x00200000)
505#define MAC_CR_FDPX_ (0x00100000)
506#define MAC_CR_MCPAS_ (0x00080000)
507#define MAC_CR_PRMS_ (0x00040000)
508#define MAC_CR_INVFILT_ (0x00020000)
509#define MAC_CR_PASSBAD_ (0x00010000)
510#define MAC_CR_HFILT_ (0x00008000)
511#define MAC_CR_HPFILT_ (0x00002000)
512#define MAC_CR_LCOLL_ (0x00001000)
513#define MAC_CR_BCAST_ (0x00000800)
514#define MAC_CR_DISRTY_ (0x00000400)
515#define MAC_CR_PADSTR_ (0x00000100)
516#define MAC_CR_BOLMT_MASK_ (0x000000C0)
517#define MAC_CR_DFCHK_ (0x00000020)
518#define MAC_CR_TXEN_ (0x00000008)
519#define MAC_CR_RXEN_ (0x00000004)
520
521#define ADDRH (0x02) /* R/W mask 0x0000FFFFUL */
522#define ADDRL (0x03) /* R/W mask 0xFFFFFFFFUL */
523#define HASHH (0x04) /* R/W */
524#define HASHL (0x05) /* R/W */
525
526#define MII_ACC (0x06) /* R/W */
527#define MII_ACC_PHY_ADDR_ (0x0000F800)
528#define MII_ACC_MIIRINDA_ (0x000007C0)
529#define MII_ACC_MII_WRITE_ (0x00000002)
530#define MII_ACC_MII_BUSY_ (0x00000001)
531
532#define MII_DATA (0x07) /* R/W mask 0x0000FFFFUL */
533
534#define FLOW (0x08) /* R/W */
535#define FLOW_FCPT_ (0xFFFF0000)
536#define FLOW_FCPASS_ (0x00000004)
537#define FLOW_FCEN_ (0x00000002)
538#define FLOW_FCBSY_ (0x00000001)
539
540#define VLAN1 (0x09) /* R/W mask 0x0000FFFFUL */
541#define VLAN1_VTI1_ (0x0000ffff)
542
543#define VLAN2 (0x0A) /* R/W mask 0x0000FFFFUL */
544#define VLAN2_VTI2_ (0x0000ffff)
545
546#define WUFF (0x0B) /* WO */
547
548#define WUCSR (0x0C) /* R/W */
549#define WUCSR_GUE_ (0x00000200)
550#define WUCSR_WUFR_ (0x00000040)
551#define WUCSR_MPR_ (0x00000020)
552#define WUCSR_WAKE_EN_ (0x00000004)
553#define WUCSR_MPEN_ (0x00000002)
554
555/*
556 ****************************************************************************
557 * Chip Specific MII Defines
558 ****************************************************************************
559 *
560 * Phy register offsets and bit definitions
561 *
562 */
563
564#define PHY_MODE_CTRL_STS ((u32)17) /* Mode Control/Status Register */
565//#define MODE_CTRL_STS_FASTRIP_ ((u16)0x4000)
566#define MODE_CTRL_STS_EDPWRDOWN_ ((u16)0x2000)
567//#define MODE_CTRL_STS_LOWSQEN_ ((u16)0x0800)
568//#define MODE_CTRL_STS_MDPREBP_ ((u16)0x0400)
569//#define MODE_CTRL_STS_FARLOOPBACK_ ((u16)0x0200)
570//#define MODE_CTRL_STS_FASTEST_ ((u16)0x0100)
571//#define MODE_CTRL_STS_REFCLKEN_ ((u16)0x0010)
572//#define MODE_CTRL_STS_PHYADBP_ ((u16)0x0008)
573//#define MODE_CTRL_STS_FORCE_G_LINK_ ((u16)0x0004)
574#define MODE_CTRL_STS_ENERGYON_ ((u16)0x0002)
575
576#define PHY_INT_SRC ((u32)29)
577#define PHY_INT_SRC_ENERGY_ON_ ((u16)0x0080)
578#define PHY_INT_SRC_ANEG_COMP_ ((u16)0x0040)
579#define PHY_INT_SRC_REMOTE_FAULT_ ((u16)0x0020)
580#define PHY_INT_SRC_LINK_DOWN_ ((u16)0x0010)
581#define PHY_INT_SRC_ANEG_LP_ACK_ ((u16)0x0008)
582#define PHY_INT_SRC_PAR_DET_FAULT_ ((u16)0x0004)
583#define PHY_INT_SRC_ANEG_PGRX_ ((u16)0x0002)
584
585#define PHY_INT_MASK ((u32)30)
586#define PHY_INT_MASK_ENERGY_ON_ ((u16)0x0080)
587#define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
588#define PHY_INT_MASK_REMOTE_FAULT_ ((u16)0x0020)
589#define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
590#define PHY_INT_MASK_ANEG_LP_ACK_ ((u16)0x0008)
591#define PHY_INT_MASK_PAR_DET_FAULT_ ((u16)0x0004)
592#define PHY_INT_MASK_ANEG_PGRX_ ((u16)0x0002)
593
594#define PHY_SPECIAL ((u32)31)
595#define PHY_SPECIAL_ANEG_DONE_ ((u16)0x1000)
596#define PHY_SPECIAL_RES_ ((u16)0x0040)
597#define PHY_SPECIAL_RES_MASK_ ((u16)0x0FE1)
598#define PHY_SPECIAL_SPD_ ((u16)0x001C)
599#define PHY_SPECIAL_SPD_10HALF_ ((u16)0x0004)
600#define PHY_SPECIAL_SPD_10FULL_ ((u16)0x0014)
601#define PHY_SPECIAL_SPD_100HALF_ ((u16)0x0008)
602#define PHY_SPECIAL_SPD_100FULL_ ((u16)0x0018)
603
604#define LAN911X_INTERNAL_PHY_ID (0x0007C000)
605
606/* Chip ID values */
607#define CHIP_9115 0x115
608#define CHIP_9116 0x116
609#define CHIP_9117 0x117
610#define CHIP_9118 0x118
611
612struct chip_id {
613 u16 id;
614 char *name;
615};
616
617static const struct chip_id chip_ids[] = {
618 { CHIP_9115, "LAN9115" },
619 { CHIP_9116, "LAN9116" },
620 { CHIP_9117, "LAN9117" },
621 { CHIP_9118, "LAN9118" },
622 { 0, NULL },
623};
624
625#define IS_REV_A(x) ((x & 0xFFFF)==0)
626
627/*
628 * Macros to abstract register access according to the data bus
629 * capabilities. Please use those and not the in/out primitives.
630 */
631/* FIFO read/write macros */
632#define SMC_PUSH_DATA(p, l) SMC_outsl( ioaddr, TX_DATA_FIFO, p, (l) >> 2 )
633#define SMC_PULL_DATA(p, l) SMC_insl ( ioaddr, RX_DATA_FIFO, p, (l) >> 2 )
634#define SMC_SET_TX_FIFO(x) SMC_outl( x, ioaddr, TX_DATA_FIFO )
635#define SMC_GET_RX_FIFO() SMC_inl( ioaddr, RX_DATA_FIFO )
636
637
638/* I/O mapped register read/write macros */
639#define SMC_GET_TX_STS_FIFO() SMC_inl( ioaddr, TX_STATUS_FIFO )
640#define SMC_GET_RX_STS_FIFO() SMC_inl( ioaddr, RX_STATUS_FIFO )
641#define SMC_GET_RX_STS_FIFO_PEEK() SMC_inl( ioaddr, RX_STATUS_FIFO_PEEK )
642#define SMC_GET_PN() (SMC_inl( ioaddr, ID_REV ) >> 16)
643#define SMC_GET_REV() (SMC_inl( ioaddr, ID_REV ) & 0xFFFF)
644#define SMC_GET_IRQ_CFG() SMC_inl( ioaddr, INT_CFG )
645#define SMC_SET_IRQ_CFG(x) SMC_outl( x, ioaddr, INT_CFG )
646#define SMC_GET_INT() SMC_inl( ioaddr, INT_STS )
647#define SMC_ACK_INT(x) SMC_outl( x, ioaddr, INT_STS )
648#define SMC_GET_INT_EN() SMC_inl( ioaddr, INT_EN )
649#define SMC_SET_INT_EN(x) SMC_outl( x, ioaddr, INT_EN )
650#define SMC_GET_BYTE_TEST() SMC_inl( ioaddr, BYTE_TEST )
651#define SMC_SET_BYTE_TEST(x) SMC_outl( x, ioaddr, BYTE_TEST )
652#define SMC_GET_FIFO_INT() SMC_inl( ioaddr, FIFO_INT )
653#define SMC_SET_FIFO_INT(x) SMC_outl( x, ioaddr, FIFO_INT )
654#define SMC_SET_FIFO_TDA(x) \
655 do { \
656 unsigned long __flags; \
657 int __mask; \
658 local_irq_save(__flags); \
659 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<24); \
660 SMC_SET_FIFO_INT( __mask | (x)<<24 ); \
661 local_irq_restore(__flags); \
662 } while (0)
663#define SMC_SET_FIFO_TSL(x) \
664 do { \
665 unsigned long __flags; \
666 int __mask; \
667 local_irq_save(__flags); \
668 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<16); \
669 SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<16)); \
670 local_irq_restore(__flags); \
671 } while (0)
672#define SMC_SET_FIFO_RSA(x) \
673 do { \
674 unsigned long __flags; \
675 int __mask; \
676 local_irq_save(__flags); \
677 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<8); \
678 SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<8)); \
679 local_irq_restore(__flags); \
680 } while (0)
681#define SMC_SET_FIFO_RSL(x) \
682 do { \
683 unsigned long __flags; \
684 int __mask; \
685 local_irq_save(__flags); \
686 __mask = SMC_GET_FIFO_INT() & ~0xFF; \
687 SMC_SET_FIFO_INT( __mask | ((x) & 0xFF)); \
688 local_irq_restore(__flags); \
689 } while (0)
690#define SMC_GET_RX_CFG() SMC_inl( ioaddr, RX_CFG )
691#define SMC_SET_RX_CFG(x) SMC_outl( x, ioaddr, RX_CFG )
692#define SMC_GET_TX_CFG() SMC_inl( ioaddr, TX_CFG )
693#define SMC_SET_TX_CFG(x) SMC_outl( x, ioaddr, TX_CFG )
694#define SMC_GET_HW_CFG() SMC_inl( ioaddr, HW_CFG )
695#define SMC_SET_HW_CFG(x) SMC_outl( x, ioaddr, HW_CFG )
696#define SMC_GET_RX_DP_CTRL() SMC_inl( ioaddr, RX_DP_CTRL )
697#define SMC_SET_RX_DP_CTRL(x) SMC_outl( x, ioaddr, RX_DP_CTRL )
698#define SMC_GET_PMT_CTRL() SMC_inl( ioaddr, PMT_CTRL )
699#define SMC_SET_PMT_CTRL(x) SMC_outl( x, ioaddr, PMT_CTRL )
700#define SMC_GET_GPIO_CFG() SMC_inl( ioaddr, GPIO_CFG )
701#define SMC_SET_GPIO_CFG(x) SMC_outl( x, ioaddr, GPIO_CFG )
702#define SMC_GET_RX_FIFO_INF() SMC_inl( ioaddr, RX_FIFO_INF )
703#define SMC_SET_RX_FIFO_INF(x) SMC_outl( x, ioaddr, RX_FIFO_INF )
704#define SMC_GET_TX_FIFO_INF() SMC_inl( ioaddr, TX_FIFO_INF )
705#define SMC_SET_TX_FIFO_INF(x) SMC_outl( x, ioaddr, TX_FIFO_INF )
706#define SMC_GET_GPT_CFG() SMC_inl( ioaddr, GPT_CFG )
707#define SMC_SET_GPT_CFG(x) SMC_outl( x, ioaddr, GPT_CFG )
708#define SMC_GET_RX_DROP() SMC_inl( ioaddr, RX_DROP )
709#define SMC_SET_RX_DROP(x) SMC_outl( x, ioaddr, RX_DROP )
710#define SMC_GET_MAC_CMD() SMC_inl( ioaddr, MAC_CSR_CMD )
711#define SMC_SET_MAC_CMD(x) SMC_outl( x, ioaddr, MAC_CSR_CMD )
712#define SMC_GET_MAC_DATA() SMC_inl( ioaddr, MAC_CSR_DATA )
713#define SMC_SET_MAC_DATA(x) SMC_outl( x, ioaddr, MAC_CSR_DATA )
714#define SMC_GET_AFC_CFG() SMC_inl( ioaddr, AFC_CFG )
715#define SMC_SET_AFC_CFG(x) SMC_outl( x, ioaddr, AFC_CFG )
716#define SMC_GET_E2P_CMD() SMC_inl( ioaddr, E2P_CMD )
717#define SMC_SET_E2P_CMD(x) SMC_outl( x, ioaddr, E2P_CMD )
718#define SMC_GET_E2P_DATA() SMC_inl( ioaddr, E2P_DATA )
719#define SMC_SET_E2P_DATA(x) SMC_outl( x, ioaddr, E2P_DATA )
720
721/* MAC register read/write macros */
722#define SMC_GET_MAC_CSR(a,v) \
723 do { \
724 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
725 SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ | \
726 MAC_CSR_CMD_R_NOT_W_ | (a) ); \
727 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
728 v = SMC_GET_MAC_DATA(); \
729 } while (0)
730#define SMC_SET_MAC_CSR(a,v) \
731 do { \
732 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
733 SMC_SET_MAC_DATA(v); \
734 SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ | (a) ); \
735 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
736 } while (0)
737#define SMC_GET_MAC_CR(x) SMC_GET_MAC_CSR( MAC_CR, x )
738#define SMC_SET_MAC_CR(x) SMC_SET_MAC_CSR( MAC_CR, x )
739#define SMC_GET_ADDRH(x) SMC_GET_MAC_CSR( ADDRH, x )
740#define SMC_SET_ADDRH(x) SMC_SET_MAC_CSR( ADDRH, x )
741#define SMC_GET_ADDRL(x) SMC_GET_MAC_CSR( ADDRL, x )
742#define SMC_SET_ADDRL(x) SMC_SET_MAC_CSR( ADDRL, x )
743#define SMC_GET_HASHH(x) SMC_GET_MAC_CSR( HASHH, x )
744#define SMC_SET_HASHH(x) SMC_SET_MAC_CSR( HASHH, x )
745#define SMC_GET_HASHL(x) SMC_GET_MAC_CSR( HASHL, x )
746#define SMC_SET_HASHL(x) SMC_SET_MAC_CSR( HASHL, x )
747#define SMC_GET_MII_ACC(x) SMC_GET_MAC_CSR( MII_ACC, x )
748#define SMC_SET_MII_ACC(x) SMC_SET_MAC_CSR( MII_ACC, x )
749#define SMC_GET_MII_DATA(x) SMC_GET_MAC_CSR( MII_DATA, x )
750#define SMC_SET_MII_DATA(x) SMC_SET_MAC_CSR( MII_DATA, x )
751#define SMC_GET_FLOW(x) SMC_GET_MAC_CSR( FLOW, x )
752#define SMC_SET_FLOW(x) SMC_SET_MAC_CSR( FLOW, x )
753#define SMC_GET_VLAN1(x) SMC_GET_MAC_CSR( VLAN1, x )
754#define SMC_SET_VLAN1(x) SMC_SET_MAC_CSR( VLAN1, x )
755#define SMC_GET_VLAN2(x) SMC_GET_MAC_CSR( VLAN2, x )
756#define SMC_SET_VLAN2(x) SMC_SET_MAC_CSR( VLAN2, x )
757#define SMC_SET_WUFF(x) SMC_SET_MAC_CSR( WUFF, x )
758#define SMC_GET_WUCSR(x) SMC_GET_MAC_CSR( WUCSR, x )
759#define SMC_SET_WUCSR(x) SMC_SET_MAC_CSR( WUCSR, x )
760
761/* PHY register read/write macros */
762#define SMC_GET_MII(a,phy,v) \
763 do { \
764 u32 __v; \
765 do { \
766 SMC_GET_MII_ACC(__v); \
767 } while ( __v & MII_ACC_MII_BUSY_ ); \
768 SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) | \
769 MII_ACC_MII_BUSY_); \
770 do { \
771 SMC_GET_MII_ACC(__v); \
772 } while ( __v & MII_ACC_MII_BUSY_ ); \
773 SMC_GET_MII_DATA(v); \
774 } while (0)
775#define SMC_SET_MII(a,phy,v) \
776 do { \
777 u32 __v; \
778 do { \
779 SMC_GET_MII_ACC(__v); \
780 } while ( __v & MII_ACC_MII_BUSY_ ); \
781 SMC_SET_MII_DATA(v); \
782 SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) | \
783 MII_ACC_MII_BUSY_ | \
784 MII_ACC_MII_WRITE_ ); \
785 do { \
786 SMC_GET_MII_ACC(__v); \
787 } while ( __v & MII_ACC_MII_BUSY_ ); \
788 } while (0)
789#define SMC_GET_PHY_BMCR(phy,x) SMC_GET_MII( MII_BMCR, phy, x )
790#define SMC_SET_PHY_BMCR(phy,x) SMC_SET_MII( MII_BMCR, phy, x )
791#define SMC_GET_PHY_BMSR(phy,x) SMC_GET_MII( MII_BMSR, phy, x )
792#define SMC_GET_PHY_ID1(phy,x) SMC_GET_MII( MII_PHYSID1, phy, x )
793#define SMC_GET_PHY_ID2(phy,x) SMC_GET_MII( MII_PHYSID2, phy, x )
794#define SMC_GET_PHY_MII_ADV(phy,x) SMC_GET_MII( MII_ADVERTISE, phy, x )
795#define SMC_SET_PHY_MII_ADV(phy,x) SMC_SET_MII( MII_ADVERTISE, phy, x )
796#define SMC_GET_PHY_MII_LPA(phy,x) SMC_GET_MII( MII_LPA, phy, x )
797#define SMC_SET_PHY_MII_LPA(phy,x) SMC_SET_MII( MII_LPA, phy, x )
798#define SMC_GET_PHY_CTRL_STS(phy,x) SMC_GET_MII( PHY_MODE_CTRL_STS, phy, x )
799#define SMC_SET_PHY_CTRL_STS(phy,x) SMC_SET_MII( PHY_MODE_CTRL_STS, phy, x )
800#define SMC_GET_PHY_INT_SRC(phy,x) SMC_GET_MII( PHY_INT_SRC, phy, x )
801#define SMC_SET_PHY_INT_SRC(phy,x) SMC_SET_MII( PHY_INT_SRC, phy, x )
802#define SMC_GET_PHY_INT_MASK(phy,x) SMC_GET_MII( PHY_INT_MASK, phy, x )
803#define SMC_SET_PHY_INT_MASK(phy,x) SMC_SET_MII( PHY_INT_MASK, phy, x )
804#define SMC_GET_PHY_SPECIAL(phy,x) SMC_GET_MII( PHY_SPECIAL, phy, x )
805
806
807
808/* Misc read/write macros */
809
810#ifndef SMC_GET_MAC_ADDR
811#define SMC_GET_MAC_ADDR(addr) \
812 do { \
813 unsigned int __v; \
814 \
815 SMC_GET_MAC_CSR(ADDRL, __v); \
816 addr[0] = __v; addr[1] = __v >> 8; \
817 addr[2] = __v >> 16; addr[3] = __v >> 24; \
818 SMC_GET_MAC_CSR(ADDRH, __v); \
819 addr[4] = __v; addr[5] = __v >> 8; \
820 } while (0)
821#endif
822
823#define SMC_SET_MAC_ADDR(addr) \
824 do { \
825 SMC_SET_MAC_CSR(ADDRL, \
826 addr[0] | \
827 (addr[1] << 8) | \
828 (addr[2] << 16) | \
829 (addr[3] << 24)); \
830 SMC_SET_MAC_CSR(ADDRH, addr[4]|(addr[5] << 8));\
831 } while (0)
832
833
834#define SMC_WRITE_EEPROM_CMD(cmd, addr) \
835 do { \
836 while (SMC_GET_E2P_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
837 SMC_SET_MAC_CMD(MAC_CSR_CMD_R_NOT_W_ | a ); \
838 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
839 } while (0)
840
841#endif /* _SMC911X_H_ */