tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/************************************************************************
2 * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2007 Neterion Inc.
4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 ************************************************************************/
13#ifndef _S2IO_H
14#define _S2IO_H
15
16#define TBD 0
17#define s2BIT(loc) (0x8000000000000000ULL >> (loc))
18#define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
19#define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
20
21#ifndef BOOL
22#define BOOL int
23#endif
24
25#ifndef TRUE
26#define TRUE 1
27#define FALSE 0
28#endif
29
30#undef SUCCESS
31#define SUCCESS 0
32#define FAILURE -1
33#define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL
34#define S2IO_DISABLE_MAC_ENTRY 0xFFFFFFFFFFFFULL
35#define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100
36#define S2IO_BIT_RESET 1
37#define S2IO_BIT_SET 2
38#define CHECKBIT(value, nbit) (value & (1 << nbit))
39
40/* Maximum time to flicker LED when asked to identify NIC using ethtool */
41#define MAX_FLICKER_TIME 60000 /* 60 Secs */
42
43/* Maximum outstanding splits to be configured into xena. */
44enum {
45 XENA_ONE_SPLIT_TRANSACTION = 0,
46 XENA_TWO_SPLIT_TRANSACTION = 1,
47 XENA_THREE_SPLIT_TRANSACTION = 2,
48 XENA_FOUR_SPLIT_TRANSACTION = 3,
49 XENA_EIGHT_SPLIT_TRANSACTION = 4,
50 XENA_TWELVE_SPLIT_TRANSACTION = 5,
51 XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
52 XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
53};
54#define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
55
56/* OS concerned variables and constants */
57#define WATCH_DOG_TIMEOUT 15*HZ
58#define EFILL 0x1234
59#define ALIGN_SIZE 127
60#define PCIX_COMMAND_REGISTER 0x62
61
62/*
63 * Debug related variables.
64 */
65/* different debug levels. */
66#define ERR_DBG 0
67#define INIT_DBG 1
68#define INFO_DBG 2
69#define TX_DBG 3
70#define INTR_DBG 4
71
72/* Global variable that defines the present debug level of the driver. */
73static int debug_level = ERR_DBG;
74
75/* DEBUG message print. */
76#define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args)
77
78#ifndef DMA_ERROR_CODE
79#define DMA_ERROR_CODE (~(dma_addr_t)0x0)
80#endif
81
82/* Protocol assist features of the NIC */
83#define L3_CKSUM_OK 0xFFFF
84#define L4_CKSUM_OK 0xFFFF
85#define S2IO_JUMBO_SIZE 9600
86
87/* Driver statistics maintained by driver */
88struct swStat {
89 unsigned long long single_ecc_errs;
90 unsigned long long double_ecc_errs;
91 unsigned long long parity_err_cnt;
92 unsigned long long serious_err_cnt;
93 unsigned long long soft_reset_cnt;
94 unsigned long long fifo_full_cnt;
95 unsigned long long ring_full_cnt[8];
96 /* LRO statistics */
97 unsigned long long clubbed_frms_cnt;
98 unsigned long long sending_both;
99 unsigned long long outof_sequence_pkts;
100 unsigned long long flush_max_pkts;
101 unsigned long long sum_avg_pkts_aggregated;
102 unsigned long long num_aggregations;
103 /* Other statistics */
104 unsigned long long mem_alloc_fail_cnt;
105 unsigned long long pci_map_fail_cnt;
106 unsigned long long watchdog_timer_cnt;
107 unsigned long long mem_allocated;
108 unsigned long long mem_freed;
109 unsigned long long link_up_cnt;
110 unsigned long long link_down_cnt;
111 unsigned long long link_up_time;
112 unsigned long long link_down_time;
113
114 /* Transfer Code statistics */
115 unsigned long long tx_buf_abort_cnt;
116 unsigned long long tx_desc_abort_cnt;
117 unsigned long long tx_parity_err_cnt;
118 unsigned long long tx_link_loss_cnt;
119 unsigned long long tx_list_proc_err_cnt;
120
121 unsigned long long rx_parity_err_cnt;
122 unsigned long long rx_abort_cnt;
123 unsigned long long rx_parity_abort_cnt;
124 unsigned long long rx_rda_fail_cnt;
125 unsigned long long rx_unkn_prot_cnt;
126 unsigned long long rx_fcs_err_cnt;
127 unsigned long long rx_buf_size_err_cnt;
128 unsigned long long rx_rxd_corrupt_cnt;
129 unsigned long long rx_unkn_err_cnt;
130
131 /* Error/alarm statistics*/
132 unsigned long long tda_err_cnt;
133 unsigned long long pfc_err_cnt;
134 unsigned long long pcc_err_cnt;
135 unsigned long long tti_err_cnt;
136 unsigned long long lso_err_cnt;
137 unsigned long long tpa_err_cnt;
138 unsigned long long sm_err_cnt;
139 unsigned long long mac_tmac_err_cnt;
140 unsigned long long mac_rmac_err_cnt;
141 unsigned long long xgxs_txgxs_err_cnt;
142 unsigned long long xgxs_rxgxs_err_cnt;
143 unsigned long long rc_err_cnt;
144 unsigned long long prc_pcix_err_cnt;
145 unsigned long long rpa_err_cnt;
146 unsigned long long rda_err_cnt;
147 unsigned long long rti_err_cnt;
148 unsigned long long mc_err_cnt;
149
150};
151
152/* Xpak releated alarm and warnings */
153struct xpakStat {
154 u64 alarm_transceiver_temp_high;
155 u64 alarm_transceiver_temp_low;
156 u64 alarm_laser_bias_current_high;
157 u64 alarm_laser_bias_current_low;
158 u64 alarm_laser_output_power_high;
159 u64 alarm_laser_output_power_low;
160 u64 warn_transceiver_temp_high;
161 u64 warn_transceiver_temp_low;
162 u64 warn_laser_bias_current_high;
163 u64 warn_laser_bias_current_low;
164 u64 warn_laser_output_power_high;
165 u64 warn_laser_output_power_low;
166 u64 xpak_regs_stat;
167 u32 xpak_timer_count;
168};
169
170
171/* The statistics block of Xena */
172struct stat_block {
173/* Tx MAC statistics counters. */
174 __le32 tmac_data_octets;
175 __le32 tmac_frms;
176 __le64 tmac_drop_frms;
177 __le32 tmac_bcst_frms;
178 __le32 tmac_mcst_frms;
179 __le64 tmac_pause_ctrl_frms;
180 __le32 tmac_ucst_frms;
181 __le32 tmac_ttl_octets;
182 __le32 tmac_any_err_frms;
183 __le32 tmac_nucst_frms;
184 __le64 tmac_ttl_less_fb_octets;
185 __le64 tmac_vld_ip_octets;
186 __le32 tmac_drop_ip;
187 __le32 tmac_vld_ip;
188 __le32 tmac_rst_tcp;
189 __le32 tmac_icmp;
190 __le64 tmac_tcp;
191 __le32 reserved_0;
192 __le32 tmac_udp;
193
194/* Rx MAC Statistics counters. */
195 __le32 rmac_data_octets;
196 __le32 rmac_vld_frms;
197 __le64 rmac_fcs_err_frms;
198 __le64 rmac_drop_frms;
199 __le32 rmac_vld_bcst_frms;
200 __le32 rmac_vld_mcst_frms;
201 __le32 rmac_out_rng_len_err_frms;
202 __le32 rmac_in_rng_len_err_frms;
203 __le64 rmac_long_frms;
204 __le64 rmac_pause_ctrl_frms;
205 __le64 rmac_unsup_ctrl_frms;
206 __le32 rmac_accepted_ucst_frms;
207 __le32 rmac_ttl_octets;
208 __le32 rmac_discarded_frms;
209 __le32 rmac_accepted_nucst_frms;
210 __le32 reserved_1;
211 __le32 rmac_drop_events;
212 __le64 rmac_ttl_less_fb_octets;
213 __le64 rmac_ttl_frms;
214 __le64 reserved_2;
215 __le32 rmac_usized_frms;
216 __le32 reserved_3;
217 __le32 rmac_frag_frms;
218 __le32 rmac_osized_frms;
219 __le32 reserved_4;
220 __le32 rmac_jabber_frms;
221 __le64 rmac_ttl_64_frms;
222 __le64 rmac_ttl_65_127_frms;
223 __le64 reserved_5;
224 __le64 rmac_ttl_128_255_frms;
225 __le64 rmac_ttl_256_511_frms;
226 __le64 reserved_6;
227 __le64 rmac_ttl_512_1023_frms;
228 __le64 rmac_ttl_1024_1518_frms;
229 __le32 rmac_ip;
230 __le32 reserved_7;
231 __le64 rmac_ip_octets;
232 __le32 rmac_drop_ip;
233 __le32 rmac_hdr_err_ip;
234 __le32 reserved_8;
235 __le32 rmac_icmp;
236 __le64 rmac_tcp;
237 __le32 rmac_err_drp_udp;
238 __le32 rmac_udp;
239 __le64 rmac_xgmii_err_sym;
240 __le64 rmac_frms_q0;
241 __le64 rmac_frms_q1;
242 __le64 rmac_frms_q2;
243 __le64 rmac_frms_q3;
244 __le64 rmac_frms_q4;
245 __le64 rmac_frms_q5;
246 __le64 rmac_frms_q6;
247 __le64 rmac_frms_q7;
248 __le16 rmac_full_q3;
249 __le16 rmac_full_q2;
250 __le16 rmac_full_q1;
251 __le16 rmac_full_q0;
252 __le16 rmac_full_q7;
253 __le16 rmac_full_q6;
254 __le16 rmac_full_q5;
255 __le16 rmac_full_q4;
256 __le32 reserved_9;
257 __le32 rmac_pause_cnt;
258 __le64 rmac_xgmii_data_err_cnt;
259 __le64 rmac_xgmii_ctrl_err_cnt;
260 __le32 rmac_err_tcp;
261 __le32 rmac_accepted_ip;
262
263/* PCI/PCI-X Read transaction statistics. */
264 __le32 new_rd_req_cnt;
265 __le32 rd_req_cnt;
266 __le32 rd_rtry_cnt;
267 __le32 new_rd_req_rtry_cnt;
268
269/* PCI/PCI-X Write/Read transaction statistics. */
270 __le32 wr_req_cnt;
271 __le32 wr_rtry_rd_ack_cnt;
272 __le32 new_wr_req_rtry_cnt;
273 __le32 new_wr_req_cnt;
274 __le32 wr_disc_cnt;
275 __le32 wr_rtry_cnt;
276
277/* PCI/PCI-X Write / DMA Transaction statistics. */
278 __le32 txp_wr_cnt;
279 __le32 rd_rtry_wr_ack_cnt;
280 __le32 txd_wr_cnt;
281 __le32 txd_rd_cnt;
282 __le32 rxd_wr_cnt;
283 __le32 rxd_rd_cnt;
284 __le32 rxf_wr_cnt;
285 __le32 txf_rd_cnt;
286
287/* Tx MAC statistics overflow counters. */
288 __le32 tmac_data_octets_oflow;
289 __le32 tmac_frms_oflow;
290 __le32 tmac_bcst_frms_oflow;
291 __le32 tmac_mcst_frms_oflow;
292 __le32 tmac_ucst_frms_oflow;
293 __le32 tmac_ttl_octets_oflow;
294 __le32 tmac_any_err_frms_oflow;
295 __le32 tmac_nucst_frms_oflow;
296 __le64 tmac_vlan_frms;
297 __le32 tmac_drop_ip_oflow;
298 __le32 tmac_vld_ip_oflow;
299 __le32 tmac_rst_tcp_oflow;
300 __le32 tmac_icmp_oflow;
301 __le32 tpa_unknown_protocol;
302 __le32 tmac_udp_oflow;
303 __le32 reserved_10;
304 __le32 tpa_parse_failure;
305
306/* Rx MAC Statistics overflow counters. */
307 __le32 rmac_data_octets_oflow;
308 __le32 rmac_vld_frms_oflow;
309 __le32 rmac_vld_bcst_frms_oflow;
310 __le32 rmac_vld_mcst_frms_oflow;
311 __le32 rmac_accepted_ucst_frms_oflow;
312 __le32 rmac_ttl_octets_oflow;
313 __le32 rmac_discarded_frms_oflow;
314 __le32 rmac_accepted_nucst_frms_oflow;
315 __le32 rmac_usized_frms_oflow;
316 __le32 rmac_drop_events_oflow;
317 __le32 rmac_frag_frms_oflow;
318 __le32 rmac_osized_frms_oflow;
319 __le32 rmac_ip_oflow;
320 __le32 rmac_jabber_frms_oflow;
321 __le32 rmac_icmp_oflow;
322 __le32 rmac_drop_ip_oflow;
323 __le32 rmac_err_drp_udp_oflow;
324 __le32 rmac_udp_oflow;
325 __le32 reserved_11;
326 __le32 rmac_pause_cnt_oflow;
327 __le64 rmac_ttl_1519_4095_frms;
328 __le64 rmac_ttl_4096_8191_frms;
329 __le64 rmac_ttl_8192_max_frms;
330 __le64 rmac_ttl_gt_max_frms;
331 __le64 rmac_osized_alt_frms;
332 __le64 rmac_jabber_alt_frms;
333 __le64 rmac_gt_max_alt_frms;
334 __le64 rmac_vlan_frms;
335 __le32 rmac_len_discard;
336 __le32 rmac_fcs_discard;
337 __le32 rmac_pf_discard;
338 __le32 rmac_da_discard;
339 __le32 rmac_red_discard;
340 __le32 rmac_rts_discard;
341 __le32 reserved_12;
342 __le32 rmac_ingm_full_discard;
343 __le32 reserved_13;
344 __le32 rmac_accepted_ip_oflow;
345 __le32 reserved_14;
346 __le32 link_fault_cnt;
347 u8 buffer[20];
348 struct swStat sw_stat;
349 struct xpakStat xpak_stat;
350};
351
352/* Default value for 'vlan_strip_tag' configuration parameter */
353#define NO_STRIP_IN_PROMISC 2
354
355/*
356 * Structures representing different init time configuration
357 * parameters of the NIC.
358 */
359
360#define MAX_TX_FIFOS 8
361#define MAX_RX_RINGS 8
362
363#define FIFO_DEFAULT_NUM 1
364
365#define MAX_RX_DESC_1 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 127 )
366#define MAX_RX_DESC_2 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
367#define MAX_RX_DESC_3 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
368#define MAX_TX_DESC (MAX_AVAILABLE_TXDS)
369
370/* FIFO mappings for all possible number of fifos configured */
371static int fifo_map[][MAX_TX_FIFOS] = {
372 {0, 0, 0, 0, 0, 0, 0, 0},
373 {0, 0, 0, 0, 1, 1, 1, 1},
374 {0, 0, 0, 1, 1, 1, 2, 2},
375 {0, 0, 1, 1, 2, 2, 3, 3},
376 {0, 0, 1, 1, 2, 2, 3, 4},
377 {0, 0, 1, 1, 2, 3, 4, 5},
378 {0, 0, 1, 2, 3, 4, 5, 6},
379 {0, 1, 2, 3, 4, 5, 6, 7},
380};
381
382/* Maintains Per FIFO related information. */
383struct tx_fifo_config {
384#define MAX_AVAILABLE_TXDS 8192
385 u32 fifo_len; /* specifies len of FIFO upto 8192, ie no of TxDLs */
386/* Priority definition */
387#define TX_FIFO_PRI_0 0 /*Highest */
388#define TX_FIFO_PRI_1 1
389#define TX_FIFO_PRI_2 2
390#define TX_FIFO_PRI_3 3
391#define TX_FIFO_PRI_4 4
392#define TX_FIFO_PRI_5 5
393#define TX_FIFO_PRI_6 6
394#define TX_FIFO_PRI_7 7 /*lowest */
395 u8 fifo_priority; /* specifies pointer level for FIFO */
396 /* user should not set twos fifos with same pri */
397 u8 f_no_snoop;
398#define NO_SNOOP_TXD 0x01
399#define NO_SNOOP_TXD_BUFFER 0x02
400};
401
402
403/* Maintains per Ring related information */
404struct rx_ring_config {
405 u32 num_rxd; /*No of RxDs per Rx Ring */
406#define RX_RING_PRI_0 0 /* highest */
407#define RX_RING_PRI_1 1
408#define RX_RING_PRI_2 2
409#define RX_RING_PRI_3 3
410#define RX_RING_PRI_4 4
411#define RX_RING_PRI_5 5
412#define RX_RING_PRI_6 6
413#define RX_RING_PRI_7 7 /* lowest */
414
415 u8 ring_priority; /*Specifies service priority of ring */
416 /* OSM should not set any two rings with same priority */
417 u8 ring_org; /*Organization of ring */
418#define RING_ORG_BUFF1 0x01
419#define RX_RING_ORG_BUFF3 0x03
420#define RX_RING_ORG_BUFF5 0x05
421
422 u8 f_no_snoop;
423#define NO_SNOOP_RXD 0x01
424#define NO_SNOOP_RXD_BUFFER 0x02
425};
426
427/* This structure provides contains values of the tunable parameters
428 * of the H/W
429 */
430struct config_param {
431/* Tx Side */
432 u32 tx_fifo_num; /*Number of Tx FIFOs */
433
434 u8 fifo_mapping[MAX_TX_FIFOS];
435 struct tx_fifo_config tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
436 u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */
437 u64 tx_intr_type;
438#define INTA 0
439#define MSI_X 2
440 u8 intr_type;
441 u8 napi;
442
443 /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
444
445/* Rx Side */
446 u32 rx_ring_num; /*Number of receive rings */
447#define MAX_RX_BLOCKS_PER_RING 150
448
449 struct rx_ring_config rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
450
451#define HEADER_ETHERNET_II_802_3_SIZE 14
452#define HEADER_802_2_SIZE 3
453#define HEADER_SNAP_SIZE 5
454#define HEADER_VLAN_SIZE 4
455
456#define MIN_MTU 46
457#define MAX_PYLD 1500
458#define MAX_MTU (MAX_PYLD+18)
459#define MAX_MTU_VLAN (MAX_PYLD+22)
460#define MAX_PYLD_JUMBO 9600
461#define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
462#define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
463 u16 bus_speed;
464 int max_mc_addr; /* xena=64 herc=256 */
465 int max_mac_addr; /* xena=16 herc=64 */
466 int mc_start_offset; /* xena=16 herc=64 */
467};
468
469/* Structure representing MAC Addrs */
470struct mac_addr {
471 u8 mac_addr[ETH_ALEN];
472};
473
474/* Structure that represent every FIFO element in the BAR1
475 * Address location.
476 */
477struct TxFIFO_element {
478 u64 TxDL_Pointer;
479
480 u64 List_Control;
481#define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8)
482#define TX_FIFO_FIRST_LIST s2BIT(14)
483#define TX_FIFO_LAST_LIST s2BIT(15)
484#define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2)
485#define TX_FIFO_SPECIAL_FUNC s2BIT(23)
486#define TX_FIFO_DS_NO_SNOOP s2BIT(31)
487#define TX_FIFO_BUFF_NO_SNOOP s2BIT(30)
488};
489
490/* Tx descriptor structure */
491struct TxD {
492 u64 Control_1;
493/* bit mask */
494#define TXD_LIST_OWN_XENA s2BIT(7)
495#define TXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
496#define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE))
497#define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12)
498#define TXD_GATHER_CODE (s2BIT(22) | s2BIT(23))
499#define TXD_GATHER_CODE_FIRST s2BIT(22)
500#define TXD_GATHER_CODE_LAST s2BIT(23)
501#define TXD_TCP_LSO_EN s2BIT(30)
502#define TXD_UDP_COF_EN s2BIT(31)
503#define TXD_UFO_EN s2BIT(31) | s2BIT(30)
504#define TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
505#define TXD_UFO_MSS(val) vBIT(val,34,14)
506#define TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
507
508 u64 Control_2;
509#define TXD_TX_CKO_CONTROL (s2BIT(5)|s2BIT(6)|s2BIT(7))
510#define TXD_TX_CKO_IPV4_EN s2BIT(5)
511#define TXD_TX_CKO_TCP_EN s2BIT(6)
512#define TXD_TX_CKO_UDP_EN s2BIT(7)
513#define TXD_VLAN_ENABLE s2BIT(15)
514#define TXD_VLAN_TAG(val) vBIT(val,16,16)
515#define TXD_INT_NUMBER(val) vBIT(val,34,6)
516#define TXD_INT_TYPE_PER_LIST s2BIT(47)
517#define TXD_INT_TYPE_UTILZ s2BIT(46)
518#define TXD_SET_MARKER vBIT(0x6,0,4)
519
520 u64 Buffer_Pointer;
521 u64 Host_Control; /* reserved for host */
522};
523
524/* Structure to hold the phy and virt addr of every TxDL. */
525struct list_info_hold {
526 dma_addr_t list_phy_addr;
527 void *list_virt_addr;
528};
529
530/* Rx descriptor structure for 1 buffer mode */
531struct RxD_t {
532 u64 Host_Control; /* reserved for host */
533 u64 Control_1;
534#define RXD_OWN_XENA s2BIT(7)
535#define RXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
536#define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
537#define RXD_FRAME_PROTO_IPV4 s2BIT(27)
538#define RXD_FRAME_PROTO_IPV6 s2BIT(28)
539#define RXD_FRAME_IP_FRAG s2BIT(29)
540#define RXD_FRAME_PROTO_TCP s2BIT(30)
541#define RXD_FRAME_PROTO_UDP s2BIT(31)
542#define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
543#define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF)
544#define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
545
546 u64 Control_2;
547#define THE_RXD_MARK 0x3
548#define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2)
549#define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62)
550
551#define MASK_VLAN_TAG vBIT(0xFFFF,48,16)
552#define SET_VLAN_TAG(val) vBIT(val,48,16)
553#define SET_NUM_TAG(val) vBIT(val,16,32)
554
555
556};
557/* Rx descriptor structure for 1 buffer mode */
558struct RxD1 {
559 struct RxD_t h;
560
561#define MASK_BUFFER0_SIZE_1 vBIT(0x3FFF,2,14)
562#define SET_BUFFER0_SIZE_1(val) vBIT(val,2,14)
563#define RXD_GET_BUFFER0_SIZE_1(_Control_2) \
564 (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48)
565 u64 Buffer0_ptr;
566};
567/* Rx descriptor structure for 3 or 2 buffer mode */
568
569struct RxD3 {
570 struct RxD_t h;
571
572#define MASK_BUFFER0_SIZE_3 vBIT(0xFF,2,14)
573#define MASK_BUFFER1_SIZE_3 vBIT(0xFFFF,16,16)
574#define MASK_BUFFER2_SIZE_3 vBIT(0xFFFF,32,16)
575#define SET_BUFFER0_SIZE_3(val) vBIT(val,8,8)
576#define SET_BUFFER1_SIZE_3(val) vBIT(val,16,16)
577#define SET_BUFFER2_SIZE_3(val) vBIT(val,32,16)
578#define RXD_GET_BUFFER0_SIZE_3(Control_2) \
579 (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48)
580#define RXD_GET_BUFFER1_SIZE_3(Control_2) \
581 (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32)
582#define RXD_GET_BUFFER2_SIZE_3(Control_2) \
583 (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16)
584#define BUF0_LEN 40
585#define BUF1_LEN 1
586
587 u64 Buffer0_ptr;
588 u64 Buffer1_ptr;
589 u64 Buffer2_ptr;
590};
591
592
593/* Structure that represents the Rx descriptor block which contains
594 * 128 Rx descriptors.
595 */
596struct RxD_block {
597#define MAX_RXDS_PER_BLOCK_1 127
598 struct RxD1 rxd[MAX_RXDS_PER_BLOCK_1];
599
600 u64 reserved_0;
601#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
602 u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last
603 * Rxd in this blk */
604 u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
605 u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch
606 * the upper 32 bits should
607 * be 0 */
608};
609
610#define SIZE_OF_BLOCK 4096
611
612#define RXD_MODE_1 0 /* One Buffer mode */
613#define RXD_MODE_3B 1 /* Two Buffer mode */
614
615/* Structure to hold virtual addresses of Buf0 and Buf1 in
616 * 2buf mode. */
617struct buffAdd {
618 void *ba_0_org;
619 void *ba_1_org;
620 void *ba_0;
621 void *ba_1;
622};
623
624/* Structure which stores all the MAC control parameters */
625
626/* This structure stores the offset of the RxD in the ring
627 * from which the Rx Interrupt processor can start picking
628 * up the RxDs for processing.
629 */
630struct rx_curr_get_info {
631 u32 block_index;
632 u32 offset;
633 u32 ring_len;
634};
635
636struct rx_curr_put_info {
637 u32 block_index;
638 u32 offset;
639 u32 ring_len;
640};
641
642/* This structure stores the offset of the TxDl in the FIFO
643 * from which the Tx Interrupt processor can start picking
644 * up the TxDLs for send complete interrupt processing.
645 */
646struct tx_curr_get_info {
647 u32 offset;
648 u32 fifo_len;
649};
650
651struct tx_curr_put_info {
652 u32 offset;
653 u32 fifo_len;
654};
655
656struct rxd_info {
657 void *virt_addr;
658 dma_addr_t dma_addr;
659};
660
661/* Structure that holds the Phy and virt addresses of the Blocks */
662struct rx_block_info {
663 void *block_virt_addr;
664 dma_addr_t block_dma_addr;
665 struct rxd_info *rxds;
666};
667
668/* Ring specific structure */
669struct ring_info {
670 /* The ring number */
671 int ring_no;
672
673 /*
674 * Place holders for the virtual and physical addresses of
675 * all the Rx Blocks
676 */
677 struct rx_block_info rx_blocks[MAX_RX_BLOCKS_PER_RING];
678 int block_count;
679 int pkt_cnt;
680
681 /*
682 * Put pointer info which indictes which RxD has to be replenished
683 * with a new buffer.
684 */
685 struct rx_curr_put_info rx_curr_put_info;
686
687 /*
688 * Get pointer info which indictes which is the last RxD that was
689 * processed by the driver.
690 */
691 struct rx_curr_get_info rx_curr_get_info;
692
693 /* Index to the absolute position of the put pointer of Rx ring */
694 int put_pos;
695
696 /* Buffer Address store. */
697 struct buffAdd **ba;
698 struct s2io_nic *nic;
699};
700
701/* Fifo specific structure */
702struct fifo_info {
703 /* FIFO number */
704 int fifo_no;
705
706 /* Maximum TxDs per TxDL */
707 int max_txds;
708
709 /* Place holder of all the TX List's Phy and Virt addresses. */
710 struct list_info_hold *list_info;
711
712 /*
713 * Current offset within the tx FIFO where driver would write
714 * new Tx frame
715 */
716 struct tx_curr_put_info tx_curr_put_info;
717
718 /*
719 * Current offset within tx FIFO from where the driver would start freeing
720 * the buffers
721 */
722 struct tx_curr_get_info tx_curr_get_info;
723
724 /* Per fifo lock */
725 spinlock_t tx_lock;
726
727 /* Per fifo UFO in band structure */
728 u64 *ufo_in_band_v;
729
730 struct s2io_nic *nic;
731} ____cacheline_aligned;
732
733/* Information related to the Tx and Rx FIFOs and Rings of Xena
734 * is maintained in this structure.
735 */
736struct mac_info {
737/* tx side stuff */
738 /* logical pointer of start of each Tx FIFO */
739 struct TxFIFO_element __iomem *tx_FIFO_start[MAX_TX_FIFOS];
740
741 /* Fifo specific structure */
742 struct fifo_info fifos[MAX_TX_FIFOS];
743
744 /* Save virtual address of TxD page with zero DMA addr(if any) */
745 void *zerodma_virt_addr;
746
747/* rx side stuff */
748 /* Ring specific structure */
749 struct ring_info rings[MAX_RX_RINGS];
750
751 u16 rmac_pause_time;
752 u16 mc_pause_threshold_q0q3;
753 u16 mc_pause_threshold_q4q7;
754
755 void *stats_mem; /* orignal pointer to allocated mem */
756 dma_addr_t stats_mem_phy; /* Physical address of the stat block */
757 u32 stats_mem_sz;
758 struct stat_block *stats_info; /* Logical address of the stat block */
759};
760
761/* structure representing the user defined MAC addresses */
762struct usr_addr {
763 char addr[ETH_ALEN];
764 int usage_cnt;
765};
766
767/* Default Tunable parameters of the NIC. */
768#define DEFAULT_FIFO_0_LEN 4096
769#define DEFAULT_FIFO_1_7_LEN 512
770#define SMALL_BLK_CNT 30
771#define LARGE_BLK_CNT 100
772
773/*
774 * Structure to keep track of the MSI-X vectors and the corresponding
775 * argument registered against each vector
776 */
777#define MAX_REQUESTED_MSI_X 17
778struct s2io_msix_entry
779{
780 u16 vector;
781 u16 entry;
782 void *arg;
783
784 u8 type;
785#define MSIX_FIFO_TYPE 1
786#define MSIX_RING_TYPE 2
787
788 u8 in_use;
789#define MSIX_REGISTERED_SUCCESS 0xAA
790};
791
792struct msix_info_st {
793 u64 addr;
794 u64 data;
795};
796
797/* Data structure to represent a LRO session */
798struct lro {
799 struct sk_buff *parent;
800 struct sk_buff *last_frag;
801 u8 *l2h;
802 struct iphdr *iph;
803 struct tcphdr *tcph;
804 u32 tcp_next_seq;
805 __be32 tcp_ack;
806 int total_len;
807 int frags_len;
808 int sg_num;
809 int in_use;
810 __be16 window;
811 u32 cur_tsval;
812 u32 cur_tsecr;
813 u8 saw_ts;
814};
815
816/* These flags represent the devices temporary state */
817enum s2io_device_state_t
818{
819 __S2IO_STATE_LINK_TASK=0,
820 __S2IO_STATE_CARD_UP
821};
822
823/* Structure representing one instance of the NIC */
824struct s2io_nic {
825 int rxd_mode;
826 /*
827 * Count of packets to be processed in a given iteration, it will be indicated
828 * by the quota field of the device structure when NAPI is enabled.
829 */
830 int pkts_to_process;
831 struct net_device *dev;
832 struct napi_struct napi;
833 struct mac_info mac_control;
834 struct config_param config;
835 struct pci_dev *pdev;
836 void __iomem *bar0;
837 void __iomem *bar1;
838#define MAX_MAC_SUPPORTED 16
839#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
840
841 struct mac_addr def_mac_addr[256];
842
843 struct net_device_stats stats;
844 int high_dma_flag;
845 int device_enabled_once;
846
847 char name[60];
848 struct tasklet_struct task;
849 volatile unsigned long tasklet_status;
850
851 /* Timer that handles I/O errors/exceptions */
852 struct timer_list alarm_timer;
853
854 /* Space to back up the PCI config space */
855 u32 config_space[256 / sizeof(u32)];
856
857 atomic_t rx_bufs_left[MAX_RX_RINGS];
858
859 spinlock_t put_lock;
860
861#define PROMISC 1
862#define ALL_MULTI 2
863
864#define MAX_ADDRS_SUPPORTED 64
865 u16 usr_addr_count;
866 u16 mc_addr_count;
867 struct usr_addr usr_addrs[256];
868
869 u16 m_cast_flg;
870 u16 all_multi_pos;
871 u16 promisc_flg;
872
873 /* Id timer, used to blink NIC to physically identify NIC. */
874 struct timer_list id_timer;
875
876 /* Restart timer, used to restart NIC if the device is stuck and
877 * a schedule task that will set the correct Link state once the
878 * NIC's PHY has stabilized after a state change.
879 */
880 struct work_struct rst_timer_task;
881 struct work_struct set_link_task;
882
883 /* Flag that can be used to turn on or turn off the Rx checksum
884 * offload feature.
885 */
886 int rx_csum;
887
888 /* after blink, the adapter must be restored with original
889 * values.
890 */
891 u64 adapt_ctrl_org;
892
893 /* Last known link state. */
894 u16 last_link_state;
895#define LINK_DOWN 1
896#define LINK_UP 2
897
898 int task_flag;
899 unsigned long long start_time;
900 struct vlan_group *vlgrp;
901#define MSIX_FLG 0xA5
902 struct msix_entry *entries;
903 int msi_detected;
904 wait_queue_head_t msi_wait;
905 struct s2io_msix_entry *s2io_entries;
906 char desc[MAX_REQUESTED_MSI_X][25];
907
908 int avail_msix_vectors; /* No. of MSI-X vectors granted by system */
909
910 struct msix_info_st msix_info[0x3f];
911
912#define XFRAME_I_DEVICE 1
913#define XFRAME_II_DEVICE 2
914 u8 device_type;
915
916#define MAX_LRO_SESSIONS 32
917 struct lro lro0_n[MAX_LRO_SESSIONS];
918 unsigned long clubbed_frms_cnt;
919 unsigned long sending_both;
920 u8 lro;
921 u16 lro_max_aggr_per_sess;
922 volatile unsigned long state;
923 spinlock_t rx_lock;
924 u64 general_int_mask;
925#define VPD_STRING_LEN 80
926 u8 product_name[VPD_STRING_LEN];
927 u8 serial_num[VPD_STRING_LEN];
928};
929
930#define RESET_ERROR 1;
931#define CMD_ERROR 2;
932
933/* OS related system calls */
934#ifndef readq
935static inline u64 readq(void __iomem *addr)
936{
937 u64 ret = 0;
938 ret = readl(addr + 4);
939 ret <<= 32;
940 ret |= readl(addr);
941
942 return ret;
943}
944#endif
945
946#ifndef writeq
947static inline void writeq(u64 val, void __iomem *addr)
948{
949 writel((u32) (val), addr);
950 writel((u32) (val >> 32), (addr + 4));
951}
952#endif
953
954/*
955 * Some registers have to be written in a particular order to
956 * expect correct hardware operation. The macro SPECIAL_REG_WRITE
957 * is used to perform such ordered writes. Defines UF (Upper First)
958 * and LF (Lower First) will be used to specify the required write order.
959 */
960#define UF 1
961#define LF 2
962static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
963{
964 u32 ret;
965
966 if (order == LF) {
967 writel((u32) (val), addr);
968 ret = readl(addr);
969 writel((u32) (val >> 32), (addr + 4));
970 ret = readl(addr + 4);
971 } else {
972 writel((u32) (val >> 32), (addr + 4));
973 ret = readl(addr + 4);
974 writel((u32) (val), addr);
975 ret = readl(addr);
976 }
977}
978
979/* Interrupt related values of Xena */
980
981#define ENABLE_INTRS 1
982#define DISABLE_INTRS 2
983
984/* Highest level interrupt blocks */
985#define TX_PIC_INTR (0x0001<<0)
986#define TX_DMA_INTR (0x0001<<1)
987#define TX_MAC_INTR (0x0001<<2)
988#define TX_XGXS_INTR (0x0001<<3)
989#define TX_TRAFFIC_INTR (0x0001<<4)
990#define RX_PIC_INTR (0x0001<<5)
991#define RX_DMA_INTR (0x0001<<6)
992#define RX_MAC_INTR (0x0001<<7)
993#define RX_XGXS_INTR (0x0001<<8)
994#define RX_TRAFFIC_INTR (0x0001<<9)
995#define MC_INTR (0x0001<<10)
996#define ENA_ALL_INTRS ( TX_PIC_INTR | \
997 TX_DMA_INTR | \
998 TX_MAC_INTR | \
999 TX_XGXS_INTR | \
1000 TX_TRAFFIC_INTR | \
1001 RX_PIC_INTR | \
1002 RX_DMA_INTR | \
1003 RX_MAC_INTR | \
1004 RX_XGXS_INTR | \
1005 RX_TRAFFIC_INTR | \
1006 MC_INTR )
1007
1008/* Interrupt masks for the general interrupt mask register */
1009#define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL
1010
1011#define TXPIC_INT_M s2BIT(0)
1012#define TXDMA_INT_M s2BIT(1)
1013#define TXMAC_INT_M s2BIT(2)
1014#define TXXGXS_INT_M s2BIT(3)
1015#define TXTRAFFIC_INT_M s2BIT(8)
1016#define PIC_RX_INT_M s2BIT(32)
1017#define RXDMA_INT_M s2BIT(33)
1018#define RXMAC_INT_M s2BIT(34)
1019#define MC_INT_M s2BIT(35)
1020#define RXXGXS_INT_M s2BIT(36)
1021#define RXTRAFFIC_INT_M s2BIT(40)
1022
1023/* PIC level Interrupts TODO*/
1024
1025/* DMA level Inressupts */
1026#define TXDMA_PFC_INT_M s2BIT(0)
1027#define TXDMA_PCC_INT_M s2BIT(2)
1028
1029/* PFC block interrupts */
1030#define PFC_MISC_ERR_1 s2BIT(0) /* Interrupt to indicate FIFO full */
1031
1032/* PCC block interrupts. */
1033#define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate
1034 PCC_FB_ECC Error. */
1035
1036#define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
1037/*
1038 * Prototype declaration.
1039 */
1040static int __devinit s2io_init_nic(struct pci_dev *pdev,
1041 const struct pci_device_id *pre);
1042static void __devexit s2io_rem_nic(struct pci_dev *pdev);
1043static int init_shared_mem(struct s2io_nic *sp);
1044static void free_shared_mem(struct s2io_nic *sp);
1045static int init_nic(struct s2io_nic *nic);
1046static void rx_intr_handler(struct ring_info *ring_data);
1047static void tx_intr_handler(struct fifo_info *fifo_data);
1048static void s2io_handle_errors(void * dev_id);
1049
1050static int s2io_starter(void);
1051static void s2io_closer(void);
1052static void s2io_tx_watchdog(struct net_device *dev);
1053static void s2io_tasklet(unsigned long dev_addr);
1054static void s2io_set_multicast(struct net_device *dev);
1055static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp);
1056static void s2io_link(struct s2io_nic * sp, int link);
1057static void s2io_reset(struct s2io_nic * sp);
1058static int s2io_poll(struct napi_struct *napi, int budget);
1059static void s2io_init_pci(struct s2io_nic * sp);
1060static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr);
1061static void s2io_alarm_handle(unsigned long data);
1062static irqreturn_t
1063s2io_msix_ring_handle(int irq, void *dev_id);
1064static irqreturn_t
1065s2io_msix_fifo_handle(int irq, void *dev_id);
1066static irqreturn_t s2io_isr(int irq, void *dev_id);
1067static int verify_xena_quiescence(struct s2io_nic *sp);
1068static const struct ethtool_ops netdev_ethtool_ops;
1069static void s2io_set_link(struct work_struct *work);
1070static int s2io_set_swapper(struct s2io_nic * sp);
1071static void s2io_card_down(struct s2io_nic *nic);
1072static int s2io_card_up(struct s2io_nic *nic);
1073static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
1074 int bit_state);
1075static int s2io_add_isr(struct s2io_nic * sp);
1076static void s2io_rem_isr(struct s2io_nic * sp);
1077
1078static void restore_xmsi_data(struct s2io_nic *nic);
1079static void do_s2io_store_unicast_mc(struct s2io_nic *sp);
1080static void do_s2io_restore_unicast_mc(struct s2io_nic *sp);
1081static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset);
1082static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr);
1083static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int offset);
1084static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr);
1085
1086static int
1087s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
1088 struct RxD_t *rxdp, struct s2io_nic *sp);
1089static void clear_lro_session(struct lro *lro);
1090static void queue_rx_frame(struct sk_buff *skb);
1091static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro);
1092static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
1093 struct sk_buff *skb, u32 tcp_len);
1094static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring);
1095
1096static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
1097 pci_channel_state_t state);
1098static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev);
1099static void s2io_io_resume(struct pci_dev *pdev);
1100
1101#define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size
1102#define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size
1103#define s2io_offload_type(skb) skb_shinfo(skb)->gso_type
1104
1105#define S2IO_PARM_INT(X, def_val) \
1106 static unsigned int X = def_val;\
1107 module_param(X , uint, 0);
1108
1109#endif /* _S2IO_H */