tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _IXGBE_H_
30#define _IXGBE_H_
31
32#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/netdevice.h>
35
36#include "ixgbe_type.h"
37#include "ixgbe_common.h"
38
39
40#define IXGBE_ERR(args...) printk(KERN_ERR "ixgbe: " args)
41
42#define PFX "ixgbe: "
43#define DPRINTK(nlevel, klevel, fmt, args...) \
44 ((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
45 printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
46 __FUNCTION__ , ## args)))
47
48/* TX/RX descriptor defines */
49#define IXGBE_DEFAULT_TXD 1024
50#define IXGBE_MAX_TXD 4096
51#define IXGBE_MIN_TXD 64
52
53#define IXGBE_DEFAULT_RXD 1024
54#define IXGBE_MAX_RXD 4096
55#define IXGBE_MIN_RXD 64
56
57#define IXGBE_DEFAULT_RXQ 1
58#define IXGBE_MAX_RXQ 1
59#define IXGBE_MIN_RXQ 1
60
61#define IXGBE_DEFAULT_ITR_RX_USECS 125 /* 8k irqs/sec */
62#define IXGBE_DEFAULT_ITR_TX_USECS 250 /* 4k irqs/sec */
63#define IXGBE_MIN_ITR_USECS 100 /* 500k irqs/sec */
64#define IXGBE_MAX_ITR_USECS 10000 /* 100 irqs/sec */
65
66/* flow control */
67#define IXGBE_DEFAULT_FCRTL 0x10000
68#define IXGBE_MIN_FCRTL 0
69#define IXGBE_MAX_FCRTL 0x7FF80
70#define IXGBE_DEFAULT_FCRTH 0x20000
71#define IXGBE_MIN_FCRTH 0
72#define IXGBE_MAX_FCRTH 0x7FFF0
73#define IXGBE_DEFAULT_FCPAUSE 0x6800 /* may be too long */
74#define IXGBE_MIN_FCPAUSE 0
75#define IXGBE_MAX_FCPAUSE 0xFFFF
76
77/* Supported Rx Buffer Sizes */
78#define IXGBE_RXBUFFER_64 64 /* Used for packet split */
79#define IXGBE_RXBUFFER_128 128 /* Used for packet split */
80#define IXGBE_RXBUFFER_256 256 /* Used for packet split */
81#define IXGBE_RXBUFFER_2048 2048
82
83#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
84
85#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
86
87/* How many Tx Descriptors do we need to call netif_wake_queue? */
88#define IXGBE_TX_QUEUE_WAKE 16
89
90/* How many Rx Buffers do we bundle into one write to the hardware ? */
91#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
92
93#define IXGBE_TX_FLAGS_CSUM (u32)(1)
94#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
95#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
96#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
97#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
98#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
99
100/* wrapper around a pointer to a socket buffer,
101 * so a DMA handle can be stored along with the buffer */
102struct ixgbe_tx_buffer {
103 struct sk_buff *skb;
104 dma_addr_t dma;
105 unsigned long time_stamp;
106 u16 length;
107 u16 next_to_watch;
108};
109
110struct ixgbe_rx_buffer {
111 struct sk_buff *skb;
112 dma_addr_t dma;
113 struct page *page;
114 dma_addr_t page_dma;
115};
116
117struct ixgbe_queue_stats {
118 u64 packets;
119 u64 bytes;
120};
121
122struct ixgbe_ring {
123 struct ixgbe_adapter *adapter; /* backlink */
124 void *desc; /* descriptor ring memory */
125 dma_addr_t dma; /* phys. address of descriptor ring */
126 unsigned int size; /* length in bytes */
127 unsigned int count; /* amount of descriptors */
128 unsigned int next_to_use;
129 unsigned int next_to_clean;
130
131 union {
132 struct ixgbe_tx_buffer *tx_buffer_info;
133 struct ixgbe_rx_buffer *rx_buffer_info;
134 };
135
136 u16 head;
137 u16 tail;
138
139 /* To protect race between sender and clean_tx_irq */
140 spinlock_t tx_lock;
141
142 struct ixgbe_queue_stats stats;
143
144 u32 eims_value;
145 u16 itr_register;
146
147 char name[IFNAMSIZ + 5];
148 u16 work_limit; /* max work per interrupt */
149};
150
151/* Helper macros to switch between ints/sec and what the register uses.
152 * And yes, it's the same math going both ways.
153 */
154#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
155 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 0)
156#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
157
158#define IXGBE_DESC_UNUSED(R) \
159 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
160 (R)->next_to_clean - (R)->next_to_use - 1)
161
162#define IXGBE_RX_DESC_ADV(R, i) \
163 (&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
164#define IXGBE_TX_DESC_ADV(R, i) \
165 (&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
166#define IXGBE_TX_CTXTDESC_ADV(R, i) \
167 (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
168
169#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
170
171/* board specific private data structure */
172struct ixgbe_adapter {
173 struct timer_list watchdog_timer;
174 struct vlan_group *vlgrp;
175 u16 bd_number;
176 u16 rx_buf_len;
177 atomic_t irq_sem;
178 struct work_struct reset_task;
179
180 /* TX */
181 struct ixgbe_ring *tx_ring; /* One per active queue */
182 struct napi_struct napi;
183 u64 restart_queue;
184 u64 lsc_int;
185 u64 hw_tso_ctxt;
186 u64 hw_tso6_ctxt;
187 u32 tx_timeout_count;
188 bool detect_tx_hung;
189
190 /* RX */
191 struct ixgbe_ring *rx_ring; /* One per active queue */
192 u64 hw_csum_tx_good;
193 u64 hw_csum_rx_error;
194 u64 hw_csum_rx_good;
195 u64 non_eop_descs;
196 int num_tx_queues;
197 int num_rx_queues;
198 struct msix_entry *msix_entries;
199
200 u64 rx_hdr_split;
201 u32 alloc_rx_page_failed;
202 u32 alloc_rx_buff_failed;
203
204 u32 flags;
205#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
206#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1)
207#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 2)
208#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 3)
209#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 4)
210
211 /* Interrupt Throttle Rate */
212 u32 rx_eitr;
213 u32 tx_eitr;
214
215 /* OS defined structs */
216 struct net_device *netdev;
217 struct pci_dev *pdev;
218 struct net_device_stats net_stats;
219
220 /* structs defined in ixgbe_hw.h */
221 struct ixgbe_hw hw;
222 u16 msg_enable;
223 struct ixgbe_hw_stats stats;
224 char lsc_name[IFNAMSIZ + 5];
225
226 unsigned long state;
227 u64 tx_busy;
228};
229
230enum ixbge_state_t {
231 __IXGBE_TESTING,
232 __IXGBE_RESETTING,
233 __IXGBE_DOWN
234};
235
236enum ixgbe_boards {
237 board_82598,
238};
239
240extern struct ixgbe_info ixgbe_82598_info;
241
242extern char ixgbe_driver_name[];
243extern const char ixgbe_driver_version[];
244
245extern int ixgbe_up(struct ixgbe_adapter *adapter);
246extern void ixgbe_down(struct ixgbe_adapter *adapter);
247extern void ixgbe_reset(struct ixgbe_adapter *adapter);
248extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
249extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
250extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
251 struct ixgbe_ring *rxdr);
252extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
253 struct ixgbe_ring *txdr);
254
255#endif /* _IXGBE_H_ */