tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
4 *
5 * This is a look-alike variation of the ICH0 PIIX4 Ultra-66,
6 * but this keeps the ISA-Bridge and slots alive.
7 *
8 */
9
10#include <linux/types.h>
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/ioport.h>
14#include <linux/pci.h>
15#include <linux/hdreg.h>
16#include <linux/ide.h>
17#include <linux/delay.h>
18#include <linux/init.h>
19
20#include <asm/io.h>
21
22static DEFINE_SPINLOCK(slc90e66_lock);
23
24static void slc90e66_set_pio_mode(ide_drive_t *drive, const u8 pio)
25{
26 ide_hwif_t *hwif = HWIF(drive);
27 struct pci_dev *dev = to_pci_dev(hwif->dev);
28 int is_slave = drive->dn & 1;
29 int master_port = hwif->channel ? 0x42 : 0x40;
30 int slave_port = 0x44;
31 unsigned long flags;
32 u16 master_data;
33 u8 slave_data;
34 int control = 0;
35 /* ISP RTC */
36 static const u8 timings[][2]= {
37 { 0, 0 },
38 { 0, 0 },
39 { 1, 0 },
40 { 2, 1 },
41 { 2, 3 }, };
42
43 spin_lock_irqsave(&slc90e66_lock, flags);
44 pci_read_config_word(dev, master_port, &master_data);
45
46 if (pio > 1)
47 control |= 1; /* Programmable timing on */
48 if (drive->media == ide_disk)
49 control |= 4; /* Prefetch, post write */
50 if (pio > 2)
51 control |= 2; /* IORDY */
52 if (is_slave) {
53 master_data |= 0x4000;
54 master_data &= ~0x0070;
55 if (pio > 1) {
56 /* Set PPE, IE and TIME */
57 master_data |= control << 4;
58 }
59 pci_read_config_byte(dev, slave_port, &slave_data);
60 slave_data &= hwif->channel ? 0x0f : 0xf0;
61 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
62 (hwif->channel ? 4 : 0);
63 } else {
64 master_data &= ~0x3307;
65 if (pio > 1) {
66 /* enable PPE, IE and TIME */
67 master_data |= control;
68 }
69 master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
70 }
71 pci_write_config_word(dev, master_port, master_data);
72 if (is_slave)
73 pci_write_config_byte(dev, slave_port, slave_data);
74 spin_unlock_irqrestore(&slc90e66_lock, flags);
75}
76
77static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed)
78{
79 ide_hwif_t *hwif = HWIF(drive);
80 struct pci_dev *dev = to_pci_dev(hwif->dev);
81 u8 maslave = hwif->channel ? 0x42 : 0x40;
82 int sitre = 0, a_speed = 7 << (drive->dn * 4);
83 int u_speed = 0, u_flag = 1 << drive->dn;
84 u16 reg4042, reg44, reg48, reg4a;
85
86 pci_read_config_word(dev, maslave, ®4042);
87 sitre = (reg4042 & 0x4000) ? 1 : 0;
88 pci_read_config_word(dev, 0x44, ®44);
89 pci_read_config_word(dev, 0x48, ®48);
90 pci_read_config_word(dev, 0x4a, ®4a);
91
92 if (speed >= XFER_UDMA_0) {
93 u_speed = (speed - XFER_UDMA_0) << (drive->dn * 4);
94
95 if (!(reg48 & u_flag))
96 pci_write_config_word(dev, 0x48, reg48|u_flag);
97 /* FIXME: (reg4a & a_speed) ? */
98 if ((reg4a & u_speed) != u_speed) {
99 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
100 pci_read_config_word(dev, 0x4a, ®4a);
101 pci_write_config_word(dev, 0x4a, reg4a|u_speed);
102 }
103 } else {
104 const u8 mwdma_to_pio[] = { 0, 3, 4 };
105 u8 pio;
106
107 if (reg48 & u_flag)
108 pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
109 if (reg4a & a_speed)
110 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
111
112 if (speed >= XFER_MW_DMA_0)
113 pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
114 else
115 pio = 2; /* only SWDMA2 is allowed */
116
117 slc90e66_set_pio_mode(drive, pio);
118 }
119}
120
121static void __devinit init_hwif_slc90e66 (ide_hwif_t *hwif)
122{
123 struct pci_dev *dev = to_pci_dev(hwif->dev);
124 u8 reg47 = 0;
125 u8 mask = hwif->channel ? 0x01 : 0x02; /* bit0:Primary */
126
127 hwif->set_pio_mode = &slc90e66_set_pio_mode;
128 hwif->set_dma_mode = &slc90e66_set_dma_mode;
129
130 pci_read_config_byte(dev, 0x47, ®47);
131
132 if (hwif->dma_base == 0)
133 return;
134
135 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
136 /* bit[0(1)]: 0:80, 1:40 */
137 hwif->cbl = (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
138}
139
140static const struct ide_port_info slc90e66_chipset __devinitdata = {
141 .name = "SLC90E66",
142 .init_hwif = init_hwif_slc90e66,
143 .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
144 .host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_BOOTABLE,
145 .pio_mask = ATA_PIO4,
146 .swdma_mask = ATA_SWDMA2_ONLY,
147 .mwdma_mask = ATA_MWDMA12_ONLY,
148 .udma_mask = ATA_UDMA4,
149};
150
151static int __devinit slc90e66_init_one(struct pci_dev *dev, const struct pci_device_id *id)
152{
153 return ide_setup_pci_device(dev, &slc90e66_chipset);
154}
155
156static const struct pci_device_id slc90e66_pci_tbl[] = {
157 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0 },
158 { 0, },
159};
160MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);
161
162static struct pci_driver driver = {
163 .name = "SLC90e66_IDE",
164 .id_table = slc90e66_pci_tbl,
165 .probe = slc90e66_init_one,
166};
167
168static int __init slc90e66_ide_init(void)
169{
170 return ide_pci_register_driver(&driver);
171}
172
173module_init(slc90e66_ide_init);
174
175MODULE_AUTHOR("Andre Hedrick");
176MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
177MODULE_LICENSE("GPL");