tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/*
2 * arch/ppc/boot/include/mpsc_defs.h
3 *
4 * Register definitions for the Marvell Multi-Protocol Serial Controller (MPSC),
5 * Serial DMA Controller (SDMA), and Baud Rate Generator (BRG).
6 *
7 * Author: Mark A. Greer <mgreer@mvista.com>
8 *
9 * 2004 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14#ifndef _PPC_BOOT_MPSC_DEFS_H__
15#define _PPC_BOOT_MPSC_DEFS_H__
16
17#define MPSC_NUM_CTLRS 2
18
19/*
20 *****************************************************************************
21 *
22 * Multi-Protocol Serial Controller Interface Registers
23 *
24 *****************************************************************************
25 */
26
27/* Main Configuratino Register Offsets */
28#define MPSC_MMCRL 0x0000
29#define MPSC_MMCRH 0x0004
30#define MPSC_MPCR 0x0008
31#define MPSC_CHR_1 0x000c
32#define MPSC_CHR_2 0x0010
33#define MPSC_CHR_3 0x0014
34#define MPSC_CHR_4 0x0018
35#define MPSC_CHR_5 0x001c
36#define MPSC_CHR_6 0x0020
37#define MPSC_CHR_7 0x0024
38#define MPSC_CHR_8 0x0028
39#define MPSC_CHR_9 0x002c
40#define MPSC_CHR_10 0x0030
41#define MPSC_CHR_11 0x0034
42
43#define MPSC_MPCR_CL_5 0
44#define MPSC_MPCR_CL_6 1
45#define MPSC_MPCR_CL_7 2
46#define MPSC_MPCR_CL_8 3
47#define MPSC_MPCR_SBL_1 0
48#define MPSC_MPCR_SBL_2 3
49
50#define MPSC_CHR_2_TEV (1<<1)
51#define MPSC_CHR_2_TA (1<<7)
52#define MPSC_CHR_2_TTCS (1<<9)
53#define MPSC_CHR_2_REV (1<<17)
54#define MPSC_CHR_2_RA (1<<23)
55#define MPSC_CHR_2_CRD (1<<25)
56#define MPSC_CHR_2_EH (1<<31)
57#define MPSC_CHR_2_PAR_ODD 0
58#define MPSC_CHR_2_PAR_SPACE 1
59#define MPSC_CHR_2_PAR_EVEN 2
60#define MPSC_CHR_2_PAR_MARK 3
61
62/* MPSC Signal Routing */
63#define MPSC_MRR 0x0000
64#define MPSC_RCRR 0x0004
65#define MPSC_TCRR 0x0008
66
67/*
68 *****************************************************************************
69 *
70 * Serial DMA Controller Interface Registers
71 *
72 *****************************************************************************
73 */
74
75#define SDMA_SDC 0x0000
76#define SDMA_SDCM 0x0008
77#define SDMA_RX_DESC 0x0800
78#define SDMA_RX_BUF_PTR 0x0808
79#define SDMA_SCRDP 0x0810
80#define SDMA_TX_DESC 0x0c00
81#define SDMA_SCTDP 0x0c10
82#define SDMA_SFTDP 0x0c14
83
84#define SDMA_DESC_CMDSTAT_PE (1<<0)
85#define SDMA_DESC_CMDSTAT_CDL (1<<1)
86#define SDMA_DESC_CMDSTAT_FR (1<<3)
87#define SDMA_DESC_CMDSTAT_OR (1<<6)
88#define SDMA_DESC_CMDSTAT_BR (1<<9)
89#define SDMA_DESC_CMDSTAT_MI (1<<10)
90#define SDMA_DESC_CMDSTAT_A (1<<11)
91#define SDMA_DESC_CMDSTAT_AM (1<<12)
92#define SDMA_DESC_CMDSTAT_CT (1<<13)
93#define SDMA_DESC_CMDSTAT_C (1<<14)
94#define SDMA_DESC_CMDSTAT_ES (1<<15)
95#define SDMA_DESC_CMDSTAT_L (1<<16)
96#define SDMA_DESC_CMDSTAT_F (1<<17)
97#define SDMA_DESC_CMDSTAT_P (1<<18)
98#define SDMA_DESC_CMDSTAT_EI (1<<23)
99#define SDMA_DESC_CMDSTAT_O (1<<31)
100
101#define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O | \
102 SDMA_DESC_CMDSTAT_EI)
103
104#define SDMA_SDC_RFT (1<<0)
105#define SDMA_SDC_SFM (1<<1)
106#define SDMA_SDC_BLMR (1<<6)
107#define SDMA_SDC_BLMT (1<<7)
108#define SDMA_SDC_POVR (1<<8)
109#define SDMA_SDC_RIFB (1<<9)
110
111#define SDMA_SDCM_ERD (1<<7)
112#define SDMA_SDCM_AR (1<<15)
113#define SDMA_SDCM_STD (1<<16)
114#define SDMA_SDCM_TXD (1<<23)
115#define SDMA_SDCM_AT (1<<31)
116
117#define SDMA_0_CAUSE_RXBUF (1<<0)
118#define SDMA_0_CAUSE_RXERR (1<<1)
119#define SDMA_0_CAUSE_TXBUF (1<<2)
120#define SDMA_0_CAUSE_TXEND (1<<3)
121#define SDMA_1_CAUSE_RXBUF (1<<8)
122#define SDMA_1_CAUSE_RXERR (1<<9)
123#define SDMA_1_CAUSE_TXBUF (1<<10)
124#define SDMA_1_CAUSE_TXEND (1<<11)
125
126#define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR | \
127 SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
128#define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND | \
129 SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
130
131/* SDMA Interrupt registers */
132#define SDMA_INTR_CAUSE 0x0000
133#define SDMA_INTR_MASK 0x0080
134
135/*
136 *****************************************************************************
137 *
138 * Baud Rate Generator Interface Registers
139 *
140 *****************************************************************************
141 */
142
143#define BRG_BCR 0x0000
144#define BRG_BTR 0x0004
145
146#endif /*_PPC_BOOT_MPSC_DEFS_H__ */