tjh.dev
Linux kernel mirror (for testing)
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linux
1/*
2 * ibm_ocp.h
3 *
4 * (c) Benjamin Herrenschmidt (benh@kernel.crashing.org)
5 * Mipsys - France
6 *
7 * Derived from work (c) Armin Kuster akuster@pacbell.net
8 *
9 * Additional support and port to 2.6 LDM/sysfs by
10 * Matt Porter <mporter@kernel.crashing.org>
11 * Copyright 2003-2004 MontaVista Software, Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19#ifdef __KERNEL__
20#ifndef __IBM_OCP_H__
21#define __IBM_OCP_H__
22
23#include <asm/types.h>
24
25/*
26 * IBM 4xx OCP system information
27 */
28struct ocp_sys_info_data {
29 int opb_bus_freq; /* OPB Bus Frequency (Hz) */
30 int ebc_bus_freq; /* EBC Bus Frequency (Hz) */
31};
32
33extern struct ocp_sys_info_data ocp_sys_info;
34
35/*
36 * EMAC additional data and sysfs support
37 *
38 * Note about mdio_idx: When you have a zmii, it's usually
39 * not necessary, it covers the case of the 405EP which has
40 * the MDIO lines on EMAC0 only
41 *
42 * Note about phy_map: Per EMAC map of PHY ids which should
43 * be probed by emac_probe. Different EMACs can have
44 * overlapping maps.
45 *
46 * Note, this map uses inverse logic for bits:
47 * 0 - id should be probed
48 * 1 - id should be ignored
49 *
50 * Default value of 0x00000000 - will result in usual
51 * auto-detection logic.
52 *
53 */
54
55struct ocp_func_emac_data {
56 int rgmii_idx; /* RGMII device index or -1 */
57 int rgmii_mux; /* RGMII input of this EMAC */
58 int zmii_idx; /* ZMII device index or -1 */
59 int zmii_mux; /* ZMII input of this EMAC */
60 int mal_idx; /* MAL device index */
61 int mal_rx_chan; /* MAL rx channel number */
62 int mal_tx_chan; /* MAL tx channel number */
63 int wol_irq; /* WOL interrupt */
64 int mdio_idx; /* EMAC idx of MDIO master or -1 */
65 int tah_idx; /* TAH device index or -1 */
66 int jumbo; /* Jumbo frames capable flag */
67 int phy_mode; /* PHY type or configurable mode */
68 u8 mac_addr[6]; /* EMAC mac address */
69 u32 phy_map; /* EMAC phy map */
70 u32 phy_feat_exc; /* Excluded PHY features */
71};
72
73/* Sysfs support */
74#define OCP_SYSFS_EMAC_DATA() \
75OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_idx) \
76OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_mux) \
77OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_idx) \
78OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_mux) \
79OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_idx) \
80OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_rx_chan) \
81OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_tx_chan) \
82OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, wol_irq) \
83OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mdio_idx) \
84OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, tah_idx) \
85OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, phy_mode) \
86OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "0x%08x\n", emac, phy_map) \
87OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "0x%08x\n", emac, phy_feat_exc)\
88 \
89void ocp_show_emac_data(struct device *dev) \
90{ \
91 device_create_file(dev, &dev_attr_emac_rgmii_idx); \
92 device_create_file(dev, &dev_attr_emac_rgmii_mux); \
93 device_create_file(dev, &dev_attr_emac_zmii_idx); \
94 device_create_file(dev, &dev_attr_emac_zmii_mux); \
95 device_create_file(dev, &dev_attr_emac_mal_idx); \
96 device_create_file(dev, &dev_attr_emac_mal_rx_chan); \
97 device_create_file(dev, &dev_attr_emac_mal_tx_chan); \
98 device_create_file(dev, &dev_attr_emac_wol_irq); \
99 device_create_file(dev, &dev_attr_emac_mdio_idx); \
100 device_create_file(dev, &dev_attr_emac_tah_idx); \
101 device_create_file(dev, &dev_attr_emac_phy_mode); \
102 device_create_file(dev, &dev_attr_emac_phy_map); \
103 device_create_file(dev, &dev_attr_emac_phy_feat_exc); \
104}
105
106/*
107 * PHY mode settings (EMAC <-> ZMII/RGMII bridge <-> PHY)
108 */
109#define PHY_MODE_NA 0
110#define PHY_MODE_MII 1
111#define PHY_MODE_RMII 2
112#define PHY_MODE_SMII 3
113#define PHY_MODE_RGMII 4
114#define PHY_MODE_TBI 5
115#define PHY_MODE_GMII 6
116#define PHY_MODE_RTBI 7
117#define PHY_MODE_SGMII 8
118
119#ifdef CONFIG_40x
120/*
121 * Helper function to copy MAC addresses from the bd_t to OCP EMAC
122 * additions.
123 *
124 * The range of EMAC indices (inclusive) to be copied are the arguments.
125 */
126static inline void ibm_ocp_set_emac(int start, int end)
127{
128 int i;
129 struct ocp_def *def;
130
131 /* Copy MAC addresses to EMAC additions */
132 for (i=start; i<=end; i++) {
133 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
134 memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr,
135 &__res.bi_enetaddr[i],
136 6);
137 }
138}
139#endif
140
141/*
142 * MAL additional data and sysfs support
143 */
144struct ocp_func_mal_data {
145 int num_tx_chans; /* Number of TX channels */
146 int num_rx_chans; /* Number of RX channels */
147 int txeob_irq; /* TX End Of Buffer IRQ */
148 int rxeob_irq; /* RX End Of Buffer IRQ */
149 int txde_irq; /* TX Descriptor Error IRQ */
150 int rxde_irq; /* RX Descriptor Error IRQ */
151 int serr_irq; /* MAL System Error IRQ */
152 int dcr_base; /* MALx_CFG DCR number */
153};
154
155#define OCP_SYSFS_MAL_DATA() \
156OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, num_tx_chans) \
157OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, num_rx_chans) \
158OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txeob_irq) \
159OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxeob_irq) \
160OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txde_irq) \
161OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxde_irq) \
162OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, serr_irq) \
163OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, dcr_base) \
164 \
165void ocp_show_mal_data(struct device *dev) \
166{ \
167 device_create_file(dev, &dev_attr_mal_num_tx_chans); \
168 device_create_file(dev, &dev_attr_mal_num_rx_chans); \
169 device_create_file(dev, &dev_attr_mal_txeob_irq); \
170 device_create_file(dev, &dev_attr_mal_rxeob_irq); \
171 device_create_file(dev, &dev_attr_mal_txde_irq); \
172 device_create_file(dev, &dev_attr_mal_rxde_irq); \
173 device_create_file(dev, &dev_attr_mal_serr_irq); \
174 device_create_file(dev, &dev_attr_mal_dcr_base); \
175}
176
177/*
178 * IIC additional data and sysfs support
179 */
180struct ocp_func_iic_data {
181 int fast_mode; /* IIC fast mode enabled */
182};
183
184#define OCP_SYSFS_IIC_DATA() \
185OCP_SYSFS_ADDTL(struct ocp_func_iic_data, "%d\n", iic, fast_mode) \
186 \
187void ocp_show_iic_data(struct device *dev) \
188{ \
189 device_create_file(dev, &dev_attr_iic_fast_mode); \
190}
191#endif /* __IBM_OCP_H__ */
192#endif /* __KERNEL__ */