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1/*
2 * include/asm-powerpc/paca.h
3 *
4 * This control block defines the PACA which defines the processor
5 * specific data for each logical processor on the system.
6 * There are some pointers defined that are utilized by PLIC.
7 *
8 * C 2001 PPC 64 Team, IBM Corp
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15#ifndef _ASM_POWERPC_PACA_H
16#define _ASM_POWERPC_PACA_H
17#ifdef __KERNEL__
18
19#include <linux/config.h>
20#include <asm/types.h>
21#include <asm/lppaca.h>
22#include <asm/mmu.h>
23
24register struct paca_struct *local_paca asm("r13");
25#define get_paca() local_paca
26
27struct task_struct;
28
29/*
30 * Defines the layout of the paca.
31 *
32 * This structure is not directly accessed by firmware or the service
33 * processor except for the first two pointers that point to the
34 * lppaca area and the ItLpRegSave area for this CPU. The lppaca
35 * object is currently contained within the PACA but it doesn't need
36 * to be.
37 */
38struct paca_struct {
39 /*
40 * Because hw_cpu_id, unlike other paca fields, is accessed
41 * routinely from other CPUs (from the IRQ code), we stick to
42 * read-only (after boot) fields in the first cacheline to
43 * avoid cacheline bouncing.
44 */
45
46 /*
47 * MAGIC: These first two pointers can't be moved - they're
48 * accessed by the firmware
49 */
50 struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */
51#ifdef CONFIG_PPC_ISERIES
52 void *reg_save_ptr; /* Pointer to LpRegSave for PLIC */
53#endif /* CONFIG_PPC_ISERIES */
54
55 /*
56 * MAGIC: the spinlock functions in arch/ppc64/lib/locks.c
57 * load lock_token and paca_index with a single lwz
58 * instruction. They must travel together and be properly
59 * aligned.
60 */
61 u16 lock_token; /* Constant 0x8000, used in locks */
62 u16 paca_index; /* Logical processor number */
63
64 u64 kernel_toc; /* Kernel TOC address */
65 u64 stab_real; /* Absolute address of segment table */
66 u64 stab_addr; /* Virtual address of segment table */
67 void *emergency_sp; /* pointer to emergency stack */
68 u64 data_offset; /* per cpu data offset */
69 s16 hw_cpu_id; /* Physical processor number */
70 u8 cpu_start; /* At startup, processor spins until */
71 /* this becomes non-zero. */
72
73 /*
74 * Now, starting in cacheline 2, the exception save areas
75 */
76 /* used for most interrupts/exceptions */
77 u64 exgen[10] __attribute__((aligned(0x80)));
78 u64 exmc[10]; /* used for machine checks */
79 u64 exslb[10]; /* used for SLB/segment table misses
80 * on the linear mapping */
81#ifdef CONFIG_PPC_64K_PAGES
82 pgd_t *pgdir;
83#endif /* CONFIG_PPC_64K_PAGES */
84
85 mm_context_t context;
86 u16 slb_cache[SLB_CACHE_ENTRIES];
87 u16 slb_cache_ptr;
88
89 /*
90 * then miscellaneous read-write fields
91 */
92 struct task_struct *__current; /* Pointer to current */
93 u64 kstack; /* Saved Kernel stack addr */
94 u64 stab_rr; /* stab/slb round-robin counter */
95 u64 saved_r1; /* r1 save for RTAS calls */
96 u64 saved_msr; /* MSR saved here by enter_rtas */
97 u8 proc_enabled; /* irq soft-enable flag */
98
99 /*
100 * iSeries structure which the hypervisor knows about -
101 * this structure should not cross a page boundary.
102 * The vpa_init/register_vpa call is now known to fail if the
103 * lppaca structure crosses a page boundary.
104 * The lppaca is also used on POWER5 pSeries boxes.
105 * The lppaca is 640 bytes long, and cannot readily change
106 * since the hypervisor knows its layout, so a 1kB
107 * alignment will suffice to ensure that it doesn't
108 * cross a page boundary.
109 */
110 struct lppaca lppaca __attribute__((__aligned__(0x400)));
111};
112
113extern struct paca_struct paca[];
114
115#endif /* __KERNEL__ */
116#endif /* _ASM_POWERPC_PACA_H */