tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 */
36
37#ifndef MLX4_H
38#define MLX4_H
39
40#include <linux/mutex.h>
41#include <linux/radix-tree.h>
42#include <linux/timer.h>
43
44#include <linux/mlx4/device.h>
45#include <linux/mlx4/doorbell.h>
46
47#define DRV_NAME "mlx4_core"
48#define PFX DRV_NAME ": "
49#define DRV_VERSION "0.01"
50#define DRV_RELDATE "May 1, 2007"
51
52enum {
53 MLX4_HCR_BASE = 0x80680,
54 MLX4_HCR_SIZE = 0x0001c,
55 MLX4_CLR_INT_SIZE = 0x00008
56};
57
58enum {
59 MLX4_MGM_ENTRY_SIZE = 0x100,
60 MLX4_QP_PER_MGM = 4 * (MLX4_MGM_ENTRY_SIZE / 16 - 2),
61 MLX4_MTT_ENTRY_PER_SEG = 8
62};
63
64enum {
65 MLX4_EQ_ASYNC,
66 MLX4_EQ_COMP,
67 MLX4_NUM_EQ
68};
69
70enum {
71 MLX4_NUM_PDS = 1 << 15
72};
73
74enum {
75 MLX4_CMPT_TYPE_QP = 0,
76 MLX4_CMPT_TYPE_SRQ = 1,
77 MLX4_CMPT_TYPE_CQ = 2,
78 MLX4_CMPT_TYPE_EQ = 3,
79 MLX4_CMPT_NUM_TYPE
80};
81
82enum {
83 MLX4_CMPT_SHIFT = 24,
84 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
85};
86
87#ifdef CONFIG_MLX4_DEBUG
88extern int mlx4_debug_level;
89
90#define mlx4_dbg(mdev, format, arg...) \
91 do { \
92 if (mlx4_debug_level) \
93 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ## arg); \
94 } while (0)
95
96#else /* CONFIG_MLX4_DEBUG */
97
98#define mlx4_dbg(mdev, format, arg...) do { (void) mdev; } while (0)
99
100#endif /* CONFIG_MLX4_DEBUG */
101
102#define mlx4_err(mdev, format, arg...) \
103 dev_err(&mdev->pdev->dev, format, ## arg)
104#define mlx4_info(mdev, format, arg...) \
105 dev_info(&mdev->pdev->dev, format, ## arg)
106#define mlx4_warn(mdev, format, arg...) \
107 dev_warn(&mdev->pdev->dev, format, ## arg)
108
109struct mlx4_bitmap {
110 u32 last;
111 u32 top;
112 u32 max;
113 u32 mask;
114 spinlock_t lock;
115 unsigned long *table;
116};
117
118struct mlx4_buddy {
119 unsigned long **bits;
120 int max_order;
121 spinlock_t lock;
122};
123
124struct mlx4_icm;
125
126struct mlx4_icm_table {
127 u64 virt;
128 int num_icm;
129 int num_obj;
130 int obj_size;
131 int lowmem;
132 int coherent;
133 struct mutex mutex;
134 struct mlx4_icm **icm;
135};
136
137struct mlx4_eq {
138 struct mlx4_dev *dev;
139 void __iomem *doorbell;
140 int eqn;
141 u32 cons_index;
142 u16 irq;
143 u16 have_irq;
144 int nent;
145 struct mlx4_buf_list *page_list;
146 struct mlx4_mtt mtt;
147};
148
149struct mlx4_profile {
150 int num_qp;
151 int rdmarc_per_qp;
152 int num_srq;
153 int num_cq;
154 int num_mcg;
155 int num_mpt;
156 int num_mtt;
157};
158
159struct mlx4_fw {
160 u64 clr_int_base;
161 u64 catas_offset;
162 struct mlx4_icm *fw_icm;
163 struct mlx4_icm *aux_icm;
164 u32 catas_size;
165 u16 fw_pages;
166 u8 clr_int_bar;
167 u8 catas_bar;
168};
169
170struct mlx4_cmd {
171 struct pci_pool *pool;
172 void __iomem *hcr;
173 struct mutex hcr_mutex;
174 struct semaphore poll_sem;
175 struct semaphore event_sem;
176 int max_cmds;
177 spinlock_t context_lock;
178 int free_head;
179 struct mlx4_cmd_context *context;
180 u16 token_mask;
181 u8 use_events;
182 u8 toggle;
183};
184
185struct mlx4_uar_table {
186 struct mlx4_bitmap bitmap;
187};
188
189struct mlx4_mr_table {
190 struct mlx4_bitmap mpt_bitmap;
191 struct mlx4_buddy mtt_buddy;
192 u64 mtt_base;
193 u64 mpt_base;
194 struct mlx4_icm_table mtt_table;
195 struct mlx4_icm_table dmpt_table;
196};
197
198struct mlx4_cq_table {
199 struct mlx4_bitmap bitmap;
200 spinlock_t lock;
201 struct radix_tree_root tree;
202 struct mlx4_icm_table table;
203 struct mlx4_icm_table cmpt_table;
204};
205
206struct mlx4_eq_table {
207 struct mlx4_bitmap bitmap;
208 void __iomem *clr_int;
209 void __iomem *uar_map[(MLX4_NUM_EQ + 6) / 4];
210 u32 clr_mask;
211 struct mlx4_eq eq[MLX4_NUM_EQ];
212 u64 icm_virt;
213 struct page *icm_page;
214 dma_addr_t icm_dma;
215 struct mlx4_icm_table cmpt_table;
216 int have_irq;
217 u8 inta_pin;
218};
219
220struct mlx4_srq_table {
221 struct mlx4_bitmap bitmap;
222 spinlock_t lock;
223 struct radix_tree_root tree;
224 struct mlx4_icm_table table;
225 struct mlx4_icm_table cmpt_table;
226};
227
228struct mlx4_qp_table {
229 struct mlx4_bitmap bitmap;
230 u32 rdmarc_base;
231 int rdmarc_shift;
232 spinlock_t lock;
233 struct mlx4_icm_table qp_table;
234 struct mlx4_icm_table auxc_table;
235 struct mlx4_icm_table altc_table;
236 struct mlx4_icm_table rdmarc_table;
237 struct mlx4_icm_table cmpt_table;
238};
239
240struct mlx4_mcg_table {
241 struct mutex mutex;
242 struct mlx4_bitmap bitmap;
243 struct mlx4_icm_table table;
244};
245
246struct mlx4_catas_err {
247 u32 __iomem *map;
248 struct timer_list timer;
249 struct list_head list;
250};
251
252struct mlx4_priv {
253 struct mlx4_dev dev;
254
255 struct list_head dev_list;
256 struct list_head ctx_list;
257 spinlock_t ctx_lock;
258
259 struct mlx4_fw fw;
260 struct mlx4_cmd cmd;
261
262 struct mlx4_bitmap pd_bitmap;
263 struct mlx4_uar_table uar_table;
264 struct mlx4_mr_table mr_table;
265 struct mlx4_cq_table cq_table;
266 struct mlx4_eq_table eq_table;
267 struct mlx4_srq_table srq_table;
268 struct mlx4_qp_table qp_table;
269 struct mlx4_mcg_table mcg_table;
270
271 struct mlx4_catas_err catas_err;
272
273 void __iomem *clr_base;
274
275 struct mlx4_uar driver_uar;
276 void __iomem *kar;
277};
278
279static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
280{
281 return container_of(dev, struct mlx4_priv, dev);
282}
283
284u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
285void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
286int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, u32 reserved);
287void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
288
289int mlx4_reset(struct mlx4_dev *dev);
290
291int mlx4_init_pd_table(struct mlx4_dev *dev);
292int mlx4_init_uar_table(struct mlx4_dev *dev);
293int mlx4_init_mr_table(struct mlx4_dev *dev);
294int mlx4_init_eq_table(struct mlx4_dev *dev);
295int mlx4_init_cq_table(struct mlx4_dev *dev);
296int mlx4_init_qp_table(struct mlx4_dev *dev);
297int mlx4_init_srq_table(struct mlx4_dev *dev);
298int mlx4_init_mcg_table(struct mlx4_dev *dev);
299
300void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
301void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
302void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
303void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
304void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
305void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
306void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
307void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
308
309void mlx4_start_catas_poll(struct mlx4_dev *dev);
310void mlx4_stop_catas_poll(struct mlx4_dev *dev);
311int mlx4_catas_init(void);
312void mlx4_catas_cleanup(void);
313int mlx4_restart_one(struct pci_dev *pdev);
314int mlx4_register_device(struct mlx4_dev *dev);
315void mlx4_unregister_device(struct mlx4_dev *dev);
316void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_event type,
317 int subtype, int port);
318
319struct mlx4_dev_cap;
320struct mlx4_init_hca_param;
321
322u64 mlx4_make_profile(struct mlx4_dev *dev,
323 struct mlx4_profile *request,
324 struct mlx4_dev_cap *dev_cap,
325 struct mlx4_init_hca_param *init_hca);
326
327int mlx4_map_eq_icm(struct mlx4_dev *dev, u64 icm_virt);
328void mlx4_unmap_eq_icm(struct mlx4_dev *dev);
329
330int mlx4_cmd_init(struct mlx4_dev *dev);
331void mlx4_cmd_cleanup(struct mlx4_dev *dev);
332void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
333int mlx4_cmd_use_events(struct mlx4_dev *dev);
334void mlx4_cmd_use_polling(struct mlx4_dev *dev);
335
336void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
337void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
338
339void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
340
341void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
342
343void mlx4_handle_catas_err(struct mlx4_dev *dev);
344
345#endif /* MLX4_H */