tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1#ifndef __SAA7146__
2#define __SAA7146__
3
4#include <linux/module.h> /* for module-version */
5#include <linux/delay.h> /* for delay-stuff */
6#include <linux/slab.h> /* for kmalloc/kfree */
7#include <linux/pci.h> /* for pci-config-stuff, vendor ids etc. */
8#include <linux/init.h> /* for "__init" */
9#include <linux/interrupt.h> /* for IMMEDIATE_BH */
10#include <linux/kmod.h> /* for kernel module loader */
11#include <linux/i2c.h> /* for i2c subsystem */
12#include <asm/io.h> /* for accessing devices */
13#include <linux/stringify.h>
14#include <linux/vmalloc.h> /* for vmalloc() */
15#include <linux/mm.h> /* for vmalloc_to_page() */
16
17#define SAA7146_VERSION_CODE 0x000500 /* 0.5.0 */
18
19#define saa7146_write(sxy,adr,dat) writel((dat),(sxy->mem+(adr)))
20#define saa7146_read(sxy,adr) readl(sxy->mem+(adr))
21
22extern unsigned int saa7146_debug;
23
24//#define DEBUG_PROLOG printk("(0x%08x)(0x%08x) %s: %s(): ",(dev==0?-1:(dev->mem==0?-1:saa7146_read(dev,RPS_ADDR0))),(dev==0?-1:(dev->mem==0?-1:saa7146_read(dev,IER))),__stringify(KBUILD_MODNAME),__FUNCTION__)
25
26#ifndef DEBUG_VARIABLE
27 #define DEBUG_VARIABLE saa7146_debug
28#endif
29
30#define DEBUG_PROLOG printk("%s: %s(): ",__stringify(KBUILD_MODNAME),__FUNCTION__)
31#define INFO(x) { printk("%s: ",__stringify(KBUILD_MODNAME)); printk x; }
32
33#define ERR(x) { DEBUG_PROLOG; printk x; }
34
35#define DEB_S(x) if (0!=(DEBUG_VARIABLE&0x01)) { DEBUG_PROLOG; printk x; } /* simple debug messages */
36#define DEB_D(x) if (0!=(DEBUG_VARIABLE&0x02)) { DEBUG_PROLOG; printk x; } /* more detailed debug messages */
37#define DEB_EE(x) if (0!=(DEBUG_VARIABLE&0x04)) { DEBUG_PROLOG; printk x; } /* print enter and exit of functions */
38#define DEB_I2C(x) if (0!=(DEBUG_VARIABLE&0x08)) { DEBUG_PROLOG; printk x; } /* i2c debug messages */
39#define DEB_VBI(x) if (0!=(DEBUG_VARIABLE&0x10)) { DEBUG_PROLOG; printk x; } /* vbi debug messages */
40#define DEB_INT(x) if (0!=(DEBUG_VARIABLE&0x20)) { DEBUG_PROLOG; printk x; } /* interrupt debug messages */
41#define DEB_CAP(x) if (0!=(DEBUG_VARIABLE&0x40)) { DEBUG_PROLOG; printk x; } /* capture debug messages */
42
43#define SAA7146_IER_DISABLE(x,y) \
44 saa7146_write(x, IER, saa7146_read(x, IER) & ~(y));
45#define SAA7146_IER_ENABLE(x,y) \
46 saa7146_write(x, IER, saa7146_read(x, IER) | (y));
47#define SAA7146_ISR_CLEAR(x,y) \
48 saa7146_write(x, ISR, (y));
49
50struct saa7146_dev;
51struct saa7146_extension;
52struct saa7146_vv;
53
54/* saa7146 page table */
55struct saa7146_pgtable {
56 unsigned int size;
57 u32 *cpu;
58 dma_addr_t dma;
59 /* used for offsets for u,v planes for planar capture modes */
60 unsigned long offset;
61 /* used for custom pagetables (used for example by budget dvb cards) */
62 struct scatterlist *slist;
63};
64
65struct saa7146_pci_extension_data {
66 struct saa7146_extension *ext;
67 void *ext_priv; /* most likely a name string */
68};
69
70#define MAKE_EXTENSION_PCI(x_var, x_vendor, x_device) \
71 { \
72 .vendor = PCI_VENDOR_ID_PHILIPS, \
73 .device = PCI_DEVICE_ID_PHILIPS_SAA7146, \
74 .subvendor = x_vendor, \
75 .subdevice = x_device, \
76 .driver_data = (unsigned long)& x_var, \
77 }
78
79struct saa7146_extension
80{
81 char name[32]; /* name of the device */
82#define SAA7146_USE_I2C_IRQ 0x1
83#define SAA7146_I2C_SHORT_DELAY 0x2
84 int flags;
85
86 /* pairs of subvendor and subdevice ids for
87 supported devices, last entry 0xffff, 0xfff */
88 struct module *module;
89 struct pci_driver driver;
90 struct pci_device_id *pci_tbl;
91
92 /* extension functions */
93 int (*probe)(struct saa7146_dev *);
94 int (*attach)(struct saa7146_dev *, struct saa7146_pci_extension_data *);
95 int (*detach)(struct saa7146_dev*);
96
97 u32 irq_mask; /* mask to indicate, which irq-events are handled by the extension */
98 void (*irq_func)(struct saa7146_dev*, u32* irq_mask);
99};
100
101struct saa7146_dma
102{
103 dma_addr_t dma_handle;
104 u32 *cpu_addr;
105};
106
107struct saa7146_dev
108{
109 struct module *module;
110
111 struct list_head item;
112
113 /* different device locks */
114 spinlock_t slock;
115 struct semaphore lock;
116
117 unsigned char __iomem *mem; /* pointer to mapped IO memory */
118 int revision; /* chip revision; needed for bug-workarounds*/
119
120 /* pci-device & irq stuff*/
121 char name[32];
122 struct pci_dev *pci;
123 u32 int_todo;
124 spinlock_t int_slock;
125
126 /* extension handling */
127 struct saa7146_extension *ext; /* indicates if handled by extension */
128 void *ext_priv; /* pointer for extension private use (most likely some private data) */
129 struct saa7146_ext_vv *ext_vv_data;
130
131 /* per device video/vbi informations (if available) */
132 struct saa7146_vv *vv_data;
133 void (*vv_callback)(struct saa7146_dev *dev, unsigned long status);
134
135 /* i2c-stuff */
136 struct semaphore i2c_lock;
137 u32 i2c_bitrate;
138 struct saa7146_dma d_i2c; /* pointer to i2c memory */
139 wait_queue_head_t i2c_wq;
140 int i2c_op;
141
142 /* memories */
143 struct saa7146_dma d_rps0;
144 struct saa7146_dma d_rps1;
145};
146
147/* from saa7146_i2c.c */
148int saa7146_i2c_adapter_prepare(struct saa7146_dev *dev, struct i2c_adapter *i2c_adapter, u32 bitrate);
149int saa7146_i2c_transfer(struct saa7146_dev *saa, const struct i2c_msg *msgs, int num, int retries);
150
151/* from saa7146_core.c */
152extern struct list_head saa7146_devices;
153extern struct semaphore saa7146_devices_lock;
154int saa7146_register_extension(struct saa7146_extension*);
155int saa7146_unregister_extension(struct saa7146_extension*);
156struct saa7146_format* format_by_fourcc(struct saa7146_dev *dev, int fourcc);
157int saa7146_pgtable_alloc(struct pci_dev *pci, struct saa7146_pgtable *pt);
158void saa7146_pgtable_free(struct pci_dev *pci, struct saa7146_pgtable *pt);
159int saa7146_pgtable_build_single(struct pci_dev *pci, struct saa7146_pgtable *pt, struct scatterlist *list, int length );
160char *saa7146_vmalloc_build_pgtable(struct pci_dev *pci, long length, struct saa7146_pgtable *pt);
161void saa7146_setgpio(struct saa7146_dev *dev, int port, u32 data);
162int saa7146_wait_for_debi_done(struct saa7146_dev *dev, int nobusyloop);
163
164/* some memory sizes */
165#define SAA7146_I2C_MEM ( 1*PAGE_SIZE)
166#define SAA7146_RPS_MEM ( 1*PAGE_SIZE)
167
168/* some i2c constants */
169#define SAA7146_I2C_TIMEOUT 100 /* i2c-timeout-value in ms */
170#define SAA7146_I2C_RETRIES 3 /* how many times shall we retry an i2c-operation? */
171#define SAA7146_I2C_DELAY 5 /* time we wait after certain i2c-operations */
172
173/* unsorted defines */
174#define ME1 0x0000000800
175#define PV1 0x0000000008
176
177/* gpio defines */
178#define SAA7146_GPIO_INPUT 0x00
179#define SAA7146_GPIO_IRQHI 0x10
180#define SAA7146_GPIO_IRQLO 0x20
181#define SAA7146_GPIO_IRQHL 0x30
182#define SAA7146_GPIO_OUTLO 0x40
183#define SAA7146_GPIO_OUTHI 0x50
184
185/* debi defines */
186#define DEBINOSWAP 0x000e0000
187
188/* define for the register programming sequencer (rps) */
189#define CMD_NOP 0x00000000 /* No operation */
190#define CMD_CLR_EVENT 0x00000000 /* Clear event */
191#define CMD_SET_EVENT 0x10000000 /* Set signal event */
192#define CMD_PAUSE 0x20000000 /* Pause */
193#define CMD_CHECK_LATE 0x30000000 /* Check late */
194#define CMD_UPLOAD 0x40000000 /* Upload */
195#define CMD_STOP 0x50000000 /* Stop */
196#define CMD_INTERRUPT 0x60000000 /* Interrupt */
197#define CMD_JUMP 0x80000000 /* Jump */
198#define CMD_WR_REG 0x90000000 /* Write (load) register */
199#define CMD_RD_REG 0xa0000000 /* Read (store) register */
200#define CMD_WR_REG_MASK 0xc0000000 /* Write register with mask */
201
202#define CMD_OAN MASK_27
203#define CMD_INV MASK_26
204#define CMD_SIG4 MASK_25
205#define CMD_SIG3 MASK_24
206#define CMD_SIG2 MASK_23
207#define CMD_SIG1 MASK_22
208#define CMD_SIG0 MASK_21
209#define CMD_O_FID_B MASK_14
210#define CMD_E_FID_B MASK_13
211#define CMD_O_FID_A MASK_12
212#define CMD_E_FID_A MASK_11
213
214/* some events and command modifiers for rps1 squarewave generator */
215#define EVT_HS (1<<15) // Source Line Threshold reached
216#define EVT_VBI_B (1<<9) // VSYNC Event
217#define RPS_OAN (1<<27) // 1: OR events, 0: AND events
218#define RPS_INV (1<<26) // Invert (compound) event
219#define GPIO3_MSK 0xFF000000 // GPIO #3 control bits
220
221/* Bit mask constants */
222#define MASK_00 0x00000001 /* Mask value for bit 0 */
223#define MASK_01 0x00000002 /* Mask value for bit 1 */
224#define MASK_02 0x00000004 /* Mask value for bit 2 */
225#define MASK_03 0x00000008 /* Mask value for bit 3 */
226#define MASK_04 0x00000010 /* Mask value for bit 4 */
227#define MASK_05 0x00000020 /* Mask value for bit 5 */
228#define MASK_06 0x00000040 /* Mask value for bit 6 */
229#define MASK_07 0x00000080 /* Mask value for bit 7 */
230#define MASK_08 0x00000100 /* Mask value for bit 8 */
231#define MASK_09 0x00000200 /* Mask value for bit 9 */
232#define MASK_10 0x00000400 /* Mask value for bit 10 */
233#define MASK_11 0x00000800 /* Mask value for bit 11 */
234#define MASK_12 0x00001000 /* Mask value for bit 12 */
235#define MASK_13 0x00002000 /* Mask value for bit 13 */
236#define MASK_14 0x00004000 /* Mask value for bit 14 */
237#define MASK_15 0x00008000 /* Mask value for bit 15 */
238#define MASK_16 0x00010000 /* Mask value for bit 16 */
239#define MASK_17 0x00020000 /* Mask value for bit 17 */
240#define MASK_18 0x00040000 /* Mask value for bit 18 */
241#define MASK_19 0x00080000 /* Mask value for bit 19 */
242#define MASK_20 0x00100000 /* Mask value for bit 20 */
243#define MASK_21 0x00200000 /* Mask value for bit 21 */
244#define MASK_22 0x00400000 /* Mask value for bit 22 */
245#define MASK_23 0x00800000 /* Mask value for bit 23 */
246#define MASK_24 0x01000000 /* Mask value for bit 24 */
247#define MASK_25 0x02000000 /* Mask value for bit 25 */
248#define MASK_26 0x04000000 /* Mask value for bit 26 */
249#define MASK_27 0x08000000 /* Mask value for bit 27 */
250#define MASK_28 0x10000000 /* Mask value for bit 28 */
251#define MASK_29 0x20000000 /* Mask value for bit 29 */
252#define MASK_30 0x40000000 /* Mask value for bit 30 */
253#define MASK_31 0x80000000 /* Mask value for bit 31 */
254
255#define MASK_B0 0x000000ff /* Mask value for byte 0 */
256#define MASK_B1 0x0000ff00 /* Mask value for byte 1 */
257#define MASK_B2 0x00ff0000 /* Mask value for byte 2 */
258#define MASK_B3 0xff000000 /* Mask value for byte 3 */
259
260#define MASK_W0 0x0000ffff /* Mask value for word 0 */
261#define MASK_W1 0xffff0000 /* Mask value for word 1 */
262
263#define MASK_PA 0xfffffffc /* Mask value for physical address */
264#define MASK_PR 0xfffffffe /* Mask value for protection register */
265#define MASK_ER 0xffffffff /* Mask value for the entire register */
266
267#define MASK_NONE 0x00000000 /* No mask */
268
269/* register aliases */
270#define BASE_ODD1 0x00 /* Video DMA 1 registers */
271#define BASE_EVEN1 0x04
272#define PROT_ADDR1 0x08
273#define PITCH1 0x0C
274#define BASE_PAGE1 0x10 /* Video DMA 1 base page */
275#define NUM_LINE_BYTE1 0x14
276
277#define BASE_ODD2 0x18 /* Video DMA 2 registers */
278#define BASE_EVEN2 0x1C
279#define PROT_ADDR2 0x20
280#define PITCH2 0x24
281#define BASE_PAGE2 0x28 /* Video DMA 2 base page */
282#define NUM_LINE_BYTE2 0x2C
283
284#define BASE_ODD3 0x30 /* Video DMA 3 registers */
285#define BASE_EVEN3 0x34
286#define PROT_ADDR3 0x38
287#define PITCH3 0x3C
288#define BASE_PAGE3 0x40 /* Video DMA 3 base page */
289#define NUM_LINE_BYTE3 0x44
290
291#define PCI_BT_V1 0x48 /* Video/FIFO 1 */
292#define PCI_BT_V2 0x49 /* Video/FIFO 2 */
293#define PCI_BT_V3 0x4A /* Video/FIFO 3 */
294#define PCI_BT_DEBI 0x4B /* DEBI */
295#define PCI_BT_A 0x4C /* Audio */
296
297#define DD1_INIT 0x50 /* Init setting of DD1 interface */
298
299#define DD1_STREAM_B 0x54 /* DD1 B video data stream handling */
300#define DD1_STREAM_A 0x56 /* DD1 A video data stream handling */
301
302#define BRS_CTRL 0x58 /* BRS control register */
303#define HPS_CTRL 0x5C /* HPS control register */
304#define HPS_V_SCALE 0x60 /* HPS vertical scale */
305#define HPS_V_GAIN 0x64 /* HPS vertical ACL and gain */
306#define HPS_H_PRESCALE 0x68 /* HPS horizontal prescale */
307#define HPS_H_SCALE 0x6C /* HPS horizontal scale */
308#define BCS_CTRL 0x70 /* BCS control */
309#define CHROMA_KEY_RANGE 0x74
310#define CLIP_FORMAT_CTRL 0x78 /* HPS outputs formats & clipping */
311
312#define DEBI_CONFIG 0x7C
313#define DEBI_COMMAND 0x80
314#define DEBI_PAGE 0x84
315#define DEBI_AD 0x88
316
317#define I2C_TRANSFER 0x8C
318#define I2C_STATUS 0x90
319
320#define BASE_A1_IN 0x94 /* Audio 1 input DMA */
321#define PROT_A1_IN 0x98
322#define PAGE_A1_IN 0x9C
323
324#define BASE_A1_OUT 0xA0 /* Audio 1 output DMA */
325#define PROT_A1_OUT 0xA4
326#define PAGE_A1_OUT 0xA8
327
328#define BASE_A2_IN 0xAC /* Audio 2 input DMA */
329#define PROT_A2_IN 0xB0
330#define PAGE_A2_IN 0xB4
331
332#define BASE_A2_OUT 0xB8 /* Audio 2 output DMA */
333#define PROT_A2_OUT 0xBC
334#define PAGE_A2_OUT 0xC0
335
336#define RPS_PAGE0 0xC4 /* RPS task 0 page register */
337#define RPS_PAGE1 0xC8 /* RPS task 1 page register */
338
339#define RPS_THRESH0 0xCC /* HBI threshold for task 0 */
340#define RPS_THRESH1 0xD0 /* HBI threshold for task 1 */
341
342#define RPS_TOV0 0xD4 /* RPS timeout for task 0 */
343#define RPS_TOV1 0xD8 /* RPS timeout for task 1 */
344
345#define IER 0xDC /* Interrupt enable register */
346
347#define GPIO_CTRL 0xE0 /* GPIO 0-3 register */
348
349#define EC1SSR 0xE4 /* Event cnt set 1 source select */
350#define EC2SSR 0xE8 /* Event cnt set 2 source select */
351#define ECT1R 0xEC /* Event cnt set 1 thresholds */
352#define ECT2R 0xF0 /* Event cnt set 2 thresholds */
353
354#define ACON1 0xF4
355#define ACON2 0xF8
356
357#define MC1 0xFC /* Main control register 1 */
358#define MC2 0x100 /* Main control register 2 */
359
360#define RPS_ADDR0 0x104 /* RPS task 0 address register */
361#define RPS_ADDR1 0x108 /* RPS task 1 address register */
362
363#define ISR 0x10C /* Interrupt status register */
364#define PSR 0x110 /* Primary status register */
365#define SSR 0x114 /* Secondary status register */
366
367#define EC1R 0x118 /* Event counter set 1 register */
368#define EC2R 0x11C /* Event counter set 2 register */
369
370#define PCI_VDP1 0x120 /* Video DMA pointer of FIFO 1 */
371#define PCI_VDP2 0x124 /* Video DMA pointer of FIFO 2 */
372#define PCI_VDP3 0x128 /* Video DMA pointer of FIFO 3 */
373#define PCI_ADP1 0x12C /* Audio DMA pointer of audio out 1 */
374#define PCI_ADP2 0x130 /* Audio DMA pointer of audio in 1 */
375#define PCI_ADP3 0x134 /* Audio DMA pointer of audio out 2 */
376#define PCI_ADP4 0x138 /* Audio DMA pointer of audio in 2 */
377#define PCI_DMA_DDP 0x13C /* DEBI DMA pointer */
378
379#define LEVEL_REP 0x140,
380#define A_TIME_SLOT1 0x180, /* from 180 - 1BC */
381#define A_TIME_SLOT2 0x1C0, /* from 1C0 - 1FC */
382
383/* isr masks */
384#define SPCI_PPEF 0x80000000 /* PCI parity error */
385#define SPCI_PABO 0x40000000 /* PCI access error (target or master abort) */
386#define SPCI_PPED 0x20000000 /* PCI parity error on 'real time data' */
387#define SPCI_RPS_I1 0x10000000 /* Interrupt issued by RPS1 */
388#define SPCI_RPS_I0 0x08000000 /* Interrupt issued by RPS0 */
389#define SPCI_RPS_LATE1 0x04000000 /* RPS task 1 is late */
390#define SPCI_RPS_LATE0 0x02000000 /* RPS task 0 is late */
391#define SPCI_RPS_E1 0x01000000 /* RPS error from task 1 */
392#define SPCI_RPS_E0 0x00800000 /* RPS error from task 0 */
393#define SPCI_RPS_TO1 0x00400000 /* RPS timeout task 1 */
394#define SPCI_RPS_TO0 0x00200000 /* RPS timeout task 0 */
395#define SPCI_UPLD 0x00100000 /* RPS in upload */
396#define SPCI_DEBI_S 0x00080000 /* DEBI status */
397#define SPCI_DEBI_E 0x00040000 /* DEBI error */
398#define SPCI_IIC_S 0x00020000 /* I2C status */
399#define SPCI_IIC_E 0x00010000 /* I2C error */
400#define SPCI_A2_IN 0x00008000 /* Audio 2 input DMA protection / limit */
401#define SPCI_A2_OUT 0x00004000 /* Audio 2 output DMA protection / limit */
402#define SPCI_A1_IN 0x00002000 /* Audio 1 input DMA protection / limit */
403#define SPCI_A1_OUT 0x00001000 /* Audio 1 output DMA protection / limit */
404#define SPCI_AFOU 0x00000800 /* Audio FIFO over- / underflow */
405#define SPCI_V_PE 0x00000400 /* Video protection address */
406#define SPCI_VFOU 0x00000200 /* Video FIFO over- / underflow */
407#define SPCI_FIDA 0x00000100 /* Field ID video port A */
408#define SPCI_FIDB 0x00000080 /* Field ID video port B */
409#define SPCI_PIN3 0x00000040 /* GPIO pin 3 */
410#define SPCI_PIN2 0x00000020 /* GPIO pin 2 */
411#define SPCI_PIN1 0x00000010 /* GPIO pin 1 */
412#define SPCI_PIN0 0x00000008 /* GPIO pin 0 */
413#define SPCI_ECS 0x00000004 /* Event counter 1, 2, 4, 5 */
414#define SPCI_EC3S 0x00000002 /* Event counter 3 */
415#define SPCI_EC0S 0x00000001 /* Event counter 0 */
416
417/* i2c */
418#define SAA7146_I2C_ABORT (1<<7)
419#define SAA7146_I2C_SPERR (1<<6)
420#define SAA7146_I2C_APERR (1<<5)
421#define SAA7146_I2C_DTERR (1<<4)
422#define SAA7146_I2C_DRERR (1<<3)
423#define SAA7146_I2C_AL (1<<2)
424#define SAA7146_I2C_ERR (1<<1)
425#define SAA7146_I2C_BUSY (1<<0)
426
427#define SAA7146_I2C_START (0x3)
428#define SAA7146_I2C_CONT (0x2)
429#define SAA7146_I2C_STOP (0x1)
430#define SAA7146_I2C_NOP (0x0)
431
432#define SAA7146_I2C_BUS_BIT_RATE_6400 (0x500)
433#define SAA7146_I2C_BUS_BIT_RATE_3200 (0x100)
434#define SAA7146_I2C_BUS_BIT_RATE_480 (0x400)
435#define SAA7146_I2C_BUS_BIT_RATE_320 (0x600)
436#define SAA7146_I2C_BUS_BIT_RATE_240 (0x700)
437#define SAA7146_I2C_BUS_BIT_RATE_120 (0x000)
438#define SAA7146_I2C_BUS_BIT_RATE_80 (0x200)
439#define SAA7146_I2C_BUS_BIT_RATE_60 (0x300)
440
441#endif