tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 * Defines for the Atlas interrupt controller.
23 *
24 */
25#ifndef _MIPS_ATLASINT_H
26#define _MIPS_ATLASINT_H
27
28#define ATLASINT_BASE 1
29#define ATLASINT_UART (ATLASINT_BASE+0)
30#define ATLASINT_TIM0 (ATLASINT_BASE+1)
31#define ATLASINT_RES2 (ATLASINT_BASE+2)
32#define ATLASINT_RES3 (ATLASINT_BASE+3)
33#define ATLASINT_RTC (ATLASINT_BASE+4)
34#define ATLASINT_COREHI (ATLASINT_BASE+5)
35#define ATLASINT_CORELO (ATLASINT_BASE+6)
36#define ATLASINT_RES7 (ATLASINT_BASE+7)
37#define ATLASINT_PCIA (ATLASINT_BASE+8)
38#define ATLASINT_PCIB (ATLASINT_BASE+9)
39#define ATLASINT_PCIC (ATLASINT_BASE+10)
40#define ATLASINT_PCID (ATLASINT_BASE+11)
41#define ATLASINT_ENUM (ATLASINT_BASE+12)
42#define ATLASINT_DEG (ATLASINT_BASE+13)
43#define ATLASINT_ATXFAIL (ATLASINT_BASE+14)
44#define ATLASINT_INTA (ATLASINT_BASE+15)
45#define ATLASINT_INTB (ATLASINT_BASE+16)
46#define ATLASINT_ETH ATLASINT_INTB
47#define ATLASINT_INTC (ATLASINT_BASE+17)
48#define ATLASINT_SCSI ATLASINT_INTC
49#define ATLASINT_INTD (ATLASINT_BASE+18)
50#define ATLASINT_SERR (ATLASINT_BASE+19)
51#define ATLASINT_RES20 (ATLASINT_BASE+20)
52#define ATLASINT_RES21 (ATLASINT_BASE+21)
53#define ATLASINT_RES22 (ATLASINT_BASE+22)
54#define ATLASINT_RES23 (ATLASINT_BASE+23)
55#define ATLASINT_RES24 (ATLASINT_BASE+24)
56#define ATLASINT_RES25 (ATLASINT_BASE+25)
57#define ATLASINT_RES26 (ATLASINT_BASE+26)
58#define ATLASINT_RES27 (ATLASINT_BASE+27)
59#define ATLASINT_RES28 (ATLASINT_BASE+28)
60#define ATLASINT_RES29 (ATLASINT_BASE+29)
61#define ATLASINT_RES30 (ATLASINT_BASE+30)
62#define ATLASINT_RES31 (ATLASINT_BASE+31)
63#define ATLASINT_END (ATLASINT_BASE+31)
64
65/*
66 * Atlas registers are memory mapped on 64-bit aligned boundaries and
67 * only word access are allowed.
68 */
69struct atlas_ictrl_regs {
70 volatile unsigned int intraw;
71 int dummy1;
72 volatile unsigned int intseten;
73 int dummy2;
74 volatile unsigned int intrsten;
75 int dummy3;
76 volatile unsigned int intenable;
77 int dummy4;
78 volatile unsigned int intstatus;
79 int dummy5;
80};
81
82extern void atlasint_init(void);
83
84#endif /* !(_MIPS_ATLASINT_H) */