tjh.dev
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linux
1/*
2 * Hardware info about DECstation 5000/200 systems (otherwise known as
3 * 3max or KN02).
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 *
9 * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
10 * are by courtesy of Chris Fraser.
11 * Copyright (C) 2002, 2003 Maciej W. Rozycki
12 */
13#ifndef __ASM_MIPS_DEC_KN02_H
14#define __ASM_MIPS_DEC_KN02_H
15
16#ifndef __ASSEMBLY__
17#include <linux/spinlock.h>
18#include <linux/types.h>
19#endif
20
21#include <asm/addrspace.h>
22#include <asm/dec/ecc.h>
23
24
25#define KN02_SLOT_BASE KSEG1ADDR(0x1fc00000)
26#define KN02_SLOT_SIZE 0x00080000
27
28/*
29 * Address ranges decoded by the "system slot" logic for onboard devices.
30 */
31#define KN02_SYS_ROM (0*KN02_SLOT_SIZE) /* system board ROM */
32#define KN02_RES_1 (1*KN02_SLOT_SIZE) /* unused */
33#define KN02_CHKSYN (2*KN02_SLOT_SIZE) /* ECC syndrome */
34#define KN02_ERRADDR (3*KN02_SLOT_SIZE) /* bus error address */
35#define KN02_DZ11 (4*KN02_SLOT_SIZE) /* DZ11 (DC7085) serial */
36#define KN02_RTC (5*KN02_SLOT_SIZE) /* DS1287 RTC */
37#define KN02_CSR (6*KN02_SLOT_SIZE) /* system ctrl & status reg */
38#define KN02_SYS_ROM_7 (7*KN02_SLOT_SIZE) /* system board ROM (alias) */
39
40
41/*
42 * Some port addresses...
43 */
44#define KN02_DZ11_BASE (KN02_SLOT_BASE + KN02_DZ11) /* DZ11 */
45#define KN02_RTC_BASE (KN02_SLOT_BASE + KN02_RTC) /* RTC */
46#define KN02_CSR_BASE (KN02_SLOT_BASE + KN02_CSR) /* CSR */
47
48
49/*
50 * System Control & Status Register bits.
51 */
52#define KN02_CSR_RES_28 (0xf<<28) /* unused */
53#define KN02_CSR_PSU (1<<27) /* power supply unit warning */
54#define KN02_CSR_NVRAM (1<<26) /* ~NVRAM clear jumper */
55#define KN02_CSR_REFEVEN (1<<25) /* mem refresh bank toggle */
56#define KN03_CSR_NRMOD (1<<24) /* ~NRMOD manufact. jumper */
57#define KN03_CSR_IOINTEN (0xff<<16) /* IRQ mask bits */
58#define KN02_CSR_DIAGCHK (1<<15) /* diagn/norml ECC reads */
59#define KN02_CSR_DIAGGEN (1<<14) /* diagn/norml ECC writes */
60#define KN02_CSR_CORRECT (1<<13) /* ECC correct/check */
61#define KN02_CSR_LEDIAG (1<<12) /* ECC diagn. latch strobe */
62#define KN02_CSR_TXDIS (1<<11) /* DZ11 transmit disable */
63#define KN02_CSR_BNK32M (1<<10) /* 32M/8M stride */
64#define KN02_CSR_DIAGDN (1<<9) /* DIAGDN manufact. jumper */
65#define KN02_CSR_BAUD38 (1<<8) /* DZ11 38/19kbps ext. rate */
66#define KN03_CSR_IOINT (0xff<<0) /* IRQ status bits (r/o) */
67#define KN03_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */
68
69
70/*
71 * CPU interrupt bits.
72 */
73#define KN02_CPU_INR_RES_6 6 /* unused */
74#define KN02_CPU_INR_BUS 5 /* memory, I/O bus read/write errors */
75#define KN02_CPU_INR_RES_4 4 /* unused */
76#define KN02_CPU_INR_RTC 3 /* DS1287 RTC */
77#define KN02_CPU_INR_CASCADE 2 /* CSR cascade */
78
79/*
80 * CSR interrupt bits.
81 */
82#define KN02_CSR_INR_DZ11 7 /* DZ11 (DC7085) serial */
83#define KN02_CSR_INR_LANCE 6 /* LANCE (Am7990) Ethernet */
84#define KN02_CSR_INR_ASC 5 /* ASC (NCR53C94) SCSI */
85#define KN02_CSR_INR_RES_4 4 /* unused */
86#define KN02_CSR_INR_RES_3 3 /* unused */
87#define KN02_CSR_INR_TC2 2 /* TURBOchannel slot #2 */
88#define KN02_CSR_INR_TC1 1 /* TURBOchannel slot #1 */
89#define KN02_CSR_INR_TC0 0 /* TURBOchannel slot #0 */
90
91
92#define KN02_IRQ_BASE 8 /* first IRQ assigned to CSR */
93#define KN02_IRQ_LINES 8 /* number of CSR interrupts */
94
95#define KN02_IRQ_NR(n) ((n) + KN02_IRQ_BASE)
96#define KN02_IRQ_MASK(n) (1 << (n))
97#define KN02_IRQ_ALL 0xff
98
99
100#ifndef __ASSEMBLY__
101extern u32 cached_kn02_csr;
102extern spinlock_t kn02_lock;
103extern void init_kn02_irqs(int base);
104#endif
105
106#endif /* __ASM_MIPS_DEC_KN02_H */