tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * linux/include/asm-arm/arch-omap/gpio.h
3 *
4 * Defines for Multi-Channel Buffered Serial Port
5 *
6 * Copyright (C) 2002 RidgeRun, Inc.
7 * Author: Steve Johnson
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24#ifndef __ASM_ARCH_OMAP_MCBSP_H
25#define __ASM_ARCH_OMAP_MCBSP_H
26
27#include <asm/arch/hardware.h>
28
29#define OMAP730_MCBSP1_BASE 0xfffb1000
30#define OMAP730_MCBSP2_BASE 0xfffb1800
31
32#define OMAP1510_MCBSP1_BASE 0xe1011800
33#define OMAP1510_MCBSP2_BASE 0xfffb1000
34#define OMAP1510_MCBSP3_BASE 0xe1017000
35
36#define OMAP1610_MCBSP1_BASE 0xe1011800
37#define OMAP1610_MCBSP2_BASE 0xfffb1000
38#define OMAP1610_MCBSP3_BASE 0xe1017000
39
40#define OMAP_MCBSP_REG_DRR2 0x00
41#define OMAP_MCBSP_REG_DRR1 0x02
42#define OMAP_MCBSP_REG_DXR2 0x04
43#define OMAP_MCBSP_REG_DXR1 0x06
44#define OMAP_MCBSP_REG_SPCR2 0x08
45#define OMAP_MCBSP_REG_SPCR1 0x0a
46#define OMAP_MCBSP_REG_RCR2 0x0c
47#define OMAP_MCBSP_REG_RCR1 0x0e
48#define OMAP_MCBSP_REG_XCR2 0x10
49#define OMAP_MCBSP_REG_XCR1 0x12
50#define OMAP_MCBSP_REG_SRGR2 0x14
51#define OMAP_MCBSP_REG_SRGR1 0x16
52#define OMAP_MCBSP_REG_MCR2 0x18
53#define OMAP_MCBSP_REG_MCR1 0x1a
54#define OMAP_MCBSP_REG_RCERA 0x1c
55#define OMAP_MCBSP_REG_RCERB 0x1e
56#define OMAP_MCBSP_REG_XCERA 0x20
57#define OMAP_MCBSP_REG_XCERB 0x22
58#define OMAP_MCBSP_REG_PCR0 0x24
59#define OMAP_MCBSP_REG_RCERC 0x26
60#define OMAP_MCBSP_REG_RCERD 0x28
61#define OMAP_MCBSP_REG_XCERC 0x2A
62#define OMAP_MCBSP_REG_XCERD 0x2C
63#define OMAP_MCBSP_REG_RCERE 0x2E
64#define OMAP_MCBSP_REG_RCERF 0x30
65#define OMAP_MCBSP_REG_XCERE 0x32
66#define OMAP_MCBSP_REG_XCERF 0x34
67#define OMAP_MCBSP_REG_RCERG 0x36
68#define OMAP_MCBSP_REG_RCERH 0x38
69#define OMAP_MCBSP_REG_XCERG 0x3A
70#define OMAP_MCBSP_REG_XCERH 0x3C
71
72#define OMAP_MAX_MCBSP_COUNT 3
73
74#define OMAP_MCBSP_READ(base, reg) __raw_readw((base) + OMAP_MCBSP_REG_##reg)
75#define OMAP_MCBSP_WRITE(base, reg, val) __raw_writew((val), (base) + OMAP_MCBSP_REG_##reg)
76
77/************************** McBSP SPCR1 bit definitions ***********************/
78#define RRST 0x0001
79#define RRDY 0x0002
80#define RFULL 0x0004
81#define RSYNC_ERR 0x0008
82#define RINTM(value) ((value)<<4) /* bits 4:5 */
83#define ABIS 0x0040
84#define DXENA 0x0080
85#define CLKSTP(value) ((value)<<11) /* bits 11:12 */
86#define RJUST(value) ((value)<<13) /* bits 13:14 */
87#define DLB 0x8000
88
89/************************** McBSP SPCR2 bit definitions ***********************/
90#define XRST 0x0001
91#define XRDY 0x0002
92#define XEMPTY 0x0004
93#define XSYNC_ERR 0x0008
94#define XINTM(value) ((value)<<4) /* bits 4:5 */
95#define GRST 0x0040
96#define FRST 0x0080
97#define SOFT 0x0100
98#define FREE 0x0200
99
100/************************** McBSP PCR bit definitions *************************/
101#define CLKRP 0x0001
102#define CLKXP 0x0002
103#define FSRP 0x0004
104#define FSXP 0x0008
105#define DR_STAT 0x0010
106#define DX_STAT 0x0020
107#define CLKS_STAT 0x0040
108#define SCLKME 0x0080
109#define CLKRM 0x0100
110#define CLKXM 0x0200
111#define FSRM 0x0400
112#define FSXM 0x0800
113#define RIOEN 0x1000
114#define XIOEN 0x2000
115#define IDLE_EN 0x4000
116
117/************************** McBSP RCR1 bit definitions ************************/
118#define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */
119#define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */
120
121/************************** McBSP XCR1 bit definitions ************************/
122#define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */
123#define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */
124
125/*************************** McBSP RCR2 bit definitions ***********************/
126#define RDATDLY(value) (value) /* Bits 0:1 */
127#define RFIG 0x0004
128#define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */
129#define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */
130#define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */
131#define RPHASE 0x8000
132
133/*************************** McBSP XCR2 bit definitions ***********************/
134#define XDATDLY(value) (value) /* Bits 0:1 */
135#define XFIG 0x0004
136#define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */
137#define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */
138#define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */
139#define XPHASE 0x8000
140
141/************************* McBSP SRGR1 bit definitions ************************/
142#define CLKGDV(value) (value) /* Bits 0:7 */
143#define FWID(value) ((value)<<8) /* Bits 8:15 */
144
145/************************* McBSP SRGR2 bit definitions ************************/
146#define FPER(value) (value) /* Bits 0:11 */
147#define FSGM 0x1000
148#define CLKSM 0x2000
149#define CLKSP 0x4000
150#define GSYNC 0x8000
151
152/************************* McBSP MCR1 bit definitions *************************/
153#define RMCM 0x0001
154#define RCBLK(value) ((value)<<2) /* Bits 2:4 */
155#define RPABLK(value) ((value)<<5) /* Bits 5:6 */
156#define RPBBLK(value) ((value)<<7) /* Bits 7:8 */
157
158/************************* McBSP MCR2 bit definitions *************************/
159#define XMCM(value) (value) /* Bits 0:1 */
160#define XCBLK(value) ((value)<<2) /* Bits 2:4 */
161#define XPABLK(value) ((value)<<5) /* Bits 5:6 */
162#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
163
164
165/* we don't do multichannel for now */
166struct omap_mcbsp_reg_cfg {
167 u16 spcr2;
168 u16 spcr1;
169 u16 rcr2;
170 u16 rcr1;
171 u16 xcr2;
172 u16 xcr1;
173 u16 srgr2;
174 u16 srgr1;
175 u16 mcr2;
176 u16 mcr1;
177 u16 pcr0;
178 u16 rcerc;
179 u16 rcerd;
180 u16 xcerc;
181 u16 xcerd;
182 u16 rcere;
183 u16 rcerf;
184 u16 xcere;
185 u16 xcerf;
186 u16 rcerg;
187 u16 rcerh;
188 u16 xcerg;
189 u16 xcerh;
190};
191
192typedef enum {
193 OMAP_MCBSP1 = 0,
194 OMAP_MCBSP2,
195 OMAP_MCBSP3,
196} omap_mcbsp_id;
197
198typedef enum {
199 OMAP_MCBSP_WORD_8 = 0,
200 OMAP_MCBSP_WORD_12,
201 OMAP_MCBSP_WORD_16,
202 OMAP_MCBSP_WORD_20,
203 OMAP_MCBSP_WORD_24,
204 OMAP_MCBSP_WORD_32,
205} omap_mcbsp_word_length;
206
207typedef enum {
208 OMAP_MCBSP_CLK_RISING = 0,
209 OMAP_MCBSP_CLK_FALLING,
210} omap_mcbsp_clk_polarity;
211
212typedef enum {
213 OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
214 OMAP_MCBSP_FS_ACTIVE_LOW,
215} omap_mcbsp_fs_polarity;
216
217typedef enum {
218 OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
219 OMAP_MCBSP_CLK_STP_MODE_DELAY,
220} omap_mcbsp_clk_stp_mode;
221
222
223/******* SPI specific mode **********/
224typedef enum {
225 OMAP_MCBSP_SPI_MASTER = 0,
226 OMAP_MCBSP_SPI_SLAVE,
227} omap_mcbsp_spi_mode;
228
229struct omap_mcbsp_spi_cfg {
230 omap_mcbsp_spi_mode spi_mode;
231 omap_mcbsp_clk_polarity rx_clock_polarity;
232 omap_mcbsp_clk_polarity tx_clock_polarity;
233 omap_mcbsp_fs_polarity fsx_polarity;
234 u8 clk_div;
235 omap_mcbsp_clk_stp_mode clk_stp_mode;
236 omap_mcbsp_word_length word_length;
237};
238
239void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
240int omap_mcbsp_request(unsigned int id);
241void omap_mcbsp_free(unsigned int id);
242void omap_mcbsp_start(unsigned int id);
243void omap_mcbsp_stop(unsigned int id);
244void omap_mcbsp_xmit_word(unsigned int id, u32 word);
245u32 omap_mcbsp_recv_word(unsigned int id);
246
247int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
248int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
249
250/* SPI specific API */
251void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
252
253/* Polled read/write functions */
254int omap_mcbsp_pollread(unsigned int id, u16 * buf);
255int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
256
257#endif