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Linux kernel mirror (for testing)
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1/*
2 * linux/include/asm-arm/arch-omap/hardware.h
3 *
4 * Hardware definitions for TI OMAP processors and boards
5 *
6 * NOTE: Please put device driver specific defines into a separate header
7 * file for each driver.
8 *
9 * Copyright (C) 2001 RidgeRun, Inc.
10 * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
11 *
12 * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
13 * and Dirk Behme <dirk.behme@de.bosch.com>
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
34 */
35
36#ifndef __ASM_ARCH_OMAP_HARDWARE_H
37#define __ASM_ARCH_OMAP_HARDWARE_H
38
39#include <asm/sizes.h>
40#include <linux/config.h>
41#ifndef __ASSEMBLER__
42#include <asm/types.h>
43#include <asm/arch/cpu.h>
44#endif
45#include <asm/arch/io.h>
46#include <asm/arch/serial.h>
47
48/*
49 * ---------------------------------------------------------------------------
50 * Common definitions for all OMAP processors
51 * NOTE: Put all processor or board specific parts to the special header
52 * files.
53 * ---------------------------------------------------------------------------
54 */
55
56/*
57 * ----------------------------------------------------------------------------
58 * Timers
59 * ----------------------------------------------------------------------------
60 */
61#define OMAP_MPU_TIMER1_BASE (0xfffec500)
62#define OMAP_MPU_TIMER2_BASE (0xfffec600)
63#define OMAP_MPU_TIMER3_BASE (0xfffec700)
64#define MPU_TIMER_FREE (1 << 6)
65#define MPU_TIMER_CLOCK_ENABLE (1 << 5)
66#define MPU_TIMER_AR (1 << 1)
67#define MPU_TIMER_ST (1 << 0)
68
69/*
70 * ----------------------------------------------------------------------------
71 * Clocks
72 * ----------------------------------------------------------------------------
73 */
74#define CLKGEN_REG_BASE (0xfffece00)
75#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
76#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
77#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
78#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
79#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
80#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
81#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
82#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
83
84#define CK_RATEF 1
85#define CK_IDLEF 2
86#define CK_ENABLEF 4
87#define CK_SELECTF 8
88#define SETARM_IDLE_SHIFT
89
90/* DPLL control registers */
91#define DPLL_CTL (0xfffecf00)
92
93/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
94#define DSP_CONFIG_REG_BASE (0xe1008000)
95#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
96#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
97#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
98#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14)
99
100/*
101 * ---------------------------------------------------------------------------
102 * UPLD
103 * ---------------------------------------------------------------------------
104 */
105#define ULPD_REG_BASE (0xfffe0800)
106#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
107#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
108#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
109# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */
110# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */
111#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
112# define SOFT_UDC_REQ (1 << 4)
113# define SOFT_USB_CLK_REQ (1 << 3)
114# define SOFT_DPLL_REQ (1 << 0)
115#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
116#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
117#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
118#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
119#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68)
120# define DIS_MMC2_DPLL_REQ (1 << 11)
121# define DIS_MMC1_DPLL_REQ (1 << 10)
122# define DIS_UART3_DPLL_REQ (1 << 9)
123# define DIS_UART2_DPLL_REQ (1 << 8)
124# define DIS_UART1_DPLL_REQ (1 << 7)
125# define DIS_USB_HOST_DPLL_REQ (1 << 6)
126#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)
127#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
128
129/*
130 * ---------------------------------------------------------------------------
131 * Watchdog timer
132 * ---------------------------------------------------------------------------
133 */
134
135/* Watchdog timer within the OMAP3.2 gigacell */
136#define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
137#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
138#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
139#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
140#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)
141
142/*
143 * ---------------------------------------------------------------------------
144 * Interrupts
145 * ---------------------------------------------------------------------------
146 */
147#ifdef CONFIG_ARCH_OMAP1
148
149/*
150 * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
151 * or something similar.. -- PFM.
152 */
153
154#define OMAP_IH1_BASE 0xfffecb00
155#define OMAP_IH2_BASE 0xfffe0000
156
157#define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00)
158#define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04)
159#define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10)
160#define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14)
161#define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18)
162#define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c)
163#define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c)
164
165#define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00)
166#define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04)
167#define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10)
168#define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14)
169#define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18)
170#define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c)
171#define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c)
172
173#define IRQ_ITR_REG_OFFSET 0x00
174#define IRQ_MIR_REG_OFFSET 0x04
175#define IRQ_SIR_IRQ_REG_OFFSET 0x10
176#define IRQ_SIR_FIQ_REG_OFFSET 0x14
177#define IRQ_CONTROL_REG_OFFSET 0x18
178#define IRQ_ISR_REG_OFFSET 0x9c
179#define IRQ_ILR0_REG_OFFSET 0x1c
180#define IRQ_GMR_REG_OFFSET 0xa0
181
182#endif
183
184/*
185 * ----------------------------------------------------------------------------
186 * System control registers
187 * ----------------------------------------------------------------------------
188 */
189#define MOD_CONF_CTRL_0 0xfffe1080
190#define MOD_CONF_CTRL_1 0xfffe1110
191
192/*
193 * ----------------------------------------------------------------------------
194 * Pin multiplexing registers
195 * ----------------------------------------------------------------------------
196 */
197#define FUNC_MUX_CTRL_0 0xfffe1000
198#define FUNC_MUX_CTRL_1 0xfffe1004
199#define FUNC_MUX_CTRL_2 0xfffe1008
200#define COMP_MODE_CTRL_0 0xfffe100c
201#define FUNC_MUX_CTRL_3 0xfffe1010
202#define FUNC_MUX_CTRL_4 0xfffe1014
203#define FUNC_MUX_CTRL_5 0xfffe1018
204#define FUNC_MUX_CTRL_6 0xfffe101C
205#define FUNC_MUX_CTRL_7 0xfffe1020
206#define FUNC_MUX_CTRL_8 0xfffe1024
207#define FUNC_MUX_CTRL_9 0xfffe1028
208#define FUNC_MUX_CTRL_A 0xfffe102C
209#define FUNC_MUX_CTRL_B 0xfffe1030
210#define FUNC_MUX_CTRL_C 0xfffe1034
211#define FUNC_MUX_CTRL_D 0xfffe1038
212#define PULL_DWN_CTRL_0 0xfffe1040
213#define PULL_DWN_CTRL_1 0xfffe1044
214#define PULL_DWN_CTRL_2 0xfffe1048
215#define PULL_DWN_CTRL_3 0xfffe104c
216#define PULL_DWN_CTRL_4 0xfffe10ac
217
218/* OMAP-1610 specific multiplexing registers */
219#define FUNC_MUX_CTRL_E 0xfffe1090
220#define FUNC_MUX_CTRL_F 0xfffe1094
221#define FUNC_MUX_CTRL_10 0xfffe1098
222#define FUNC_MUX_CTRL_11 0xfffe109c
223#define FUNC_MUX_CTRL_12 0xfffe10a0
224#define PU_PD_SEL_0 0xfffe10b4
225#define PU_PD_SEL_1 0xfffe10b8
226#define PU_PD_SEL_2 0xfffe10bc
227#define PU_PD_SEL_3 0xfffe10c0
228#define PU_PD_SEL_4 0xfffe10c4
229
230/* Timer32K for 1610 and 1710*/
231#define OMAP_TIMER32K_BASE 0xFFFBC400
232
233/*
234 * ---------------------------------------------------------------------------
235 * TIPB bus interface
236 * ---------------------------------------------------------------------------
237 */
238#define TIPB_PUBLIC_CNTL_BASE 0xfffed300
239#define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)
240#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
241#define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)
242
243/*
244 * ----------------------------------------------------------------------------
245 * MPUI interface
246 * ----------------------------------------------------------------------------
247 */
248#define MPUI_BASE (0xfffec900)
249#define MPUI_CTRL (MPUI_BASE + 0x0)
250#define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)
251#define MPUI_DEBUG_DATA (MPUI_BASE + 0x8)
252#define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)
253#define MPUI_STATUS_REG (MPUI_BASE + 0x10)
254#define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
255#define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)
256#define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)
257
258/*
259 * ----------------------------------------------------------------------------
260 * LED Pulse Generator
261 * ----------------------------------------------------------------------------
262 */
263#define OMAP_LPG1_BASE 0xfffbd000
264#define OMAP_LPG2_BASE 0xfffbd800
265#define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00)
266#define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04)
267#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00)
268#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04)
269
270#ifndef __ASSEMBLER__
271
272/*
273 * ---------------------------------------------------------------------------
274 * Processor specific defines
275 * ---------------------------------------------------------------------------
276 */
277
278#include "omap730.h"
279#include "omap1510.h"
280
281#ifdef CONFIG_ARCH_OMAP24XX
282#include "omap24xx.h"
283#endif
284
285#include "omap16xx.h"
286
287/*
288 * ---------------------------------------------------------------------------
289 * Board specific defines
290 * ---------------------------------------------------------------------------
291 */
292
293#ifdef CONFIG_MACH_OMAP_INNOVATOR
294#include "board-innovator.h"
295#endif
296
297#ifdef CONFIG_MACH_OMAP_H2
298#include "board-h2.h"
299#endif
300
301#ifdef CONFIG_MACH_OMAP_PERSEUS2
302#include "board-perseus2.h"
303#endif
304
305#ifdef CONFIG_MACH_OMAP_H3
306#include "board-h3.h"
307#endif
308
309#ifdef CONFIG_MACH_OMAP_H4
310#include "board-h4.h"
311#endif
312
313#ifdef CONFIG_MACH_OMAP_OSK
314#include "board-osk.h"
315#endif
316
317#ifdef CONFIG_MACH_VOICEBLUE
318#include "board-voiceblue.h"
319#endif
320
321#ifdef CONFIG_MACH_NETSTAR
322#include "board-netstar.h"
323#endif
324
325#endif /* !__ASSEMBLER__ */
326
327#endif /* __ASM_ARCH_OMAP_HARDWARE_H */