tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * linux/drivers/usb/gadget/lh7a40x_udc.h
3 * Sharp LH7A40x on-chip full speed USB device controllers
4 *
5 * Copyright (C) 2004 Mikko Lahteenmaki, Nordic ID
6 * Copyright (C) 2004 Bo Henriksen, Nordic ID
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#ifndef __LH7A40X_H_
25#define __LH7A40X_H_
26
27#include <linux/config.h>
28#include <linux/module.h>
29#include <linux/kernel.h>
30#include <linux/ioport.h>
31#include <linux/types.h>
32#include <linux/version.h>
33#include <linux/errno.h>
34#include <linux/delay.h>
35#include <linux/sched.h>
36#include <linux/slab.h>
37#include <linux/init.h>
38#include <linux/timer.h>
39#include <linux/list.h>
40#include <linux/interrupt.h>
41#include <linux/proc_fs.h>
42#include <linux/mm.h>
43#include <linux/device.h>
44#include <linux/dma-mapping.h>
45
46#include <asm/byteorder.h>
47#include <asm/dma.h>
48#include <asm/io.h>
49#include <asm/irq.h>
50#include <asm/system.h>
51#include <asm/unaligned.h>
52#include <asm/hardware.h>
53
54#include <linux/usb_ch9.h>
55#include <linux/usb_gadget.h>
56
57/*
58 * Memory map
59 */
60
61#define USB_FA 0x80000200 // function address register
62#define USB_PM 0x80000204 // power management register
63
64#define USB_IN_INT 0x80000208 // IN interrupt register bank (EP0-EP3)
65#define USB_OUT_INT 0x80000210 // OUT interrupt register bank (EP2)
66#define USB_INT 0x80000218 // interrupt register bank
67
68#define USB_IN_INT_EN 0x8000021C // IN interrupt enable register bank
69#define USB_OUT_INT_EN 0x80000224 // OUT interrupt enable register bank
70#define USB_INT_EN 0x8000022C // USB interrupt enable register bank
71
72#define USB_FRM_NUM1 0x80000230 // Frame number1 register
73#define USB_FRM_NUM2 0x80000234 // Frame number2 register
74#define USB_INDEX 0x80000238 // index register
75
76#define USB_IN_MAXP 0x80000240 // IN MAXP register
77#define USB_IN_CSR1 0x80000244 // IN CSR1 register/EP0 CSR register
78#define USB_EP0_CSR 0x80000244 // IN CSR1 register/EP0 CSR register
79#define USB_IN_CSR2 0x80000248 // IN CSR2 register
80#define USB_OUT_MAXP 0x8000024C // OUT MAXP register
81
82#define USB_OUT_CSR1 0x80000250 // OUT CSR1 register
83#define USB_OUT_CSR2 0x80000254 // OUT CSR2 register
84#define USB_OUT_FIFO_WC1 0x80000258 // OUT FIFO write count1 register
85#define USB_OUT_FIFO_WC2 0x8000025C // OUT FIFO write count2 register
86
87#define USB_RESET 0x8000044C // USB reset register
88
89#define USB_EP0_FIFO 0x80000280
90#define USB_EP1_FIFO 0x80000284
91#define USB_EP2_FIFO 0x80000288
92#define USB_EP3_FIFO 0x8000028c
93
94/*
95 * USB reset register
96 */
97#define USB_RESET_APB (1<<1) //resets USB APB control side WRITE
98#define USB_RESET_IO (1<<0) //resets USB IO side WRITE
99
100/*
101 * USB function address register
102 */
103#define USB_FA_ADDR_UPDATE (1<<7)
104#define USB_FA_FUNCTION_ADDR (0x7F)
105
106/*
107 * Power Management register
108 */
109#define PM_USB_DCP (1<<5)
110#define PM_USB_ENABLE (1<<4)
111#define PM_USB_RESET (1<<3)
112#define PM_UC_RESUME (1<<2)
113#define PM_SUSPEND_MODE (1<<1)
114#define PM_ENABLE_SUSPEND (1<<0)
115
116/*
117 * IN interrupt register
118 */
119#define USB_IN_INT_EP3 (1<<3)
120#define USB_IN_INT_EP1 (1<<1)
121#define USB_IN_INT_EP0 (1<<0)
122
123/*
124 * OUT interrupt register
125 */
126#define USB_OUT_INT_EP2 (1<<2)
127
128/*
129 * USB interrupt register
130 */
131#define USB_INT_RESET_INT (1<<2)
132#define USB_INT_RESUME_INT (1<<1)
133#define USB_INT_SUSPEND_INT (1<<0)
134
135/*
136 * USB interrupt enable register
137 */
138#define USB_INT_EN_USB_RESET_INTER (1<<2)
139#define USB_INT_EN_RESUME_INTER (1<<1)
140#define USB_INT_EN_SUSPEND_INTER (1<<0)
141
142/*
143 * INCSR1 register
144 */
145#define USB_IN_CSR1_CLR_DATA_TOGGLE (1<<6)
146#define USB_IN_CSR1_SENT_STALL (1<<5)
147#define USB_IN_CSR1_SEND_STALL (1<<4)
148#define USB_IN_CSR1_FIFO_FLUSH (1<<3)
149#define USB_IN_CSR1_FIFO_NOT_EMPTY (1<<1)
150#define USB_IN_CSR1_IN_PKT_RDY (1<<0)
151
152/*
153 * INCSR2 register
154 */
155#define USB_IN_CSR2_AUTO_SET (1<<7)
156#define USB_IN_CSR2_USB_DMA_EN (1<<4)
157
158/*
159 * OUT CSR1 register
160 */
161#define USB_OUT_CSR1_CLR_DATA_REG (1<<7)
162#define USB_OUT_CSR1_SENT_STALL (1<<6)
163#define USB_OUT_CSR1_SEND_STALL (1<<5)
164#define USB_OUT_CSR1_FIFO_FLUSH (1<<4)
165#define USB_OUT_CSR1_FIFO_FULL (1<<1)
166#define USB_OUT_CSR1_OUT_PKT_RDY (1<<0)
167
168/*
169 * OUT CSR2 register
170 */
171#define USB_OUT_CSR2_AUTO_CLR (1<<7)
172#define USB_OUT_CSR2_USB_DMA_EN (1<<4)
173
174/*
175 * EP0 CSR
176 */
177#define EP0_CLR_SETUP_END (1<<7) /* Clear "Setup Ends" Bit (w) */
178#define EP0_CLR_OUT (1<<6) /* Clear "Out packet ready" Bit (w) */
179#define EP0_SEND_STALL (1<<5) /* Send STALL Handshake (rw) */
180#define EP0_SETUP_END (1<<4) /* Setup Ends (r) */
181
182#define EP0_DATA_END (1<<3) /* Data end (rw) */
183#define EP0_SENT_STALL (1<<2) /* Sent Stall Handshake (r) */
184#define EP0_IN_PKT_RDY (1<<1) /* In packet ready (rw) */
185#define EP0_OUT_PKT_RDY (1<<0) /* Out packet ready (r) */
186
187/* general CSR */
188#define OUT_PKT_RDY (1<<0)
189#define IN_PKT_RDY (1<<0)
190
191/*
192 * IN/OUT MAXP register
193 */
194#define USB_OUT_MAXP_MAXP (0xF)
195#define USB_IN_MAXP_MAXP (0xF)
196
197// Max packet size
198//#define EP0_PACKETSIZE 0x10
199#define EP0_PACKETSIZE 0x8
200#define EP0_MAXPACKETSIZE 0x10
201
202#define UDC_MAX_ENDPOINTS 4
203
204#define WAIT_FOR_SETUP 0
205#define DATA_STATE_XMIT 1
206#define DATA_STATE_NEED_ZLP 2
207#define WAIT_FOR_OUT_STATUS 3
208#define DATA_STATE_RECV 4
209
210/* ********************************************************************************************* */
211/* IO
212 */
213
214typedef enum ep_type {
215 ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt
216} ep_type_t;
217
218struct lh7a40x_ep {
219 struct usb_ep ep;
220 struct lh7a40x_udc *dev;
221
222 const struct usb_endpoint_descriptor *desc;
223 struct list_head queue;
224 unsigned long pio_irqs;
225
226 u8 stopped;
227 u8 bEndpointAddress;
228 u8 bmAttributes;
229
230 ep_type_t ep_type;
231 u32 fifo;
232 u32 csr1;
233 u32 csr2;
234};
235
236struct lh7a40x_request {
237 struct usb_request req;
238 struct list_head queue;
239};
240
241struct lh7a40x_udc {
242 struct usb_gadget gadget;
243 struct usb_gadget_driver *driver;
244 struct device *dev;
245 spinlock_t lock;
246
247 int ep0state;
248 struct lh7a40x_ep ep[UDC_MAX_ENDPOINTS];
249
250 unsigned char usb_address;
251
252 unsigned req_pending:1, req_std:1, req_config:1;
253};
254
255extern struct lh7a40x_udc *the_controller;
256
257#define ep_is_in(EP) (((EP)->bEndpointAddress&USB_DIR_IN)==USB_DIR_IN)
258#define ep_index(EP) ((EP)->bEndpointAddress&0xF)
259#define ep_maxpacket(EP) ((EP)->ep.maxpacket)
260
261#endif